Daniel Dunbar [Thu, 20 May 2010 20:20:39 +0000 (20:20 +0000)]
X86: Model i64i32imm properly, as a subclass of all immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104272
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Thu, 20 May 2010 20:20:35 +0000 (20:20 +0000)]
X86: Fix immediate type of FOO64i32 operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104271
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Thu, 20 May 2010 20:20:32 +0000 (20:20 +0000)]
tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor
it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104270
91177308-0d34-0410-b5e6-
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Dan Gohman [Thu, 20 May 2010 20:05:31 +0000 (20:05 +0000)]
Fix OptimizeShadowIV to set Changed. Change OptimizeLoopTermCond to set
Changed directly instead of using a return value.
Rename FilterOutUndesirableDedicatedRegisters's Changed variable to
distinguish it from LSRInstance's Changed member.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104269
91177308-0d34-0410-b5e6-
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Dan Gohman [Thu, 20 May 2010 20:00:41 +0000 (20:00 +0000)]
Add some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104268
91177308-0d34-0410-b5e6-
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Dan Gohman [Thu, 20 May 2010 20:00:25 +0000 (20:00 +0000)]
Simplify this code. Don't do a DomTreeNode lookup for each visited block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104267
91177308-0d34-0410-b5e6-
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Devang Patel [Thu, 20 May 2010 19:57:06 +0000 (19:57 +0000)]
Refactor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104265
91177308-0d34-0410-b5e6-
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Matt Fleming [Thu, 20 May 2010 19:45:09 +0000 (19:45 +0000)]
Grammar fix. This is a test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104264
91177308-0d34-0410-b5e6-
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Dan Gohman [Thu, 20 May 2010 19:44:23 +0000 (19:44 +0000)]
Minor code cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104263
91177308-0d34-0410-b5e6-
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Dan Gohman [Thu, 20 May 2010 19:26:52 +0000 (19:26 +0000)]
When canonicalizing icmp operand order to put the loop invariant
operand on the left, the interesting operand is on the right. This
fixes a bug where LSR was failing to recognize ICmpZero uses,
which led it to be unable to reverse the induction variable in the
attached testcase.
Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test
is extremely fragile and hard to meaningfully update.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104262
91177308-0d34-0410-b5e6-
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Mikhail Glushenkov [Thu, 20 May 2010 19:23:47 +0000 (19:23 +0000)]
llvmc: Make segfault detection work on Win32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104261
91177308-0d34-0410-b5e6-
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Dan Gohman [Thu, 20 May 2010 19:16:03 +0000 (19:16 +0000)]
Set Changed to true when canonicalizing ICmp operand order; even though
it isn't a very interesting change, it's a change nonetheless.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104260
91177308-0d34-0410-b5e6-
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Bob Wilson [Thu, 20 May 2010 18:39:53 +0000 (18:39 +0000)]
Handle Neon v2f64 and v2i64 vector shuffles as register copies.
This fixes the remaining issue with pr7167.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104257
91177308-0d34-0410-b5e6-
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Jim Grosbach [Thu, 20 May 2010 18:34:01 +0000 (18:34 +0000)]
Remove dbg_value workaround and associated command line option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104254
91177308-0d34-0410-b5e6-
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Dan Gohman [Thu, 20 May 2010 18:05:01 +0000 (18:05 +0000)]
Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn't
have a pattern and it had an invalid encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104244
91177308-0d34-0410-b5e6-
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Dale Johannesen [Thu, 20 May 2010 17:48:26 +0000 (17:48 +0000)]
The PPC MFCR instruction implicitly uses all 8 of the CR
registers. Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
vreg = MCRF CR0
MFCR <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment). That avoids all problems.
7739628.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104238
91177308-0d34-0410-b5e6-
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Devang Patel [Thu, 20 May 2010 16:49:22 +0000 (16:49 +0000)]
Strip llvm.dbg.lv also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104236
91177308-0d34-0410-b5e6-
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Dan Gohman [Thu, 20 May 2010 16:41:11 +0000 (16:41 +0000)]
Rename a variable to avoid shadowing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104234
91177308-0d34-0410-b5e6-
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Devang Patel [Thu, 20 May 2010 16:36:41 +0000 (16:36 +0000)]
Split DbgVariable. Eventually, variable info will be communicated through frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104233
91177308-0d34-0410-b5e6-
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Dan Gohman [Thu, 20 May 2010 16:23:28 +0000 (16:23 +0000)]
Minor code simplification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104232
91177308-0d34-0410-b5e6-
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Dan Gohman [Thu, 20 May 2010 16:16:00 +0000 (16:16 +0000)]
Fix assembly parsing and encoding of the pushf and popf family of
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104231
91177308-0d34-0410-b5e6-
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Dan Gohman [Thu, 20 May 2010 15:42:55 +0000 (15:42 +0000)]
Set neverHasSideEffects on 64-bit pushf and popf, for consistency with
16-bit and 32-bit pushf and popf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104228
91177308-0d34-0410-b5e6-
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Dan Gohman [Thu, 20 May 2010 15:17:54 +0000 (15:17 +0000)]
Move the code for deleting BaseRegs and LSRUses into helper functions,
and fix a bug that valgrind noticed where the code would std::swap an
element with itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104225
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Thu, 20 May 2010 14:14:22 +0000 (14:14 +0000)]
Reduce string trashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104223
91177308-0d34-0410-b5e6-
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Evan Cheng [Thu, 20 May 2010 06:13:19 +0000 (06:13 +0000)]
Add a hybrid bottom up scheduler that reduce register usage while avoiding
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104216
91177308-0d34-0410-b5e6-
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Nick Lewycky [Thu, 20 May 2010 03:30:09 +0000 (03:30 +0000)]
Fix typo in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104209
91177308-0d34-0410-b5e6-
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Dan Gohman [Thu, 20 May 2010 01:35:50 +0000 (01:35 +0000)]
Define the x86 pause instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104204
91177308-0d34-0410-b5e6-
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Dan Gohman [Thu, 20 May 2010 01:23:41 +0000 (01:23 +0000)]
Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it
doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104203
91177308-0d34-0410-b5e6-
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Eric Christopher [Thu, 20 May 2010 00:59:30 +0000 (00:59 +0000)]
Fix build by actually declaring the variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104201
91177308-0d34-0410-b5e6-
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Eric Christopher [Thu, 20 May 2010 00:49:07 +0000 (00:49 +0000)]
Partial code for emitting thread local bss data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104197
91177308-0d34-0410-b5e6-
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Bill Wendling [Thu, 20 May 2010 00:27:10 +0000 (00:27 +0000)]
Match "4" or "8" depending upon if it's 32- or 64-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104196
91177308-0d34-0410-b5e6-
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Eric Christopher [Thu, 20 May 2010 00:07:13 +0000 (00:07 +0000)]
Once more, with feeling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104190
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Wed, 19 May 2010 23:56:09 +0000 (23:56 +0000)]
lit: Add another place to look for bash.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104189
91177308-0d34-0410-b5e6-
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Dan Gohman [Wed, 19 May 2010 23:43:12 +0000 (23:43 +0000)]
Teach LSR how to cope better with unrolled loops on targets where
the addressing modes don't make this trivially easy. This allows
it to avoid falling into the less precise heuristics in more
cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104186
91177308-0d34-0410-b5e6-
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Bob Wilson [Wed, 19 May 2010 23:42:58 +0000 (23:42 +0000)]
Optimize away insertelement of an undef value. This shows up in
test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up. Radar
7998853.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104185
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Chris Lattner [Wed, 19 May 2010 23:34:33 +0000 (23:34 +0000)]
fix rdar://
7986634 - match instruction opcodes case insensitively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104183
91177308-0d34-0410-b5e6-
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Bill Wendling [Wed, 19 May 2010 23:33:26 +0000 (23:33 +0000)]
Testcase for r104181.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104182
91177308-0d34-0410-b5e6-
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Jim Grosbach [Wed, 19 May 2010 22:57:47 +0000 (22:57 +0000)]
Enable preserving debug information through post-RA scheduling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104175
91177308-0d34-0410-b5e6-
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Jim Grosbach [Wed, 19 May 2010 22:57:06 +0000 (22:57 +0000)]
Fix the post-RA instruction scheduler to handle instructions referenced by
more than one dbg_value instruction. rdar://
7759363
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104174
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Evan Cheng [Wed, 19 May 2010 22:42:23 +0000 (22:42 +0000)]
Code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104173
91177308-0d34-0410-b5e6-
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Devang Patel [Wed, 19 May 2010 21:58:28 +0000 (21:58 +0000)]
Revert r104165.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104172
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Wed, 19 May 2010 21:36:05 +0000 (21:36 +0000)]
Add support for partial redefs to the fast register allocator.
A partial redef now triggers a reload if required. Also don't add
<imp-def,dead> operands for physical superregisters.
Kill flags are still treated as full register kills, and <imp-use,kill> operands
are added for physical superregisters as before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104167
91177308-0d34-0410-b5e6-
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Devang Patel [Wed, 19 May 2010 21:26:53 +0000 (21:26 +0000)]
There is no need to maintain InsnsBeginScopeSet separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104165
91177308-0d34-0410-b5e6-
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Eric Christopher [Wed, 19 May 2010 21:19:42 +0000 (21:19 +0000)]
A more combo tls testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104163
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Wed, 19 May 2010 20:36:22 +0000 (20:36 +0000)]
Add MachineInstr::readsVirtualRegister() in preparation for proper handling of
partial redefines.
We are going to treat a partial redefine of a virtual register as a
read-modify-write:
%reg1024:6 = OP
Unless the register is fully clobbered:
%reg1024:6 = OP, %reg1024<imp-def>
MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104149
91177308-0d34-0410-b5e6-
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Eric Christopher [Wed, 19 May 2010 20:35:15 +0000 (20:35 +0000)]
Few more simple tls testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104148
91177308-0d34-0410-b5e6-
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Evan Cheng [Wed, 19 May 2010 20:19:50 +0000 (20:19 +0000)]
Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104147
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Wed, 19 May 2010 20:08:00 +0000 (20:08 +0000)]
TwoAddressInstructionPass doesn't really know how to merge live intervals when
lowering REG_SEQUENCE instructions.
Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104146
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Mikhail Glushenkov [Wed, 19 May 2010 19:24:32 +0000 (19:24 +0000)]
llvmc: report an error if a child process segfaults.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104145
91177308-0d34-0410-b5e6-
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Eric Christopher [Wed, 19 May 2010 18:59:37 +0000 (18:59 +0000)]
Attempt to run this test on x86 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104143
91177308-0d34-0410-b5e6-
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Bob Wilson [Wed, 19 May 2010 18:58:37 +0000 (18:58 +0000)]
Testcase to go with 104141.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104142
91177308-0d34-0410-b5e6-
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Bob Wilson [Wed, 19 May 2010 18:48:32 +0000 (18:48 +0000)]
When expanding a vector_shuffle, the element type may not be legal and may
need to be promoted. The BUILD_VECTOR and EXTRACT_VECTOR_ELT nodes generated
here already allow the promoted type to be used without further changes, so
just do the promotion. This fixes part of pr7167.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104141
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Wed, 19 May 2010 17:20:58 +0000 (17:20 +0000)]
MC/X86: Add missing entry for TAILJMP_1 to getRelaxedOpcode().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104122
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Wed, 19 May 2010 15:26:43 +0000 (15:26 +0000)]
MC/X86: Lower TAILCALLd[64] to JMP_1, to allow relaxation and to avoid same
prefix byte problem as in r104062.
- As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104120
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Wed, 19 May 2010 08:07:12 +0000 (08:07 +0000)]
MC/X86: Strip spurious operands from TAILJMPr64 as we do for CALL64r and
CALL64pcrel32, for the same reason.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104116
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Evan Cheng [Wed, 19 May 2010 07:28:01 +0000 (07:28 +0000)]
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104115
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Evan Cheng [Wed, 19 May 2010 07:26:50 +0000 (07:26 +0000)]
Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104114
91177308-0d34-0410-b5e6-
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Tobias Grosser [Wed, 19 May 2010 07:00:17 +0000 (07:00 +0000)]
Update autoconf/automake versions in the documentation to match the versions used in Autogen.sh
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104113
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Wed, 19 May 2010 06:20:44 +0000 (06:20 +0000)]
MC/X86: Lower MOV{8,16,32,64}{rm,mr} to fixed-register forms, as appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104112
91177308-0d34-0410-b5e6-
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Evan Cheng [Wed, 19 May 2010 06:07:03 +0000 (06:07 +0000)]
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104111
91177308-0d34-0410-b5e6-
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Evan Cheng [Wed, 19 May 2010 06:06:09 +0000 (06:06 +0000)]
Target instruction selection should copy memoperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104110
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Wed, 19 May 2010 04:31:36 +0000 (04:31 +0000)]
MC/X86: Strip spurious operands from CALL64r as we do for CALL64pcrel32, to
avoid same prefix byte problem as in r104062.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104108
91177308-0d34-0410-b5e6-
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Evan Cheng [Wed, 19 May 2010 01:52:25 +0000 (01:52 +0000)]
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104102
91177308-0d34-0410-b5e6-
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Dan Gohman [Wed, 19 May 2010 01:21:34 +0000 (01:21 +0000)]
Add a comment explaining why this code uses Append mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104095
91177308-0d34-0410-b5e6-
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Evan Cheng [Wed, 19 May 2010 01:08:17 +0000 (01:08 +0000)]
Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.
Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://
7923010.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104094
91177308-0d34-0410-b5e6-
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Dan Gohman [Wed, 19 May 2010 00:53:19 +0000 (00:53 +0000)]
Factor out the code for picking integer arithmetic with immediate
opcodes into a helper function. This fixes a few places in the code
which were not properly selecting the 8-bit-immediate opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104091
91177308-0d34-0410-b5e6-
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Eric Christopher [Wed, 19 May 2010 00:22:04 +0000 (00:22 +0000)]
Add a test to make sure that we're lowering the shift amount correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104090
91177308-0d34-0410-b5e6-
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Dan Gohman [Tue, 18 May 2010 23:55:57 +0000 (23:55 +0000)]
Add a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104089
91177308-0d34-0410-b5e6-
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Dan Gohman [Tue, 18 May 2010 23:48:08 +0000 (23:48 +0000)]
Fix the predicate which checks for non-sensical formulae which have
constants in registers which partially cancel out their immediate fields.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104088
91177308-0d34-0410-b5e6-
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Dan Gohman [Tue, 18 May 2010 23:42:37 +0000 (23:42 +0000)]
Factor out the code for recomputing an LSRUse's Regs set after some
of its formulae have been removed into a helper function, and also
teach it how to update the RegUseTracker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104087
91177308-0d34-0410-b5e6-
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Bob Wilson [Tue, 18 May 2010 23:19:42 +0000 (23:19 +0000)]
Fix a crash when debugging the coalescer. DebugValue instructions are not
in the coalescer's instruction map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104086
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Dan Gohman [Tue, 18 May 2010 22:51:59 +0000 (22:51 +0000)]
Factor out code for estimating search space complexity into a helper
function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104082
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Dan Gohman [Tue, 18 May 2010 22:41:32 +0000 (22:41 +0000)]
Add some more debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104080
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Dan Gohman [Tue, 18 May 2010 22:39:15 +0000 (22:39 +0000)]
Factor out the code for deleting a formula from an LSRUse into
a helper function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104079
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Dan Gohman [Tue, 18 May 2010 22:37:37 +0000 (22:37 +0000)]
Make some debug output more informative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104078
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Dan Gohman [Tue, 18 May 2010 22:35:55 +0000 (22:35 +0000)]
Print an error message in Formula::print if the HasBaseReg flag
is inconsistent with the BaseRegs field. It's not print's job to
assert on an invalid condition, but it can make one more obvious.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104077
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Dan Gohman [Tue, 18 May 2010 22:33:00 +0000 (22:33 +0000)]
Rename RegUseTracker's RegUses member to RegUsesMap to avoid
confusion with LSRInstance's RegUses member.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104076
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Jakob Stoklund Olesen [Tue, 18 May 2010 22:20:09 +0000 (22:20 +0000)]
Remember to update VirtRegLastUse when spilling without killing before a call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104074
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Dan Gohman [Tue, 18 May 2010 21:54:15 +0000 (21:54 +0000)]
Teach mode load folding and unfolding code about CMP32ri8 and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104068
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Bill Wendling [Tue, 18 May 2010 21:47:08 +0000 (21:47 +0000)]
Don't eliminate frame pointers from leaf functions if "--disable-fp-elim" is
specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104066
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Dan Gohman [Tue, 18 May 2010 21:42:03 +0000 (21:42 +0000)]
When converting a test to a cmp to fold a load, use the cmp that has an
8-bit immediate field rather than one with a wider immediate field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104064
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Eric Christopher [Tue, 18 May 2010 21:40:20 +0000 (21:40 +0000)]
Quick test to make sure we're emitting the tbss section correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104063
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Chris Lattner [Tue, 18 May 2010 21:40:18 +0000 (21:40 +0000)]
make mcinstlower remove all but the first operand to CALL64pcrel32.
The register use operands (e.g. the first argument is passed in a
register) is currently being modeled as a normal register use,
instead of correctly being an implicit use. This causes the operand
to get propagated onto the mcinst, which was causing the encoder to
emit a rex prefix byte, which generates an invalid call.
This fixes rdar://
7998435
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104062
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Evan Cheng [Tue, 18 May 2010 21:31:17 +0000 (21:31 +0000)]
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://
7998649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104060
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Eric Christopher [Tue, 18 May 2010 21:26:41 +0000 (21:26 +0000)]
Implement EmitTBSSSymbol for MachOStreamer.
Fixes build failure as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104059
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mike-m [Tue, 18 May 2010 21:22:12 +0000 (21:22 +0000)]
Fix enum to address array bounds regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104058
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Eric Christopher [Tue, 18 May 2010 21:16:04 +0000 (21:16 +0000)]
Make EmitTBSSSymbol take a section argument so that we can find it later.
Fix up callers and users.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104057
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Jakob Stoklund Olesen [Tue, 18 May 2010 21:10:50 +0000 (21:10 +0000)]
Properly handle multiple definitions of a virtual register in the same
instruction.
This can happen on ARM:
>> %reg1035:5<def>, %reg1035:6<def> = VLD1q16 %reg1028, 0, pred:14, pred:%reg0
Regs: Q0=%reg1032* R0=%reg1028* R1=%reg1029* R2 R3=%reg1031*
Killing last use: %reg1028
Allocating %reg1035 from QPR
Assigning %reg1035 to Q1
<< %D2<def>, %D3<def> = VLD1q16 %R0<kill>, 0, pred:14, pred:%reg0, %Q1<imp-def>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104056
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Dale Johannesen [Tue, 18 May 2010 20:47:04 +0000 (20:47 +0000)]
Test passed on ppc, to my surprise; if it worked
there it may work everywhere...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104053
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Evan Cheng [Tue, 18 May 2010 20:07:47 +0000 (20:07 +0000)]
Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104051
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Evan Cheng [Tue, 18 May 2010 20:03:28 +0000 (20:03 +0000)]
Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104050
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Dale Johannesen [Tue, 18 May 2010 19:03:51 +0000 (19:03 +0000)]
Testcase for llvm-gcc checkin 104042.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104043
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Kevin Enderby [Tue, 18 May 2010 18:09:20 +0000 (18:09 +0000)]
Incorporate Daniel's suggestion and use !isdigit(CurPtr[0]) and not
CurPtr[0] == '\n' when testing the character after a "0b" when looking
to see if it part of a something like "jmp 0b".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104039
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Kevin Enderby [Tue, 18 May 2010 17:51:35 +0000 (17:51 +0000)]
Fixed the problem with a branch to "0b" that was not parsed by llvm-mc
correctly. The Lexer was incorrectly eating the newline casusing it to branch
to address 0. Updated the test case to use a "0:" label and a branch to "0b".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104038
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Jakob Stoklund Olesen [Tue, 18 May 2010 17:31:12 +0000 (17:31 +0000)]
Teach the machine code verifier to use getSubRegisterRegClass().
The old approach was wrong. It had an off-by-one error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104034
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Daniel Dunbar [Tue, 18 May 2010 17:28:24 +0000 (17:28 +0000)]
MC/Mach-O: Implement support for setting indirect symbol table offset in section header.
Also, create symbol data for LHS of assignment, to match 'as' symbol ordering better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104033
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Daniel Dunbar [Tue, 18 May 2010 17:28:20 +0000 (17:28 +0000)]
MC/Mach-O: Remove some FIXMEs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104032
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Daniel Dunbar [Tue, 18 May 2010 17:28:17 +0000 (17:28 +0000)]
MC/Mach-O: Fail faster/harder when we see .file, which isn't yet supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104031
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Daniel Dunbar [Tue, 18 May 2010 17:22:24 +0000 (17:22 +0000)]
MC/X86: Implement custom lowering to make sure we match things like
X86::ADC32ri $0, %eax
to
X86::ADC32i32 $0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104030
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Daniel Dunbar [Tue, 18 May 2010 17:22:19 +0000 (17:22 +0000)]
llc (et al): Add support for --show-encoding and --show-inst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104029
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