Add getFeatureBits to extract feature bits for a given CPU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134298 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the confusing getDarwinNumber() api and friends.

Part of rdar://9714064

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134291 91177308-0d34-0410-b5e6-96231b3b80d8

Take a stab at fixing the llvm-x86_64-linux-checks failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134287 91177308-0d34-0410-b5e6-96231b3b80d8

TargetConstant immediates won't be placed into registers so tighten
up the valid constant check earlier.

rdar://9692967

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134286 91177308-0d34-0410-b5e6-96231b3b80d8

Add initial *-*-rtems* target, from Joel Sherrill

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134282 91177308-0d34-0410-b5e6-96231b3b80d8

Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8

Add MCSubtargetInfo target registry stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134279 91177308-0d34-0410-b5e6-96231b3b80d8

Teach IVUsers to stop at non-affine expressions unless they are both
outside the loop and reducible.

This more completely hides them from LSR, which isn't usually able to
do anything meaningful with non-affine expressions anyway, and this
consequently hides them from SCEVExpander, which is acutely unprepared
for non-affine expressions.

Replace test/CodeGen/X86/lsr-nonaffine.ll with a new test that tests
the new behavior.

This works around the bug in PR10117 / rdar://problem/9633149, and is
generally an improvement besides.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134268 91177308-0d34-0410-b5e6-96231b3b80d8

Generalize @llvm.ctlz, @llvm.cttz, and @llvm.ctpop to work on vectors of integers, and fix the one optimization pass that I'm aware of that needs updating for this.  At least one current target, ARM NEON, can implement these operations on vectors directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134265 91177308-0d34-0410-b5e6-96231b3b80d8

Calling-convention specifications for illegal types are no-ops.  Simplify based on this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134264 91177308-0d34-0410-b5e6-96231b3b80d8

ARMv7M vs. ARMv7E-M support.

The DSP instructions in the Thumb2 instruction set are an optional extension
in the Cortex-M* archtitecture. When present, the implementation is considered
an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation."

Add a subtarget feature hook for the v7e-m instructions and hook it up. The
cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is
a v7e-m implementation.

rdar://9572992

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134261 91177308-0d34-0410-b5e6-96231b3b80d8

Rename TargetSubtarget to TargetSubtargetInfo for consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8

- Added MCSubtargetInfo to capture subtarget features and scheduling
  itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
  and hide more details from targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8

Fix off-by-one error.

(low two bits always zero, so off by one bit of encoded value).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134247 91177308-0d34-0410-b5e6-96231b3b80d8

Hide the call to InitMCInstrInfo into tblgen generated ctor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8

Pseudo-ize t2MOVCC[ri].

t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them.
The Thumb1 versions, tMOVCC[ri] were only present for use by the size-
reduction pass, so they're no longer necessary at all and can be deleted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134242 91177308-0d34-0410-b5e6-96231b3b80d8

Eliminate one extra conversion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134240 91177308-0d34-0410-b5e6-96231b3b80d8

Disable commit 134216 ("Add 134199 back, but disable the optimization when the second
copy is a kill") to see if it fixes the i386 dragonegg buildbot, which is timing out
because gcc built with dragonegg is going into an infinite loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134237 91177308-0d34-0410-b5e6-96231b3b80d8

Another misuse of StringRef. MSVC is very sensitive to that kind of error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134236 91177308-0d34-0410-b5e6-96231b3b80d8

Fix likely typo, reduce number of instruction name collisions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134235 91177308-0d34-0410-b5e6-96231b3b80d8

Fix use after free.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134234 91177308-0d34-0410-b5e6-96231b3b80d8

Avoid DenseMap lookup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134231 91177308-0d34-0410-b5e6-96231b3b80d8

Fix off by one error. I misunderstood the comment about killedAt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134229 91177308-0d34-0410-b5e6-96231b3b80d8

Check the liveinterval, not the kill flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134228 91177308-0d34-0410-b5e6-96231b3b80d8

Don't inflate register classes used by inline asm.

The constraints are represented by the register class of the original
virtual register created for the inline asm. If the register class were
included in the operand descriptor, we might be able to do this.

For now, just give up on regclass inflation when inline asm is involved.

No test case, this bug hasn't happened yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134226 91177308-0d34-0410-b5e6-96231b3b80d8

Improve Mips back-end's handling of DBG_VALUE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134224 91177308-0d34-0410-b5e6-96231b3b80d8

Improve constant folding of undef for cmp and select operators.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134223 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for the 'j' immediate constraint. This is conditionalized on
supporting the instruction that the constraint is for 'movw'.

Part of rdar://9119939

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134222 91177308-0d34-0410-b5e6-96231b3b80d8

Improve constant folding of undef for binary operators.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134221 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for the ARM 't' register constraint. And another testcase
for the 'x' register constraint.

Part of rdar://9119939

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134220 91177308-0d34-0410-b5e6-96231b3b80d8

Switch SubtargetFeatures from std::string to StringRef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134219 91177308-0d34-0410-b5e6-96231b3b80d8

We'll return a null RC by default if we can't match.

Part of rdar://9119939

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134217 91177308-0d34-0410-b5e6-96231b3b80d8

Add 134199 back, but disable the optimization when the second copy is a kill.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134216 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for the 'x' constraint.

Part of rdar://9307836 and rdar://9119939

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134215 91177308-0d34-0410-b5e6-96231b3b80d8

Remove tabs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134212 91177308-0d34-0410-b5e6-96231b3b80d8

Capitalize the unsigned part of the initializer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134211 91177308-0d34-0410-b5e6-96231b3b80d8

Rename Pair to RCPair lacking any better naming ideas.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134210 91177308-0d34-0410-b5e6-96231b3b80d8

Improve comment: Show the register the DWARF label is added to.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134209 91177308-0d34-0410-b5e6-96231b3b80d8

Use the correct registers on X86_64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134208 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a problem with fast-isel return values introduced in r134018.

We would put the return value from long double functions in the wrong
register.

This fixes gcc.c-torture/execute/conversion.c

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134205 91177308-0d34-0410-b5e6-96231b3b80d8

Refact ARM Thumb1 tMOVr instruction family.

Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134204 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for the 'h' constraint.

Part of rdar://9119939

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134203 91177308-0d34-0410-b5e6-96231b3b80d8

Add target a target hook to get the register number used by the compact unwind
encoding for the registers it knows about. Return -1 if it can't handle that
register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134202 91177308-0d34-0410-b5e6-96231b3b80d8

Revert my previous patch while I debug llvm-gcc bootstrap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134201 91177308-0d34-0410-b5e6-96231b3b80d8

Add one more comment to the FDE verbose asm output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134200 91177308-0d34-0410-b5e6-96231b3b80d8

Don't give up on coalescing A and B when we find

A = X
B = X

Instead, proceed as if we had found

A = X
B = A

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134199 91177308-0d34-0410-b5e6-96231b3b80d8

Add a convenience typedef for std::pair<unsigned, const TargetRegisterClass*>.

No functional change.

Part of rdar://9119939

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134198 91177308-0d34-0410-b5e6-96231b3b80d8

Thumb1 register to register MOV instruction is predicable.

Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134197 91177308-0d34-0410-b5e6-96231b3b80d8

Add comments to the FDE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134196 91177308-0d34-0410-b5e6-96231b3b80d8

Add more comments to the ASM output for the CIE's "moves".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134194 91177308-0d34-0410-b5e6-96231b3b80d8

Tweak error messages to match GCC. Should fix gcc.target/i386/pr30848.c

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134193 91177308-0d34-0410-b5e6-96231b3b80d8

Add comments to the ASM output to help understand the compact unwind and CIE tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134191 91177308-0d34-0410-b5e6-96231b3b80d8

Create a isFullCopy predicate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134189 91177308-0d34-0410-b5e6-96231b3b80d8

Add r134057 back, but splice the predecessor after the successors phi
nodes.

Original message:
Let simplify cfg simplify bb with only debug and lifetime intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134182 91177308-0d34-0410-b5e6-96231b3b80d8

Pseudo-ize the Thumb tTPsoft instruction.

It's just a call to a special helper function. Get rid of the T2 variant
entirely, as it's identical to the Thumb1 version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134178 91177308-0d34-0410-b5e6-96231b3b80d8

indvars -disable-iv-rewrite: handle cloning binary operators that cannot overflow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134177 91177308-0d34-0410-b5e6-96231b3b80d8

Pseudo-ize the t2LDMIA_RET instruction.

It's just a t2LDMIA_UPD instruction with extra codegen properties, so it
doesn't need the encoding information. As a side-benefit, we now correctly
recognize for instruction printing as a 'pop' instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134173 91177308-0d34-0410-b5e6-96231b3b80d8

Pseudo-ize the Thumb tPOP_RET instruction.

It's just a tPOP instruction with additional code-gen properties, so it
doesn't need encoding information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134172 91177308-0d34-0410-b5e6-96231b3b80d8

Remove dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134148 91177308-0d34-0410-b5e6-96231b3b80d8

The enum was moved to ISDOpcodes.h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134134 91177308-0d34-0410-b5e6-96231b3b80d8

Kill dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134131 91177308-0d34-0410-b5e6-96231b3b80d8

Size reducing SP adjusting t2ADDri needs to check predication.

tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the
predicate is anything other than "always."

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134130 91177308-0d34-0410-b5e6-96231b3b80d8

Fix ARMSubtarget feature parsing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134129 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.

The fix is to just have the clients explictly pass the CPU name!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8

Recognize the xstorerng alias for VIA PadLock's xstore instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134126 91177308-0d34-0410-b5e6-96231b3b80d8

Reapply r134047 now that the world is ready for it.

This patch will sometimes choose live range split points next to
interference instead of always splitting next to a register point. That
means spill code can now appear almost anywhere, and it was necessary
to fix code that didn't expect that.

The difficult places were:

- Between a CALL returning a value on the x87 stack and the
  corresponding FpPOP_RETVAL (was FpGET_ST0). Probably also near x87
  inline assembly, but that didn't actually show up in testing.

- Between a CALL popping arguments off the stack and the corresponding
  ADJCALLSTACKUP.

Both are fixed now. The only place spill code can't appear is after
terminators, see SplitAnalysis::getLastSplitPoint.

Original commit message:

Rewrite RAGreedy::splitAroundRegion, now with cool ASCII art.

This function has to deal with a lot of special cases, and the old
version got it wrong sometimes. In particular, it would sometimes leave
multiple uses in the stack interval in a single block. That causes bad
code with multiple reloads in the same basic block.

The new version handles block entry and exit in a single pass. It first
eliminates all the easy cases, and then goes on to create a local
interval for the blocks with difficult interference. Previously, we
would only create the local interval for completely isolated blocks.

It can happen that the stack interval becomes completely empty because
we could allocate a register in all edge bundles, and the new local
intervals deal with the interference. The empty stack interval is
harmless, but we need to remove a SplitKit assertion that checks for
empty intervals.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134125 91177308-0d34-0410-b5e6-96231b3b80d8

indvars -disable-iv-rewrite: handle an edge case involving identity phis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134124 91177308-0d34-0410-b5e6-96231b3b80d8

Remove getRegClassForInlineAsmConstraint and all dependencies.

Fixes rdar://9643582

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134123 91177308-0d34-0410-b5e6-96231b3b80d8

Make sure we use the correct register class here since we'll need to
care about spill values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134122 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a small thinko for constant i64 lock/orq optimization where we
we didn't have an opcode for 64-bit constant or expressions.

Fixes rdar://9692967

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134121 91177308-0d34-0410-b5e6-96231b3b80d8

* Use the proper size to output the range size.
* Rough in the compact encoding part.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134119 91177308-0d34-0410-b5e6-96231b3b80d8

Stupid error: If the LSDA and Personality functions aren't there, emit 0 instead
of the encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134117 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r133953 for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134116 91177308-0d34-0410-b5e6-96231b3b80d8

We don't want to use relocations inside the compact unwind section. Just use the
symbols instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134115 91177308-0d34-0410-b5e6-96231b3b80d8

Remove redundant Thumb2 ADD/SUB SP instruction definitions.

Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the
stack pointer. It can just use the normal add-register-immediate encoding
since it can use all registers as a source, not just R0-R7. The extra
instruction definitions are just duplicates of the normal instructions with
the (not well enforced) constraint that the source register was SP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134114 91177308-0d34-0410-b5e6-96231b3b80d8

Always adjust the stack pointer immediately after the call.

Some x86-32 calls pop values off the stack, and we need to readjust the
stack pointer after the call. This happens when ADJCALLSTACKUP is
eliminated.

It could happen that spill code was inserted between the CALL and
ADJCALLSTACKUP instructions, and we would compute wrong stack pointer
offsets for those frame index references.

Fix this by inserting the stack pointer adjustment immediately after the
call instead of where the ADJCALLSTACKUP instruction was erased.

I don't have a test case since we don't currently insert code in that
position. We will soon, though. I am testing a regalloc patch that
didn't work on Linux because of this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134113 91177308-0d34-0410-b5e6-96231b3b80d8

indvars -disable-iv-rewrite: insert new trunc instructions carefully.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134112 91177308-0d34-0410-b5e6-96231b3b80d8

Added IRBuilder::SetInsertPoint(Use) to find a valid insertion point
that dominates the given Use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134111 91177308-0d34-0410-b5e6-96231b3b80d8

whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134110 91177308-0d34-0410-b5e6-96231b3b80d8

In the ARM global merging pass, allow extraneous alignment specifiers. This pass
already makes the assumption, which is correct on ARM, that a type's alignment is
less than its alloc size. This improves codegen with Clang (which inserts a lot of
extraneous alignment specifiers) and fixes <rdar://problem/9695089>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134106 91177308-0d34-0410-b5e6-96231b3b80d8

ARM RSCS* don't need explicit TableGen decoder checks.

They've been pseudos for a while now, so the decoder will never see
them in the first place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134101 91177308-0d34-0410-b5e6-96231b3b80d8

Indentation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134100 91177308-0d34-0410-b5e6-96231b3b80d8

Remove getRegClassForInlineAsmConstraint from the ARM port.

Part of rdar://9643582

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134095 91177308-0d34-0410-b5e6-96231b3b80d8

Remove todo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134094 91177308-0d34-0410-b5e6-96231b3b80d8

make compose and isMoveInstr static functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134093 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor away tSpill and tRestore pseudos in ARM backend.

The tSpill and tRestore instructions are just copies of the tSTRspi and
tLDRspi instructions, respectively. Just use those directly instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134092 91177308-0d34-0410-b5e6-96231b3b80d8

Add a TODO for the Alpha port inline asm constraints.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134089 91177308-0d34-0410-b5e6-96231b3b80d8

Move Alpha from getRegClassForInlineAsmConstraint to
getRegForInlineAsmConstraint.

Part of rdar://9643582

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134088 91177308-0d34-0410-b5e6-96231b3b80d8

Update comment for getRegForInlineAsmConstraint for Mips.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134087 91177308-0d34-0410-b5e6-96231b3b80d8

Move the Blackfin port away from getRegClassForInlineAsmConstraint by
creating a few specific register classes.

Part of rdar://9643582

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134086 91177308-0d34-0410-b5e6-96231b3b80d8

Remove getRegClassForInlineAsmConstraint from MBlaze. Add a TODO comment
for the port.

Part of rdar://9643582

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134085 91177308-0d34-0410-b5e6-96231b3b80d8

Remove getRegClassForInlineAsmConstraint for Mips.

Part of rdar://9643582

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134084 91177308-0d34-0410-b5e6-96231b3b80d8

Remove getRegClassForInlineAsmConstraint from sparc.

Part of rdar://9643582

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134083 91177308-0d34-0410-b5e6-96231b3b80d8

Move XCore from getRegClassForInlineAsmConstraint to
getRegForInlineAsmConstraint.

Part of rdar://9643582

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134080 91177308-0d34-0410-b5e6-96231b3b80d8

Use getRegForInlineAsmConstraint instead of custom defining regclasses
via vectors.

Part of rdar://9643582

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134079 91177308-0d34-0410-b5e6-96231b3b80d8

Add missing operand. rdar://9694169

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134078 91177308-0d34-0410-b5e6-96231b3b80d8

Temporarily revert r134057: "Let simplify cfg simplify bb with only debug and
lifetime intrinsics" due to buildbot failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134071 91177308-0d34-0410-b5e6-96231b3b80d8

Asm parser range checking on .<size> <value> directives.

For example, ".byte 256" would previously assert() when emitting an object
file. Now it generates a diagnostic that the literal value is out of range.

rdar://9686950

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134069 91177308-0d34-0410-b5e6-96231b3b80d8

Don't depend on the optimization reverted in r134067.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134068 91177308-0d34-0410-b5e6-96231b3b80d8

Revert a part of r126557 which could create unschedulable DAGs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134067 91177308-0d34-0410-b5e6-96231b3b80d8