LSR needs to remember inserted instructions even in postinc mode, because
there could be multiple subexpressions within a single expansion which
require insert point adjustment. This fixes PR7306.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105510 91177308-0d34-0410-b5e6-96231b3b80d8

Fix some liveout handling related to tail calls, see comments.
I don't think this ever resulted in problems on x86, but it
would on ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105509 91177308-0d34-0410-b5e6-96231b3b80d8

Implement operator== and operator!= for SetVector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105508 91177308-0d34-0410-b5e6-96231b3b80d8

test case for r105504.
Radar 8055687.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105505 91177308-0d34-0410-b5e6-96231b3b80d8

Re-apply 105308 with fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105502 91177308-0d34-0410-b5e6-96231b3b80d8

Don't track users of undef values; they aren't interesting for
register pressure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105501 91177308-0d34-0410-b5e6-96231b3b80d8

Make if-conversion ignore dbg_value instructions in its analysis. rdar://7797940

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105498 91177308-0d34-0410-b5e6-96231b3b80d8

Handle multi-vector returns and args.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105496 91177308-0d34-0410-b5e6-96231b3b80d8

Update docs to reflect new DISubprogram elements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105495 91177308-0d34-0410-b5e6-96231b3b80d8

Support for nested functions/classes in debug output.  Radar 7424645.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105492 91177308-0d34-0410-b5e6-96231b3b80d8

Copy location info for current function argument from dbg.declare if respective store instruction does not have any location info.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105490 91177308-0d34-0410-b5e6-96231b3b80d8

Additional fixes to BuiltinsARM.def generator, on to clang codegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105488 91177308-0d34-0410-b5e6-96231b3b80d8

More tail call removal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105485 91177308-0d34-0410-b5e6-96231b3b80d8

Skip dbg_value instructions when scanning instructions in register scavenging.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105481 91177308-0d34-0410-b5e6-96231b3b80d8

Fix normalization and de-normalization of non-affine SCEVs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105480 91177308-0d34-0410-b5e6-96231b3b80d8

Keep track of the call instructions whose clobber lists were skipped during fast
register allocation.

Process all of the clobber lists at the end of the function, marking the
registers as used in MachineRegisterInfo.

This is necessary in case the calls clobber callee-saved registers (sic).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105473 91177308-0d34-0410-b5e6-96231b3b80d8

More thoroughly disable tails calls by default.
8060143, although this doesn't fix the real problem with tail call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105472 91177308-0d34-0410-b5e6-96231b3b80d8

Another fix to prevent debug info from affecting codegen. rdar://7797940

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105470 91177308-0d34-0410-b5e6-96231b3b80d8

Progress on generating BuiltinsARM.def, still some duplicates to work out.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105461 91177308-0d34-0410-b5e6-96231b3b80d8

BuiltinsARM.def emitter, still needs a substantial bit of tweaking to lighten the load on clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105456 91177308-0d34-0410-b5e6-96231b3b80d8

more dbg_value adjustments so debug info doesn't affect codegen

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105454 91177308-0d34-0410-b5e6-96231b3b80d8

Fixed a bug during widening where we would avoid legalizing a node.  When we
replace an OpA with a widened OpB, it is possible to get new uses of OpA due to CSE
when recursively updating nodes.  Since OpA has been processed, the new uses are
not examined again.  The patch checks if this occurred and it it did, updates the
new uses of OpA to use OpB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105453 91177308-0d34-0410-b5e6-96231b3b80d8

Remove more tail calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105450 91177308-0d34-0410-b5e6-96231b3b80d8

Remove a tail call, and move some CHECKs to the
functions where they belong.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105449 91177308-0d34-0410-b5e6-96231b3b80d8

Mangle __builtin_neon_* names appropriately.
Add skeleton of support for emitting the list of prototypes for BuiltinsARM.def

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105443 91177308-0d34-0410-b5e6-96231b3b80d8

No need to special-case structs here; structs are first-class now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105442 91177308-0d34-0410-b5e6-96231b3b80d8

fix typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105441 91177308-0d34-0410-b5e6-96231b3b80d8

This test doesn't need the ssp attribute.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105440 91177308-0d34-0410-b5e6-96231b3b80d8

For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and
VECTOR_SHUFFLEs to REG_SEQUENCE instructions.  The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized.  That is pretty awful, but I guess it
makes sense for other targets.  Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105439 91177308-0d34-0410-b5e6-96231b3b80d8

Remove tail call.  A tail call version will follow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105438 91177308-0d34-0410-b5e6-96231b3b80d8

Add some missing checks in TwoAddressInstructionPass::CoalesceExtSubRegs.
Check that all the instructions are in the same basic block, that the
EXTRACT_SUBREGs write to the same subregs that are being extracted, and that
the source and destination registers are in the same regclass.  Some of
these constraints can be relaxed with a bit more work.  Jakob suggested
that the loop that checks for subregs when NewSubIdx != 0 should use the
"nodbg" iterator, so I made that change here, too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105437 91177308-0d34-0410-b5e6-96231b3b80d8

Cleanup 80-column and trim trailing whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105435 91177308-0d34-0410-b5e6-96231b3b80d8

Teach the ARM load-store optimizer to deal with dbg_value instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105427 91177308-0d34-0410-b5e6-96231b3b80d8

Remove tail call to preserve this test.  A tail
call version will follow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105422 91177308-0d34-0410-b5e6-96231b3b80d8

Make this test not use tail calls.  A tail call
version will follow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105419 91177308-0d34-0410-b5e6-96231b3b80d8

Add some additional capabilities to the neon emitter

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105416 91177308-0d34-0410-b5e6-96231b3b80d8

Add a emit-llvm option to the plugin and make the path argument to also-emit-llvm optional.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105414 91177308-0d34-0410-b5e6-96231b3b80d8

Early implementation of tail call for ARM.
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105413 91177308-0d34-0410-b5e6-96231b3b80d8

Fix SimplifyDemandedBits' AssertZext logic to demand all the bits. It
needs to demand the high bits because it's asserting that they're zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105406 91177308-0d34-0410-b5e6-96231b3b80d8

Revert 105308.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105399 91177308-0d34-0410-b5e6-96231b3b80d8

Perfer !string.empty() over string != "".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105397 91177308-0d34-0410-b5e6-96231b3b80d8

Forgot to update the most important part of the gtest modifications readme.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105396 91177308-0d34-0410-b5e6-96231b3b80d8

Whitespace cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105395 91177308-0d34-0410-b5e6-96231b3b80d8

Disable pthread support in googletest if llvm was configured without threads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105390 91177308-0d34-0410-b5e6-96231b3b80d8

Don't preserve all symbols in a .so and instead trust gold to know what is
needed. The result is that now we are able to drop unnecessary symbol from
shared libraries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105389 91177308-0d34-0410-b5e6-96231b3b80d8

Machine sink could potentially sink instructions into a block where the physical
registers it defines then interfere with an existing preg live range.

For instance, if we had something like these machine instructions:

BB#0
  ... = imul ... EFLAGS<imp-def,dead>
  test ..., EFLAGS<imp-def>
  jcc BB#2 EFLAGS<imp-use>

BB#1
  ... ; fallthrough to BB#2

BB#2
  ... ; No code that defines EFLAGS
  jcc ... EFLAGS<imp-use>

Machine sink will come along, see that imul implicitly defines EFLAGS, but
because it's "dead", it assumes that it can move imul into BB#2. But when it
does, imul's "dead" imp-def of EFLAGS is raised from the dead (a zombie) and
messes up the condition code for the jump (and pretty much anything else which
relies upon it being correct).

The solution is to know which pregs are live going into a basic block. However,
that information isn't calculated at this point. Nor does the LiveVariables pass
take into account non-allocatable physical registers. In lieu of this, we do a
*very* conservative pass through the basic block to determine if a preg is live
coming out of it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105387 91177308-0d34-0410-b5e6-96231b3b80d8

Turns out gtest still prefers the system <tr1/tuple> over it's own
implementation. Force the internal one to unbreak clang selfhost on linux.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105386 91177308-0d34-0410-b5e6-96231b3b80d8

Add first pass at darwin tls compiler support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105381 91177308-0d34-0410-b5e6-96231b3b80d8

arm_neon.h now makes it through clang and generates appropriate code for those functions which can use
generic vector operators rather than __builtin_neon_*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105380 91177308-0d34-0410-b5e6-96231b3b80d8

One underscore, not two.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105379 91177308-0d34-0410-b5e6-96231b3b80d8

Implement expansion in type legalization for add/sub with overflow.  The
expansion is the same as that used by LegalizeDAG.

The resulting code sucks in terms of performance/codesize on x86-32 for a
64-bit operation; I haven't looked into whether different expansions might be
better in general.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105378 91177308-0d34-0410-b5e6-96231b3b80d8

Remove some already-fixed README entries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105377 91177308-0d34-0410-b5e6-96231b3b80d8

Remove README entry which no longer compiles to something sane.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105376 91177308-0d34-0410-b5e6-96231b3b80d8

Remove a fixed item, update a couple partially-fixed items.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105375 91177308-0d34-0410-b5e6-96231b3b80d8

Use the fast register allocator by default for -O0 builds.

This affects both llvm-gcc and clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105372 91177308-0d34-0410-b5e6-96231b3b80d8

Use readsWritesVirtualRegister instead of counting uses and defs when inserting
spills and reloads.

This means that a partial define of a register causes a reload so the other
parts of the register are preserved.

The reload can be prevented by adding an <imp-def> operand for the full
register. This is already done by the coalescer and live interval analysis where
relevant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105369 91177308-0d34-0410-b5e6-96231b3b80d8

Add full register <imp-def> operands when the coalescer is creating partial
register updates.

These operands tell the spiller that the other parts of the partially defined
register are don't-care, and a reload is not necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105361 91177308-0d34-0410-b5e6-96231b3b80d8

Speedup bitcode writer. Do not walk all values for all functions to emit function local metadata. In one testcase, probably worst case scenario, the 70x speed up is seen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105360 91177308-0d34-0410-b5e6-96231b3b80d8

Compulsive reformating. No functionalitical changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105359 91177308-0d34-0410-b5e6-96231b3b80d8

Slightly change the meaning of the reMaterialize target hook when the original
instruction defines subregisters.

Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.

Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:

  %reg1234:foo = FLAP %reg1234<imp-def>

will reMaterialize(%reg3333, bar) like this:

  %reg3333:bar-foo = FLAP %reg333:bar<imp-def>

Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8

Update Readme and Makefiles for the new gtest.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105355 91177308-0d34-0410-b5e6-96231b3b80d8

Merge gtest-1.5.0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105354 91177308-0d34-0410-b5e6-96231b3b80d8

Merge gtest-1.4.0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105353 91177308-0d34-0410-b5e6-96231b3b80d8

Merge gtest-1.3.0.

OSX users: make sure that CrashReporter is disabled when running unit tests.
Death tests are enabled now so you'll get a ton of message boxes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105352 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up 80 column violations. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8

arm_neon.h emitter now mostly complete for the purposes of initial testing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105349 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the TargetRegisterClass member from CalleeSavedInfo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8

Fix comment so it doesn't include comments which are irrelevant to the x86
backend.  Add a FIXME noting what can be fixed here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105342 91177308-0d34-0410-b5e6-96231b3b80d8

Use comments to document non-obvious code rather than
mailing list archives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105341 91177308-0d34-0410-b5e6-96231b3b80d8

Skip identical instruction while calculating DBG_VALUE range.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105340 91177308-0d34-0410-b5e6-96231b3b80d8

Rename canCombinedSubRegIndex method to something more grammatically correct
and tidy up the comment describing it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105339 91177308-0d34-0410-b5e6-96231b3b80d8

Replace ARM's getCalleeSavedRegClasses with a simpler solution

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105335 91177308-0d34-0410-b5e6-96231b3b80d8

remove trailing whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105333 91177308-0d34-0410-b5e6-96231b3b80d8

Use local small vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105332 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unused function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105325 91177308-0d34-0410-b5e6-96231b3b80d8

Not all entries in the range will have an SUnit. Check for that when looking
for debug information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105324 91177308-0d34-0410-b5e6-96231b3b80d8

Update the documentation, getCalleeSavedRegClasses is not required anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105323 91177308-0d34-0410-b5e6-96231b3b80d8

cleanup

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105322 91177308-0d34-0410-b5e6-96231b3b80d8

Remove uses of getCalleeSavedRegClasses from outside the
backends and removes the virtual declaration. With that out of the way
I should be able to cleanup one backend at a time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105321 91177308-0d34-0410-b5e6-96231b3b80d8

Pacify recent gcc: remove a pointless const qualifier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105318 91177308-0d34-0410-b5e6-96231b3b80d8

Checkpoint; handle 'int' and 'void' correctly

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105316 91177308-0d34-0410-b5e6-96231b3b80d8

Emit full function prototypes.  Definitions & typedefs to come.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105315 91177308-0d34-0410-b5e6-96231b3b80d8

Enable machine cse of instructions which define physical registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105308 91177308-0d34-0410-b5e6-96231b3b80d8

Checkpoint arm_neon.h generation with tablegen

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105307 91177308-0d34-0410-b5e6-96231b3b80d8

Don't try to custom-lower 64-bit add-with-overflow and friends on x86-32; the
x86 backend currently doesn't know how to handle them.

This doesn't really fix anything because LegalizeTypes doesn't know how to
handle them either.  We do get a better error message, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105305 91177308-0d34-0410-b5e6-96231b3b80d8

Fix an obvious mistake: don't change the operands until all of them have been
checked and it is safe to proceed with the changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105304 91177308-0d34-0410-b5e6-96231b3b80d8

Remove outdated README entries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105303 91177308-0d34-0410-b5e6-96231b3b80d8

Update debug information when breaking anti-dependencies. rdar://7759363

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105300 91177308-0d34-0410-b5e6-96231b3b80d8

Fix comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105297 91177308-0d34-0410-b5e6-96231b3b80d8

DwarfWrite is now smart enough to drop debug value pointing to undefined register.  Update this test to avoid this.

iSel not properly lowring argument into a well formed DBG_VALUE in some cases is a separate issue and not related to the test in this testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105295 91177308-0d34-0410-b5e6-96231b3b80d8

Properly compose subregister indices when coalescing.
The comment about ordering of subreg indices is no longer true.
This exposed a bug in the new substVirtReg method that is also fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105294 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unused code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105293 91177308-0d34-0410-b5e6-96231b3b80d8

Ignore line number of debug value in undefined register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105292 91177308-0d34-0410-b5e6-96231b3b80d8

fix think-o

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105291 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the allocation of shadow space for the Win64 calling convention
in X86FastISel. Patch by Jan Sjodin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105290 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify things a bit more. Fix prototype to use SmallVectorImpl and
change a few SmallVectors to vanilla C arrays.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105289 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the noalias checking so that it doesn't worry about
an argument aliasing itself. Thanks Duncan!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105288 91177308-0d34-0410-b5e6-96231b3b80d8

Keep track of incoming debug value of unused argument.
Radar 7927666.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105285 91177308-0d34-0410-b5e6-96231b3b80d8

Fill in missing support for ISD::FEXP, ISD::FPOWI, and friends.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105283 91177308-0d34-0410-b5e6-96231b3b80d8

Add a FIXME

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105282 91177308-0d34-0410-b5e6-96231b3b80d8