clk: rockchip: rk3399: Add CLK_SET_RATE_PARENT for main VOP0

We recommend, VOP0 is the main screen, VOP1 is a sub screen,
only VOP0 is able to re-set parent (VPLL) rate.

Change-Id: If40f95ce18e73477df8f7f031013333a603d5eb2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: rk3399: Modify dummy clock for VOP dclks

Because frac div need to more than 20 multiple between the numerator
and denominator, but we need to be fit many HDMI/DP freqs and may
bring serious jitter when the dclk_vopx below the dclk_vopx_frac.

Therefore, we can select dclk_vopx below the dclk_vopx_div directly.

Change-Id: If3d9051211f0b160a507f0942667796f043f4ec2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Correct BCLK inversion for DSP DAI format mode

By default the device latches data on the falling edge of the
BCLK in DSP mode, whereas the expectation for normal BCLK is to
latch on the rising edge. This updates the driver to invert the
BCLK configuration for DSP mode, to align with expected behaviour.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 4acfa36be618eb8ac3aa39f473e7550710216435)

Change-Id: I646f6ec9fb377ce95d90d57c80dc05f13b6696f2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Add regmap patch to support old silicon

Initial silicon did not have master bias enabled by default, unlike
later HW, so use regmap patch to align with newer defaults.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit abd7c894fc41a9a674354e10ed6c55413e1db077)

Change-Id: I1b941c779320b58110b78c2c127bb08629c7a3fa
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Remove support for 32KHz PLL mode

PLL mode based on 32KHz master clock not supported in
AB silicon so remove support from the driver.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 501f72e9c5205b9d70d5d61e9b186ae7ba873f73)

Change-Id: Ie3e3388af33a74fca6bf60405e1b54b860b43f18
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Add support for 1.6V micbias level

HW can provide 1.6V micbias level as well the existing levels
already provided in the driver. This patch adds support for 1.6V
to the DT binding.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 0aed64c1766d354c819a13a57d8673adaf2266eb)

Change-Id: I714fb76154242aa6392143ebe8db20a7510b45a3
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Remove internal LDO features of codec

In AB silicon, the internal LDO is not supported so remove
DT and driver references to this (digital voltage direct from
'VDD' supply)

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit d8ef140dccc1645aa37a140ed7585458294210b8)

Change-Id: I540c28a7dd0994c5dd94889c2cc0f566f8fddb63
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Update REFERENCES reg default, in-line with HW

In current AB silicon, BIAS_EN field is enabled by default in the
REFERENCES register, so the regmap default value should reflect
this.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 9ff099790412cb46536efba02039b36d81300976)

Change-Id: I8eabb89f669e02c6bda6ecee0b4253367082a59f
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Disable regulators on probe() failure

If codec probe() function fails after supplies have been enabled
it should really tidy up and disable them again. This patch updates
the probe function to do just that.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 9069bf9bc839d97e07fe17c336eab095c1065cec)

Change-Id: I3eebc1ff3af1b4f07fd564cc5d054ab0d6c43ad0
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Fix Sidetone to work regardless of DAI capture

Previously Sidetone would operate only when capture to DAI was in
progress, due to DAPM path configuration. There is no reason why
this should not operate without DAI capture, so this patch updates
the DAPM path accordingly.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit fdd50a8086422caa456b5f8abb631dda6c551744)

Change-Id: I167dfe2bf18d696a01b8261b0fb0bb7a7569ec21
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Use logical instead of bitwise OR for boolean expression

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit a737447d080929c54c664adc9c62eadab9e86d3e)

Change-Id: I7b41ffe3d8144b1d4fa43dbf13e324f2f8d409ad
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

dt/bindings: rockchip-thermal: Support the RK3366 SoCs compatible

This patchset attempts to new compatible for thermal founding
on RK3366 SoCs.

Change-Id: Ida2a46f0c8dfb8f9e99c8c7ba488be07dac8a5e8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: dts: rockchip: Change PWM regulators to 300kHz for gru base

Apparently the time constant for for the PWM regulator circuit on
gru-based devices is different than EVB.  Let's run at 300kHz which
should make us work well.

BUG=None
TEST=None

Change-Id: I0973f416d026de27908c3ef527c1e9274b967fc8
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/254648
Reviewed-by: Stephen Barber <smbarber@google.com>
Tested-by: Doug Anderson <dianders@google.com>

video: rockchip: vop: 3399: enable auto gating

Change-Id: I78e1f2b0c90545f0bb9e33b98979f8c102b123b5
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

ARM64: dts: rk3399: add "rockchip,grf" for i2s0

Change-Id: I8f275e960db8fe180d769fd7f081a379f8ace1a2
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

UPSTREAM: ASoC: rockchip: i2s: configure the sdio pins' iomux mode

There are 3 i2s sdio pins, which iomux mode is as follows:

 - sdi3_sdo1
 - sdi2_sdo2
 - sdi1_sdo3

we need to configure these pins' iomux mode via the GRF register
when use multi channel playback/capture.

Change-Id: I95f01f425931d8fb826f33d5dad87ef8aa2b8b6e
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org broonie/sound.git topic/rockchip
 commit 72b7ba1f1477f1b9b0a3ddf2dd4b5392ce88a8a3)

UPSTREAM: ASoC: rockchip: add playback property

rockchip,playback-channels: max playback channels, 8 channels default.

Change-Id: I0db92ad3d3270e46bb98a2977163869251c32f2d
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 7fd9093a7570f5d8bbdc8014c0a349da2afea97e)

clk: rockchip: rk3399: add softreset ID for gpu

Change-Id: I19613ee4a35f3a61c4f02f30449ce9e389bb7162
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

usb: dwc3: add functions to set force mode

Add functions to set force mode for host and device.
These functions will check the current mode and only
force if needed thus avoiding unnecessary force mode
delays. It's useful for dwc3 controller on some platforms
which don't support otg mode but support drd mode,
like rk3399 platform.

TEST=config dr_mode = "otg" in dts first, and do
"echo device > mode" on usb debugfs dir to force device mode,
do "echo host > mode" on usb debugfs dir to force host mode.

Change-Id: I1f90ac9d1ee3daa19c1046b0e52fdfb8f2d2ad62
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

drm/panel: simple: Add support for LG LP097QX1-SPA1 2048x1536 panel

The LG LP097QX1-SPA1 is an 9.7", 2048x1536 (QXGA) TFT-LCD panel
connected using eDP interfaces.

Change-Id: I3a279ff9e4dde421832e2f9fe8152ddfbadab2ae
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

dt-bindings: add LG LP097QX1-SPA1 panle binding

The LG LP097QX1-SPA1 is an 9.7", 2048x1536 (QXGA) TFT-LCD panel
connected using eDP interfaces.

Change-Id: I09554d0c2afcce744e959878c7cd9d9950b35a17
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM64: dts: rk3399: assign VOP parent and rate for ACLK/HCLK

Change-Id: Ifcce7764eb709386e40140c58299468ea835fd8c
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: [media] media/core: Replace ctrl_class with which

Replace the obsolete field ctrl_class with "which".

Make sure it not used in future modules by commenting out the field with
ifndef __KERNEL_ .

The field cannot be simply removed because that would be change on the
kenel API to the userspace (and we don't like that).

Change-Id: I21bfb7c2a4b553e74765213fd99c381d8b609cc0
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Signed-off-by: Alpha Lin <alpha.lin@rock-chips.com>
(cherry picked from commit 0f8017bebf3efd3dcb115bf8a3f883b3123019ee)

UPSTREAM: [media] videodev2.h: Extend struct v4l2_ext_controls

So it can be used to get the default value of a control.

Without this change it is not possible to get the
default value of array controls.

Change-Id: I4370b7f2a40a08f28648f8dcaa3d84405db12523
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Signed-off-by: Alpha Lin <alpha.lin@rock-chips.com>
(cherry picked from commit 35ec2a2fa5a362b07b590ae1568dc35e47a7b846)

video: rockchip: vop: 3399: fix win lite disp size error

Change-Id: I8874026dfd75353c129418a29d860499773e2ebb
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: update for dsp output mode

Change-Id: I3558b90bea9cdad7954d17004c08cfc2c2c53aa0
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: update for CABC

Change-Id: I6e93d0e8daedf8a1c671ebbc28719da0296083da
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: add property for hwc layer

Change-Id: I012603cb216419b41a79470ebc26c8525d6a7326
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

ARM64: dts: rk3399-fb: make sure vop big probe first

Change-Id: I16f966aeadbc6a97c128c0c750863495d0fa46c0
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: update for write back function

Change-Id: I5c0ceb6797211a1384de7174f158288209d03dd2
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

ARM64: dts: rk3399-monkey: add pstore node

Change-Id: Ie4e3a3c390807c5d0559eee3d0627a5dae2bd9b3
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

ARM64: rockchip_defconfig: enable pstore

Change-Id: Ieda4ab0d02287c24c3c346ddefdbcf12c03eaf43
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

net: stmmac: replace msleep with mdelay between spinlock and spinunlock

stmmac_mdio_reset()
{
...
msleep()
...
}

stmmac_resume()
{
...
spin_lock_irqsave()
...
stmmac_mdio_reset()
...
spin_unlock_irqrestore()
}

The code above will cause the following crash when resuming.

[   50.988242] Call trace:
[   50.988489] [<ffffffc0000883b0>] dump_backtrace+0x0/0x104
[   50.988979] [<ffffffc0000884c8>] show_stack+0x14/0x1c
[   50.989440] [<ffffffc0003033f8>] dump_stack+0x90/0xb0
[   50.989899] [<ffffffc0000bb4d4>] __schedule_bug+0x44/0x5c
[   50.990388] [<ffffffc000949d00>] __schedule+0x90/0x6d8
[   50.990851] [<ffffffc00094a44c>] schedule+0x90/0xb0
[   50.991295] [<ffffffc00094cdbc>] schedule_timeout+0x1f0/0x254
[   50.991812] [<ffffffc00094ce90>] schedule_timeout_uninterruptible+0x20/0x28
[   50.992437] [<ffffffc0000ef2ac>] msleep+0x18/0x24
[   50.992870] [<ffffffc0004b2fc0>] stmmac_mdio_reset+0x120/0x194
[   50.993397] [<ffffffc0004b1c40>] stmmac_resume+0x118/0x134
[   50.993893] [<ffffffc0004b64bc>] stmmac_pltfr_resume+0x30/0x3c
[   50.994421] [<ffffffc00045b44c>] platform_pm_resume+0x2c/0x54
[   50.994943] [<ffffffc000465350>] dpm_run_callback+0xa8/0x1e0
[   50.995452] [<ffffffc000465fd4>] device_resume+0x158/0x190
[   50.995945] [<ffffffc000466178>] dpm_resume+0x16c/0x364
[   50.996417] [<ffffffc000466384>] dpm_resume_end+0x14/0x28
[   50.996905] [<ffffffc0000d8bfc>] suspend_devices_and_enter+0x114/0x2f4
[   50.997489] [<ffffffc0000d93c8>] pm_suspend+0x5ec/0x658
[   50.997960] [<ffffffc0000d7748>] state_store+0x50/0x88
[   50.998427] [<ffffffc000305594>] kobj_attr_store+0x18/0x28
[   50.998926] [<ffffffc0001ec038>] sysfs_kf_write+0x44/0x4c
[   50.999414] [<ffffffc0001eb3f4>] kernfs_fop_write+0x110/0x16c
[   50.999935] [<ffffffc00018d208>] __vfs_write+0x28/0xd0
[   51.000400] [<ffffffc00018d464>] vfs_write+0xb0/0x180
[   51.000858] [<ffffffc00018d600>] SyS_write+0x48/0x84
[   51.001311] [<ffffffc0000844b0>] el0_svc_naked+0x24/0x28
[   51.066648] ERROR stmmaceth/eth0, debugfs create directory failed
[   51.067196] stmmac_hw_setup: failed debugFS registration

Change-Id: Iee92ac9bae18a6e8fb980434c7004dd33b43b638
Signed-off-by: roger <roger.chen@rock-chips.com>

ARM64: CrOS: defconfig: update defconfig for chromeos

The CONFIG_ANDROID_PARANOID_NETWORK will block network access on ChromeOS.
Disable it on CrOS.

CONFIG_DRM_DMA_SYNC can be used to synchronize CPU/GPU access to a buffer.

Change-Id: Ia979af42b8693161c854e1987122d49c8737b51c
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>

CHROMIUM: drm/rockchip: add GEM CPU acquire/release ioctls

These ioctls can be used to synchronize CPU/GPU access to a buffer.

BUG=chrome-os-partner:33438
TEST=add CONFIG_DRM_DMA_SYNC=y, in conjunction with xf86-video-armsoc change,\
run any X application, like xev

Change-Id: I8065ec465ebd0cb6abe128a3e7d92a8f74a88928
Signed-off-by: Dominik Behr <dbehr@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229441
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Conflicts:
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
drivers/gpu/drm/rockchip/rockchip_drm_gem.c
(cherry picked from cros/chromeos-3.14 commit a847e1f492cbd186116c01a3f56575320dc87152)
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>

CHROMIUM: drm/rockchip: Add GEM create ioctl support

Rockchip Socs have GPU, we need allocate GPU accelerated buffers.
So add special ioctls GEM_CREATE/GEM_MAP_OFFSET to support
accelerated buffers.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
BUG=chromium:399935
TEST=With rest of patch set, can boot to UI on eDP

Change-Id: Ia4b13798aac97d16214da7a75a2479e6e334313e
Reviewed-on: https://chromium-review.googlesource.com/222153
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
Commit-Queue: Daniel Kurtz <djkurtz@chromium.org>
Conflicts:
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
(cherry picked from cros/chromeos-3.14 commit c29c5a3037e18815937d8af664738e499ada94d1)
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>

CHROMIUM: drm: add helpers for fence and reservation based dma-buf sync

BUG=chromium:395901
TEST=emerge-veyron chromeos-kernel-3_14, deploy and boot kernel

Change-Id: I0cdf6d23e9f4924128d4de77c0f3ed7589766bb8
Signed-off-by: Dominik Behr <dbehr@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218381
Conflicts:
drivers/gpu/drm/Makefile
(cherry picked from cros/chromeos-3.14 commit 0adee464da8094c70469514dd96799c1797f77b0)
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>

drm: rockchip: analogix_dp: split the lcdc select setting into device data

eDP controller need to declare which vop provide the video source,
and it's defined in GRF registers.

But the specific GRF register address is different between RK3288
and RK3399, so we need to create a device data to declare the GRF
messages for each CPU chips.

Change-Id: I695d1c729f5605d9e913c82453d311ed97c79a94
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

clk: rockchip: rk3399: move VOP clock to other PLLs

We hope to be able to HDMI/DP can obtain better signal quality,
therefore, we move VOP pwm and aclk clocks to other PLLs, let
HDMI/DP phyclock can monopolize VPLL.

Change-Id: Ib715f9d29c0743d113f9f74886ff3921c9e0a327
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: config: enable the REGULATOR_PWM for rockchip

That's useful for every PWM controlled to adjust the voltage
regulators.

In the moment. We make savedefconfig to cleanup the rockchuip_cros_defconfig.

Change-Id: I33d68d6cd48310b2da0ea2c3331380e71fc51eee
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: gru: fix up the pwm regulator node

This attempts to model commit 063e65397a89 ("ARM64: dts: rk3399-tb: fix
up the pwm regulator node").

Note that instead of putting a duty cycle of 25000 ns (40 kHz) I've set
a duty cycle of 1667 ns (600 kHz) because I think that's what the TRM
says.

Change-Id: Ifc209eddb20122feec96c5e86f7a14da7d74eb3f
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rk3399-chrome: delete unused code in dts

We shouldn't need them in here if you are using the coreboot/firmware.
In general, the cmdline/memory/logic_center will be overwrited
since the coreboot will do that.

Change-Id: I3902ff4eb71891b5c6320bed4355992e699e4835
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rk3399-monkey: add iep dts resource for android

Add the iep dts resource for android platform.

Change-Id: Ibb624fe0ad5253fb026d3470b52f76bc61cdb960
Signed-off-by: alpha.lin <alpha.lin@rock-chips.com>

ARM64: dts: rk3399: gru: enable eDP display nodes

Change-Id: I1548fdebfb9bb3ac98e309a3becfa16216e94ede
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM64: dts: rk3399: remove aclk_usb3_noc which is ignored unused

Change-Id: Ie864933514db3f1117ea67bd06549ad145514bef
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

clk: rockchip: rk3399: add SCLK_PCIEPHY_REF100M for PCIe

Change-Id: Iead548d47a627745267acbcc73d401f73c68a702
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: dts: rk3399: add eDP device node

Change-Id: I0b1bb874b51f45d71f63445cb30c43f94b022c20
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm/bridge: analogix_dp: hardcode input video format to RGB10 for Rockchip platform

Rockchip LCD controller could only output the RGB101010 video
format, so just hardcode the eDP input video format to that.

Change-Id: I39673a35b439656dff7e3358b65ec835c92c4120
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

net: phy: add sysfs node for reading PHY's registers

Change-Id: I76468dd235a39b6f79699b1cc931c2c7bb7bdbc5
Signed-off-by: roger <roger.chen@rock-chips.com>

ARM64: dts: rk3399-tb: change "ext_gmac" to "clkin_gmac" according to clk-rk3399.c

Change-Id: Ic0ea696408493aae97099d579d34ae33f30cc41a
Signed-off-by: roger <roger.chen@rock-chips.com>

ARM64: dts: rk3399: fix drive strength to 13mA for GMAC TXD pins

Change-Id: Ia5a45864d2f71bd7548cc5b897c33265a20c4fea
Signed-off-by: roger <roger.chen@rock-chips.com>

clk: rockchip: rk3399: remove unnecessary CLK_IGNORE_UNUSED flags

remove unnecessary CLK_IGNORE_UNUSED flags for m0.

Change-Id: Iba9daf76980c969b90700c175bfa5fec044f3524
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3399: remove unnecessary CLK_IGNORE_UNUSED flags

remove unnecessary CLK_IGNORE_UNUSED flags for uart4/gpio/timer.

Change-Id: I6046dd8d12cc78363d4e653bcad78671746a3914
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: rockchip_defconfig: enable IPA and CPU_THERMAL

Change-Id: Ia70704b3e77041231f02246ad1a230a45d4b930f
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

clk: rockchip: rk3399: add SCLK_RMII_SRC for gmac

Change-Id: I0b678b60ab99ba8166866a7f664314055f55c606
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

mfd: RK808: update the "pm_power_off" initalization conditons

Only the powerofff callback feature is supported through the
rockchip,system-power-controller.

Change-Id: I55e73c05a749edab6c3710e304ee86c03812ab6f
Signed-off-by: Shengfei xu <xsf@rock-chips.com>

include: drm: rockchip_drm.h: remove those old unsued file

Thoes file were introduced by Commit bdafdac384d56555736584775236dbd817a1cdda
(rk3288 chromium: drm grafic fb support for x11 mali gpu), for now we have the
mainline rockchip drm code, no need those old head files, let's removed them.

Change-Id: I325a5b7981ac5478349f276f8811b1b51e40c564
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

video: rockchip: mipi: add long packet support for linux-4.4

Change-Id: I0f226f0caabe100c6c41c9b0b23f80a2c61f7f4f
Signed-off-by: xubilv <xbl@rock-chips.com>

ARM64: dts: gru: Put back in TODO comments + recent SD work

This DTS purposely has some comments in "//" style to indicate bringup
work that needs to be done.  Don't remove them unless the issues have
been addressed.

The DTS that landed in Rockchip's tree also lost some recent SD work.

Change-Id: I388cfe855b52aa160c1e8d1b468d7e8f35207790
Signed-off-by: Douglas Anderson <dianders@chromium.org>

ARM64: dts: rk3399-monkey: enable iommu and vop lite

Change-Id: I6cb75f09c99ffe76691ceb61d60774256663e72e
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: update hdmi RGB101010 output and csc parameter

Change-Id: I7428da925c78f68f418ff5669b08c8cfd44808b6
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: update for iommu

Change-Id: Ic4550a2534fd016b6fff7e47f8d89ec239beba10
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: rk322x: check hwc_size before H/W register config

Check hwc_size after hwc registor config, if check fail, would cause
unexpect problem, iommu crash.

Change-Id: I2e18ea86e9e27e13ccce0737d9d48befcbe345fb
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

video: rockchip: vop: 3399: add win2 and win3 when get dsp_info

Change-Id: Ib1ae76de66656b0531683eede117346945587008
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: add to config YUYV and UYVY data format

Change-Id: I5762f691d724449035098333a732095774c96513
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: fb: add support data format YUYV and UYVY

Change-Id: Iaef1a0e6f80e4246cfe6b2692bdb6085ea5355b0
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: add support afbdc

Change-Id: I2e796809baeef99c3463c4789a65eb1057cb577f
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

thermal: rockchip: fixes the code_to_temp for tsadc driver

We should judge the table.id[mid].code insearch algorithm on matter the
adc value increment or decrement.

Or otherwise, the temperature return the incorrect value in some cases.
[    1.438589] adc_val=402,temp=-40000
[    1.438903] adc_val=403,temp=-39375
[    1.439217] adc_val=404,temp=-38750
...
[    1.441102] adc_val=410,temp=-40000
[    1.441416] adc_val=411,temp=-34445
[    1.441737] adc_val=412,temp=-33889
...

Let's fix it right now.

Fixes commit 020ba95
"thermal: rockchip: Add the sort mode for adc value increment or decrement"

Change-Id: Icac84d06ebf463439ca11db5a19d629b4b2b865c
Reported-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rk3399: the USB 2.0 vbus GPIO is board specific

A GPIO was put in rk3399.dtsi that doesn't belong there.  Specifically
this GPIO isn't the same for all rk3399 boards.  I presume it belongs in
rk3399-tb.dts, so move it there.

Change-Id: I0b3272655da565eb6b348a33401f7517224db5fa
Fixes: 3ed499f07cf7 ("ARM64: dts: rockchip: rk3399: add usb2.0 phy node")
Signed-off-by: Douglas Anderson <dianders@chromium.org>

ARM64: rockchip_cros_defconfig: Add support DRM for cros

And removed:
----
-CONFIG_FB=y
-CONFIG_LCDC_RK3368=y
-CONFIG_LCDC_LITE_RK3X=y
-CONFIG_RK_IOMMU=y
-CONFIG_RK_IOVMM=y
----
which are unused on the chromeos.

Change-Id: Icd521b56b6285099d72d3bf25575466792b6d353
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

vcodec_service/rockchip: revise build failure

there will be a build failure when CONFIG_RK_IOMMU
disabled.

Change-Id: Ifd56e39b9cb3021f308f195087304a1d1ec2c599
Signed-off-by: alpha lin <alpha.lin@rock-chips.com>

ARM64: dts: rk3399-tb: fix up the pwm regulator node

add pwm init voltage and id for uboot.
fix up the pwms node and add pwm polarity.

Change-Id: I4159c97ae498411ab958c2b1e1223139ac670452
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

Makefile: hack out the double version of SUBLEVEL

Portage's linux-info.eclass (in getfilevar_noexec) looks for the
definition of SUBLEVEL, and it doesn't expect 2 definitions. We could
fix the eclass, but let's hack this out for now.

See strongswan's emerge output:

...
 * Found sources for kernel version:
 *     4.4.6
 * 0
/mnt/host/source/src/third_party/portage-stable/eclass/linux-info.eclass: line 388: 6
0: syntax error in expression (error token is "0")
...

Change-Id: I6964e6731ed461ca3a8c4afde0ddfe48e0105627
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/252620
Reviewed-by: Doug Anderson <dianders@google.com>
Tested-by: Doug Anderson <dianders@google.com>

ARM64: rockchip_cros_defcofnig: turn on the chrome platform

This config should be opened since the config used for chromeos.

Change-Id: I52dd22b1c1a707e6d27311337a5be6f0041cb7f9
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

clk: rockchip: rk3399: remove unnecessary critical clocks

Change-Id: If1f3cf9eb91f89ad38f034b5a9d90571c486efc9
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: rk3399: add all of NOCs into critical clocks

We need to declare that we enable all NOCs which are critical clocks
always and clearly and explicitly show that we have enabled them at
clk_summary.

Change-Id: I859664692b4d1bb0dda0ee38295dfcbc3cc70019
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: rk3399: Keep DMAC1 enable always for SPI5

Change-Id: I4b2b8bdf7649b0c5209852160597ad2737ed5a7b
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: rk3399: remove unnecessary CLK_IGNORE_UNUSED flags

Change-Id: I87dddf2ceb14e5d094b320568530ae8976fdbf14
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: dts: rk3399: remove clk_ignore_unused

Change-Id: I48874e2b82487d5e9ae6e83c954ea2bd06960c8f
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

Input: touchscreen-gt9xx: enable the gt9xx SLOT REPORT

On the moment, the gt9xx touchscreen driver can't work on chromeos.
Since the driver report event has *not* judge correct by the chromeos.

We need report the singel point touch information for event firstly,
otherwise the chromeos will force a signel point to work.

That's seem a chromeos issue/leak.
Anyway, we can report the point including the signal information
to workaround.

Verify on rk3399evb board with chromeos.

root@localhost / # evtest
No device specified, trying to scan all of /dev/input/event*
Available devices:
/dev/input/event0:      goodix-ts
/dev/input/event1:      rk29-keypad
Select the device event number [0-1]: 0
Input driver version is 1.0.1
Input device ID: bus 0x18 vendor 0xdead product 0xbeef version 0x28bb
Input device name: "goodix-ts"
Supported events:
  Event type 0 (EV_SYN)
  Event type 1 (EV_KEY)
  Event code 330 (BTN_TOUCH)
  Event type 3 (EV_ABS)
  Event code 0 (ABS_X)
  ...

  Event: time 1450321044.293221, type 3 (EV_ABS), code 57 (ABS_MT_TRACKING_ID), value 0
  Event: time 1450321044.293221, type 3 (EV_ABS), code 53 (ABS_MT_POSITION_X), value 4095
  Event: time 1450321044.293221, type 3 (EV_ABS), code 54 (ABS_MT_POSITION_Y), value 4083
  Event: time 1450321044.293221, type 3 (EV_ABS), code 48 (ABS_MT_TOUCH_MAJOR), value 8
  Event: time 1450321044.293221, type 3 (EV_ABS), code 50 (ABS_MT_WIDTH_MAJOR), value 8
  Event: time 1450321044.293221, -------------- SYN_REPORT ------------
  Event: time 1450321044.384655, type 3 (EV_ABS), code 57 (ABS_MT_TRACKING_ID), value -1
  Event: time 1450321044.384655, -------------- SYN_REPORT ------------

Change-Id: Ic41327a673632e471429ded35b68eecbbd7f3069
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rk3399: chrome: enable mipi node

Change-Id: Icc169b97ec985b5e7332ed1ed5ed78d20c717062
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

ARM64/cros_defconfig: remove IEP and RK_VCODEC

Remove CONFIG_IEP and CONFIG_RK_VCODEC definition for
they aren't required in rockchip chromeos.

Change-Id: I3a0bce0943931a7546378fb7c7e663e1317b93da
Signed-off-by: alpha lin <alpha.lin@rock-chips.com>

iep/rockchip: revise build fail when CONFIG_RK_IOMMU disabled

When CONFIG_RK_IOMMU disabled, iep build will throw out error
information for some mismatch definitions.

Change-Id: I0fb22550eaaebd62523d794e45de7b94fae8db63
Signed-off-by: alpha lin <alpha.lin@rock-chips.com>

ARM64: config: enable DRM relevant config

Change-Id: Id86ee59190b4f45d5e0e3e8e114920ec28b3fa8e
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

ARM64: dts: rk3399: add mipi node

Change-Id: I06562ff3b62efa38f84ac892513725dcf4559471
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

Document: update dw_mipi_dsi document for RK3399

There is a phy config clock in RK3399, it must be control by mipi
driver.

Change-Id: I5c029b79ae5867b652ab761dc7416f78f8e070d2
Signed-off-by: Chris Zhong <zyw@rock-chips.com>

DRM/rockchip: mipi: add a phy config clock control

Thers is a phy config clock in RK3399, it must be enable before phy
init, and be disable after phy init.

Change-Id: Idb2d4c85f5284065c3f1d540d9e2fddf5565040d
Signed-off-by: Chris Zhong <zyw@rock-chips.com>

drm/rockchip: fix compile warning

fix warning:
    warning: format '%x' expects argument of type 'unsigned int',
    but argument 2 has type 'size_t'

Change-Id: Ifab0d16f0229aa3d5fc244678298fa2138bd4aa1
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

ARM64: dts: rk3399-tb: add wifi/sdio/sdcard support

Change-Id: Id5b97f2eb3b1bd2eeb42882743a3e64f59d45128
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

DRM: mipi: support rk3399 mipi dsi

The vopb/vopl switch register of rk3399 mipi is different from rk3288,
the default setting for mipi dsi mode is different too, so add a
of_device_id structure to distinguish them, and make sure set the
correct mode before mipi phy init.

Change-Id: I54542752dddd1b28fc0500c0a763f14c29fe98f0
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

ARM64: rockchip: rk3399: clk: fix i2c4 and i2c8 gate-register

Fix a typo making the sclk_i2c4 and sclk_i2c8 access a
wrong register bit offset to handle its gate.

Change-Id: I836244b8e14aa34ef44241c8ff24ebd6b63ed23a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: dts: rk3399: chrome: enable vop and vop iommu node

Change-Id: I0a92ac277c76d086703fe844bc0fa34a68a428c3
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

UPSTREAM: thermal: of-thermal: allow setting trip_temp on hardware

In current of-thermal, the .set_trip_temp only support to
set trip_temp for SW. But some sensors support to set
trip_temp on hardware, so that can trigger interrupt,
shutdown or any other events.
This patch adds .set_trip_temp() callback in
thermal_zone_of_device_ops{}, so that the sensor device can
use it to set trip_temp on hardware.

Change-Id: I879ea144a9ac21a5032dd885118887b4942c96cf
Signed-off-by: Wei Ni <wni@nvidia.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
(cherry picked from git.kernel.org next/linux-next.git master
 commit 60f9ce3ada53498409d51da06502392884933f89)

UPSTREAM: thermal: convert rockchip_thermal to use devm_thermal_zone_of_sensor_register

This changes the driver to use the devm_ version
of thermal_zone_of_sensor_register and cleans
up the  local points and unregister calls.

Change-Id: I9c13e9c91a626a0ef8df69edf3f383c494536bab
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-pm@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
(cherry picked from git.kernel.org next/linux-next.git master
 commit 93c2f85df90edfc515f99cacd7720e286861f744)

UPSTREAM: thermal: of-thermal: Add devm version of thermal_zone_of_sensor_register

Add resource managed version of thermal_zone_of_sensor_register() and
thermal_zone_of_sensor_unregister().

This helps in reducing the code size in error path, remove of
driver remove callbacks and making proper sequence for deallocations.

Change-Id: Ie2e47805f398ff7b4f1dcc71e0581221d79ba9d2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
(cherry picked from git.kernel.org next/linux-next.git master
 commit e498b4984db82b4ba3ceea7dba813222a31e9c2e)

ARM64: dts: rockchip: enable the gt9xx touchscreen on rk3399-tb dts

The gt9xx touchscreen should be used by rk3399 evb board.
The rk3399-monkey.dtsi and rk3399-chrome.dtsi just run the different OS.
So... we should move the touchscreen node into the rk3399-tb.dtsi.

Change-Id: Ida8203e045e0fc0eb49e8a37e4ad609c230e040f
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: rockchip_cros_defconfig: add the gpio regulator

The gru/kevin board works the iodomain with gpio regulator.
That's useful for rk3399 kevin/gru board.

Change-Id: I70b6185e3a21a038347b9f8ccd679908817184dd
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: rockchip_cros_defconfig: Turn on kgdb

Technically emerging the kernel with USE=kgdb is supposed to get most of
this.  ...and the kernel command line is supposed to come from
elsewhere.  Until we get that happier, maybe this CL is useful.

Change-Id: Idd0100b623eb88b4a4a26922754b71f5cbcd602a
Signed-off-by: Douglas Anderson <dianders@chromium.org>

ARM64: rockchip_cros_defconfig: turn on dwc3 / XHCI

Because USB is important.

Change-Id: I8131a57277922bf13b215fef56e23f3e06cb20d2
Signed-off-by: Douglas Anderson <dianders@chromium.org>

ARM64: rockchip_cros_defconfig: turn on REGULATOR_DEBUG

It's useful. Might be something we can leave on even in a real kernel.
We'll have to see. We have common clock debugging...

Change-Id: I3c1cb55b067a4c54bb425d23664c5f1474016c92
Signed-off-by: Douglas Anderson <dianders@chromium.org>