These forward declarations are not needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35120 91177308-0d34-0410-b5e6-96231b3b80d8

Add more comments and update to new asm syntax.

Add new micro-optimizations.

Add icmp predicate snuggling. Given %x ULT 4, "icmp ugt %x, 2" becomes
"icmp eq %x, 3". This doesn't apply in any non-trivial cases yet due to missing
support for NE values in ValueRanges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35119 91177308-0d34-0410-b5e6-96231b3b80d8

Multiplication support for MMX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35118 91177308-0d34-0410-b5e6-96231b3b80d8

Debugging output stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35117 91177308-0d34-0410-b5e6-96231b3b80d8

Regenerate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35116 91177308-0d34-0410-b5e6-96231b3b80d8

Revert last changes as they introduced other problems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35115 91177308-0d34-0410-b5e6-96231b3b80d8

ARM isel should match ldr x +/- x * (2^n) to ldr [x, +/- x, lsl #log2(n)].

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35114 91177308-0d34-0410-b5e6-96231b3b80d8

Regenerate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35113 91177308-0d34-0410-b5e6-96231b3b80d8

The sign information was not propagating into the rename map so only the
last entry stored in the map could be retrieved for a given integer type.
Propagating the sign information required an invasive change to ensure that
all ValueRef (ValID) instances get the right sign information as well. Also,
put in some assertions to ensure the RenameMap always gives us out the type
that is expected.

This fixes PR1256 and
test/Assembler/2007-03-14-UgpradeLocalSignless.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35112 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1256:
Carry sign with ValID and make TypeInfo sortable (useful in a map).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35111 91177308-0d34-0410-b5e6-96231b3b80d8

Test case for PR1256.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35110 91177308-0d34-0410-b5e6-96231b3b80d8

Estimate a cost using the possible number of scratch registers required and use
it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35109 91177308-0d34-0410-b5e6-96231b3b80d8

Under X86-64 large code model, do not emit 32-bit pc relative calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35108 91177308-0d34-0410-b5e6-96231b3b80d8

Notes about codegen issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35107 91177308-0d34-0410-b5e6-96231b3b80d8

Test that the size of a view converted object is determined by the target
type, not the source type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35106 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35105 91177308-0d34-0410-b5e6-96231b3b80d8

Oops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35104 91177308-0d34-0410-b5e6-96231b3b80d8

Change e-mail address.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35103 91177308-0d34-0410-b5e6-96231b3b80d8

Add link to exception handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35102 91177308-0d34-0410-b5e6-96231b3b80d8

Adding credit for PPC changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35101 91177308-0d34-0410-b5e6-96231b3b80d8

First draft of exception handling doc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35100 91177308-0d34-0410-b5e6-96231b3b80d8

Make older versions of bison happy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35099 91177308-0d34-0410-b5e6-96231b3b80d8

Fix for VS 2005 problem supplied by Morten Ofstad.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35098 91177308-0d34-0410-b5e6-96231b3b80d8

X86-64 JIT is in large code model. Need stubs for direct calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35097 91177308-0d34-0410-b5e6-96231b3b80d8

x86-64 JIT stub codegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35096 91177308-0d34-0410-b5e6-96231b3b80d8

Preliminary support for X86-64 JIT stub codegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35095 91177308-0d34-0410-b5e6-96231b3b80d8

ShiftAmt might equal to zero. Handle this situation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35094 91177308-0d34-0410-b5e6-96231b3b80d8

Enable KnownZero/One.clear().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35093 91177308-0d34-0410-b5e6-96231b3b80d8

New test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35091 91177308-0d34-0410-b5e6-96231b3b80d8

This got better.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35090 91177308-0d34-0410-b5e6-96231b3b80d8

Try schedule def + use closer whne Sethi-Ullman numbers are the same.
e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4

Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2

This creates more short live intervals which work better with the register
allocator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35089 91177308-0d34-0410-b5e6-96231b3b80d8

AM2 can match 2^n +/- 1. e.g.  ldr r3, [r2, r2, lsl #2]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35088 91177308-0d34-0410-b5e6-96231b3b80d8

Zero is always a legal AM immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35087 91177308-0d34-0410-b5e6-96231b3b80d8

Correct type info for isLegalAddressImmediate() check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35086 91177308-0d34-0410-b5e6-96231b3b80d8

Test support for arrays with non-zero first index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35084 91177308-0d34-0410-b5e6-96231b3b80d8

Stack and register alignment of call arguments in the ELF ABI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35083 91177308-0d34-0410-b5e6-96231b3b80d8

ifdef out some dead code.

Fix PR1244 and Transforms/InstCombine/2007-03-13-CompareMerge.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35082 91177308-0d34-0410-b5e6-96231b3b80d8

testcase for PR1244

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35081 91177308-0d34-0410-b5e6-96231b3b80d8

For expression like
"APInt::getAllOnesValue(ShiftAmt).zextOrCopy(BitWidth)",
to handle ShiftAmt == BitWidth situation, use zextOrCopy() instead of
zext().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35080 91177308-0d34-0410-b5e6-96231b3b80d8

Add zextOrCopy() into APInt for convenience.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35079 91177308-0d34-0410-b5e6-96231b3b80d8

In APInt version ComputeMaskedBits():
  1. Ensure VTy, KnownOne and KnownZero have same bitwidth.
  2. Make code more efficient.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35078 91177308-0d34-0410-b5e6-96231b3b80d8

Implement getTargetLowering() or else LSR won't be using ARM specific hooks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35077 91177308-0d34-0410-b5e6-96231b3b80d8

More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35076 91177308-0d34-0410-b5e6-96231b3b80d8

Updated TargetLowering LSR addressing mode hooks for ARM and Thumb.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35075 91177308-0d34-0410-b5e6-96231b3b80d8

More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35074 91177308-0d34-0410-b5e6-96231b3b80d8

More flexible TargetLowering LSR hooks for testing whether an immediate is
 a legal target address immediate or scale.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35073 91177308-0d34-0410-b5e6-96231b3b80d8

Use new TargetLowering addressing modes hooks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35072 91177308-0d34-0410-b5e6-96231b3b80d8

More flexible TargetLowering LSR hooks for testing whether an immediate is
a legal target address immediate or scale.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35071 91177308-0d34-0410-b5e6-96231b3b80d8

Stupid bug: SSE2 supports v2i64 add / sub.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35070 91177308-0d34-0410-b5e6-96231b3b80d8

Revert the last patch as it violates the conditions of sext/zext.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35068 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak C++ build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35067 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak VC++ build.  Do not use identifiers starting with _ as they are reserved and
can collide with system defined names.  Windows defines _BB, for example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35066 91177308-0d34-0410-b5e6-96231b3b80d8

For APInt::z/sext(width), if width == BitWidth, just return *this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35065 91177308-0d34-0410-b5e6-96231b3b80d8

Add an APInt version of SimplifyDemandedBits.

Patch by Zhou Sheng.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35064 91177308-0d34-0410-b5e6-96231b3b80d8

Add an APInt version of ShrinkDemandedConstant.

Patch by Zhou Sheng.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35063 91177308-0d34-0410-b5e6-96231b3b80d8

Avoid to assert on "(KnownZero & KnownOne) == 0".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35062 91177308-0d34-0410-b5e6-96231b3b80d8

In function ComputeMaskedBits():
  1. Replace getSignedMinValue() with getSignBit() for better code readability.
  2. Replace APIntOps::shl() with operator<<= for convenience.
  3. Make APInt construction more effective.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35060 91177308-0d34-0410-b5e6-96231b3b80d8

Add getSignBit() and operator<<= into APInt for convenience.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35059 91177308-0d34-0410-b5e6-96231b3b80d8

Add value ranges. Currently inefficient in both execution time and
optimization power.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35058 91177308-0d34-0410-b5e6-96231b3b80d8

Use range tests in LowerSwitch, where possible

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35057 91177308-0d34-0410-b5e6-96231b3b80d8

Add getter methods for the extremes of a ConstantRange.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35056 91177308-0d34-0410-b5e6-96231b3b80d8

Adding more arithmetic operators to MMX. This is an almost exact copy of
the addition. Please let me know if you have suggestions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35055 91177308-0d34-0410-b5e6-96231b3b80d8

Remove dead comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35053 91177308-0d34-0410-b5e6-96231b3b80d8

Avoid recursion. Use iterative algorithm for RenamePass().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35052 91177308-0d34-0410-b5e6-96231b3b80d8

Increment iterator now because IVUseShouldUsePostIncValue may remove
User from the list of I users.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35051 91177308-0d34-0410-b5e6-96231b3b80d8

Regenerate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35050 91177308-0d34-0410-b5e6-96231b3b80d8

Minor stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35049 91177308-0d34-0410-b5e6-96231b3b80d8

Add comments about LSR / ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35048 91177308-0d34-0410-b5e6-96231b3b80d8

Unfinished work and ideas related to register scavenger.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35047 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1245:
Account for the sign bit when computing the number of bits required for
a negative integer literal constant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35046 91177308-0d34-0410-b5e6-96231b3b80d8

apply comments from review of last patch

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35045 91177308-0d34-0410-b5e6-96231b3b80d8

Add some observations from CoreGraphics benchmark.  Remove register
scavenging todo item, since it is now implemented.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35044 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak mingw32 build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35042 91177308-0d34-0410-b5e6-96231b3b80d8

If a virtual register is already marked alive in this block, that means it is
alive in one of the successor block. Do not add it to the kill list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35041 91177308-0d34-0410-b5e6-96231b3b80d8

Print preds / succs BB numbers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35040 91177308-0d34-0410-b5e6-96231b3b80d8

Avoid variable shadowing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35039 91177308-0d34-0410-b5e6-96231b3b80d8

Don't use std::hex.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35038 91177308-0d34-0410-b5e6-96231b3b80d8

Don't use a cast. It causes an error on some platforms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35037 91177308-0d34-0410-b5e6-96231b3b80d8

Test inline asm modifier 'c'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35036 91177308-0d34-0410-b5e6-96231b3b80d8

Implement inline asm modifier c.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35035 91177308-0d34-0410-b5e6-96231b3b80d8

upgrade this testcase, add test for fp immediate to memory operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35034 91177308-0d34-0410-b5e6-96231b3b80d8

implement support for floating point constants used as inline asm memory operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35033 91177308-0d34-0410-b5e6-96231b3b80d8

Add MMX arithmetic testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35032 91177308-0d34-0410-b5e6-96231b3b80d8

Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that
moves, loads, etc. are recognized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35031 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35030 91177308-0d34-0410-b5e6-96231b3b80d8

Fix test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35029 91177308-0d34-0410-b5e6-96231b3b80d8

Speed Up Pass Manager.
- Check Immutableness before searching PreservedSet.
- Avoid unnecessary traversal while setting Last User.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35028 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a bug in function ComputeMaskedBits().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35027 91177308-0d34-0410-b5e6-96231b3b80d8

Putting more constants which do not contain relocations into .literal{4|8|16}

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35026 91177308-0d34-0410-b5e6-96231b3b80d8

make this fail even in non-assert builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35025 91177308-0d34-0410-b5e6-96231b3b80d8

This appears correct, enable it so we can see perf changes on testers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35024 91177308-0d34-0410-b5e6-96231b3b80d8

Second half of PR1226.  This is currently still disabled, until I have a chance to
do the correctness/performance analysis testing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35023 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a bug in APIntified ComputeMaskedBits().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35022 91177308-0d34-0410-b5e6-96231b3b80d8

Change register allocation order to Dale's suggestion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35021 91177308-0d34-0410-b5e6-96231b3b80d8

Bug fix. Not advancing the register scavenger iterator correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35020 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1205:
Provide an APIntified version of MaskedValueIsZero. This will (temporarily)
cause a "defined but not used" message from the compiler. It will be used
in the next patch in this series.

Patch by Sheng Zhou.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35019 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1205:
Add a new ComputeMaskedBits function that is APIntified. We'll slowly
convert things over to use this version. When its all done, we'll remove
the existing version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35018 91177308-0d34-0410-b5e6-96231b3b80d8

For Darwin, put constant data into .const, .const_data, .literal{4|8|16}
sections.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35017 91177308-0d34-0410-b5e6-96231b3b80d8

Put constant data to .const, .const_data, .literal{4|8|16} sections.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35016 91177308-0d34-0410-b5e6-96231b3b80d8

Add ReadOnlySection directive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35015 91177308-0d34-0410-b5e6-96231b3b80d8