video: rockchip: vop lite: fix lut config error

Change-Id: I201e3bb8a60650259e2de4f3973173039188fe34
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop lite: recover interlace config

Change-Id: I03171fd1546ead16f477cb255f2b1bbc1d20adf8
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: fb: rename time line name for vop0 and vop1

Change-Id: Ifae7d4fc88dd41ecb659c886237a6d65026fded6
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

ARM64: dts: rockchip: add clk_ignore_unused for rk3399

Change-Id: I2f6faf3807d5c3b347d8b6930cc8f29c56746b2a
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

video: rockchip: vop: 3366: writeback function test ok

Change-Id: I560a714a86dad83f277d380c3650d4ed7827d80b
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop lite: add deal with BGR data format

Change-Id: I5cac5cfd6385c5a0aa4152c927053ecd55290031
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: fb: add BGR data format support

Change-Id: Ia97a20b5ed1e3ab92e31136e0cb60a785b570a65
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

i2c: rk3x: add i2c support for rk3399 soc

- new method to caculate i2c timings for rk3399:
  There was an timing issue about "repeated start" time at the I2C
  controller of version0, controller appears to drop SDA at .875x (7/8)
  programmed clk high. On version 1 of the controller, the rule(.875x)
  isn't enough to meet tSU;STA
  requirements on 100k's Standard-mode. To resolve this issue,
  sda_update_config, start_setup_config and stop_setup_config for I2C
  timing information are added, new rules are designed to calculate
  the timing information at new v1.
- pclk and function clk are separated at rk3399.
- support i2c highspeed mode: 1.7MHz for rk3399

Change-Id: I413455cf94fe7486c40694059e2f0931433992bb
Signed-off-by: David Wu <david.wu@rock-chips.com>

i2c: rk3x: switch to i2c generic dt parsing

Switch to the new generic functions: i2c_parse_fw_timings().

Change-Id: I14c3bea8e696d0ba5467effba1a157cd86e376d6
Signed-off-by: David Wu <david.wu@rock-chips.com>

ARM64: dts: rk3399: add support clock assignment for PMUCRU/CRU

Change-Id: I8dc31880a232c1753c0fbfbeb4e3df0d09d7cdb3
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: add clock controller for the RK3399

Add the clock tree definition for the new RK3399 SoC.

Change-Id: I1d8755eb7c89bdc56b79644a96a7d3fd8e7fbc4b
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ARM: dts: rockchip: add rk3288 mipi_dsi nodes

Add a mipi_dsi node, and also add mipi_dsi endpoints to vopb and vopl
output port nodes.

Change-Id: I0181ec03b0c944a18391737ea6bb65c5b642a6ea
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit cab6f070ab53df0fa8a17e95ca7518a8c8e42e69)

UPSTREAM: Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver

add device tree bindings for rk3288 specific Synopsys DW MIPI DSI driver

Change-Id: Ie6774d527475889a6eab587e66eda607d1ea2c8b
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
(cherry picked from commit a20d86e7f96422d375dfa9ac0fe96ca4ce2aa647)

UPSTREAM: drm/panel: simple: Add support for BOE TV080WUM-NL0

The BOE TV080WUM-NL0 is an 8.0", 1200x1920 (WUXGA) TFT-LCD panel
connected using four DSI lanes. It can be supported by the simple-panel
driver.

Change-Id: I4fe03fc830332e60997e98b24550801827692501
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
(cherry picked from commit c8521969dea2b8e10ecbba86e0221e4f63dce921)

UPSTREAM: dt-bindings: Add BOE TV080WUM-NL0 panel binding

The BOE TV080WUM-NL0 is an 8.0", 1200x1920 (WUXGA) TFT-LCD panel
connected using four DSI lanes.

Change-Id: I963cf860315f86ca64249c8f2064acbba62276b5
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
(cherry picked from commit 86b81f3e17b34e245ee01cf2bd142d12fae125cc)

UPSTREAM: of: Add vendor prefix for BOE Technology Group

BOE Technology Group Co., Ltd. is a supplier of semiconductor display
technologies, products and services.

Change-Id: Id9a81512f6174770fc1d1282579da902fcdc89b0
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
[treding@nvidia.com: add commit message, fixup subject]
Signed-off-by: Thierry Reding <treding@nvidia.com>
(cherry picked from commit 27d23b30a561b752f1564d99cb6c8247c78f74f6)

UPSTREAM: clk: rockchip: add mipidsi clock on rk3288

sclk_mipidsi_24m is the gating of mipi dsi phy.

Change-Id: I15b3e7a17b06397eb825eb2faca37d77732c9a97
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit a2f4c560f18edd2ffe0f15d52ce2be55cff605d2)

UPSTREAM: clk: rockchip: add id for mipidsi sclk on rk3288

Adds a new id for the sclk supplying the mipidsi on rk3288 socs.

Change-Id: Ifc3b97e4feed01098b483162d6320240d4b44cb3
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit c6d49fbcfcc44264c31f93866c9a713491e4a5fe)

UPSTREAM: clk: rockchip: add an id for rk3288 crypto clk

Add an id for crypto clk to the binding header, so that it can be called
in other part.

Change-Id: I541f4373cb2753aa74e2183cae82215e31faae44
Signed-off-by: Zain Wang <zain.wang@rock-chips.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 94d5d6a0fbf33c5fde246b61b8c358cfeeba633f)

ARM64: dts: add eMMC/sdio/sd nodes for rk3399 sdk

Change-Id: Ia8bcfcb8938927cae7c970e2be02466c95ff7021
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

ARM64: dts: rk3399: add pinctrl for uart

Change-Id: I8c48826d789bb48f234aa82014754dd519888d07
Signed-off-by: David Wu <david.wu@rock-chips.com>

ARM64: dts: rockchip: fix i2c clk for rk3399

Change-Id: I2edcdb4955d9ae5659d2a8f6f5c5e5b089759d9f
Signed-off-by: David Wu <david.wu@rock-chips.com>

ARM64: dts: rockchip: fix gpio clk error for rk3399

Change-Id: I8efd8007b17cc054a8e0bd20d1ccc89f7cf26ee8
Signed-off-by: David Wu <david.wu@rock-chips.com>

ARM64: dts: rk3399: add PSCI node

Add PSCI node for RK3399 SoC, and cpu node enable-method property is
set to "psci".

Change-Id: I24f348b379435da88fe33f01e4b726e2e0210a9d
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM64: dts: rk3399: add pmu node

Change-Id: I1f3226749f66a1c2c61b9aec4fb7acba17e88135
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM64: dts: rk3399: fix arch timer irq type

Should be low level triggered.

Change-Id: Ie092cac9d262947ffc6294bc71cbb2efe73f3885
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM64: dts: rockchip: add wdt0 for rk3399

There are two watchdogs in ALIVE named WDT0 and WDT1, and
one watchdog in PMU named WDT2.

WDT0 can drive CRU to generate global software reset.

Change-Id: Ide47e7e69572d2f2a537b590dc75010cf0f56c51
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

ARM64: dts: rockchip: rk3399: add cpu dvfs support for tb

Change-Id: I707ebf8b4ba045401ebb3e609d511a8eb0883120
Signed-off-by: Feng Xiao <xf@rock-chips.com>

UPSTREAM: drm/atomic-helper: Export framebuffer_changed()

The Rockchip driver cannot use drm_atomic_helper_wait_for_vblanks()
because it has hardware counters for neither vblanks nor scanlines.

In order to simplify re-implementing the functionality for this driver,
export the framebuffer_changed() helper so it can be reused.

Change-Id: I80e2dc3b412d2299e6d97a9421e928dc32a9b63e
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit c240906d36653944d5c049df7ce667a7e8bea6ac)

mmc: sdhci-of-arasan: keep consistent with upstream

This patch manually amend some code to keep local
branch more consistent with upstream.

Change-Id: If705983f84ade4e7cebb45db8a65d34b876c7bef
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM64: dts: rockchip: rk3368: fix cpu get regulator and clock error

we only add the property of regulator and clock to cpu0 and cpu4 node,
but if cpu4~cpu7 is down and then we up cpu5~cpu7, they will can not
get their regulator and clock. So we should add the properties to all
cpu node.

Change-Id: Id601fa3d3d05875f7c68f2a5472dc0eefefb6096
Signed-off-by: Feng Xiao <xf@rock-chips.com>

ARM64: rockchip_defconfig: enable emmc phy driver

Change-Id: If555e77e60dc64782cc071ec8b78a0fdceaf9173
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM64: dts: rk3366-tb: disable vdd_arm when deep sleep

Change-Id: Iffce92e3412eeee36b735a8db5fdc08f532c3894
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

UPSTREAM: drm/rockchip: respect CONFIG_DRM_FBDEV_EMULATION

If DRM_FBDEV_EMULATION is not selected in the config then we can save a
bit of space by not including the framebuffer code.

Change-Id: I57b8888ebed0a0980e04a908116ad843b2fad556
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: John Keeping <john@metanate.com>
(cherry picked from commit f0442df2156a2171e40f1643c60103e6333f4e7e)

UPSTREAM: drm/rockchip: fix wrong pitch/size using on gem

args->pitch and args->size may not be set by userspace, sometimes
userspace only malloc args and not memset args to zero, then
args->pitch and args->size is random, it is very danger to use
pitch/size on gem.

pitch's type is u32, and min_pitch's type is int, example,
pitch is 0xffffffff, then pitch < min_pitch return true, then gem will
alloc very very big bufffer, it would eat all the memory and cause kernel
crash.

Stop using pitch/size from args, calc them from other args.

Change-Id: I867d61bf6bc48a2989ae4d15a819a85a7e38d26f
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit e3c4abdb3bc9b76bedd416ecc5c27633a2f8afed)

UPSTREAM: drm/rockchip: explain why we can't wait_for_vblanks

Change-Id: I073cf5b91554a293009a121845ac1bf3b6b3e6ce
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: John Keeping <john@metanate.com>
(cherry picked from commit c9ad1d9946e849ac3d8821d91e136d7fd728dec5)

UPSTREAM: drm/rockchip: don't wait for vblank if fb hasn't changed

As commented in drm_atomic_helper_wait_for_vblanks(), userspace relies
on cursor ioctls being unsynced.  Converting the rockchip driver to
atomic has significantly impacted cursor performance by making every
cursor update wait for vblank.

By skipping the vblank sync when the framebuffer has not changed (as is
done in drm_atomic_helper_wait_for_vblanks()) we can avoid this for the
common case of moving the cursor and only need to delay the cursor ioctl
when the cursor icon changes.

We cannot add the check on legacy_cursor_update since that results in
the cursor bo being unreferenced while the hardware may still be reading
it.  Fully supporting unsynced cursor updates is left for the future
when the atomic helper framework supports async updates.

Change-Id: I4c0e4b51ec7441fb7b7342eac5d4b98f9ca5ee62
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: John Keeping <john@metanate.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit f2227f469782e55765deacb8ebcc7ec05fe04013)

UPSTREAM: drm/rockchip/dsi: fix handling mipi_dsi_pixel_format_to_bpp result

The function can return negative value so it should be assigned to signed
variable.

The problem has been detected using patch
scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci.

Change-Id: Ide4daa64ce996d125b2f698e6f2d4899591e8065
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Chris Zhong <zyw@rock-chips.com>
(cherry picked from commit 484bb6c969523aa547d854bb57104339ee4aa800)

UPSTREAM: drm/rockchip: cleanup unnecessary export symbol

Now rockchip_drm_vop.c is build into rockchipdrm.ko, so
no need to export following symbol anymore:
    rockchip_drm_dma_attach_device
    rockchip_drm_dma_detach_device
    rockchip_drm_dma_attach_device
    rockchip_drm_dma_detach_device
    rockchip_register_crtc_funcs
    rockchip_unregister_crtc_funcs
    rockchip_fb_get_gem_obj

Change-Id: Ic6cc7cb83efca4f74f1e70e3568abdfb83d2886f
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit 63087aae5a7976a4557d16873146eae03948ec74)

UPSTREAM: drm/rockchip: vop: fix mask when updating interrupts

Commit dbb3d94 (drm/rockchip: vop: move interrupt registers into
vop_data) introduced new macros for updating the interrupt control
registers but these always use the mask from the register definition
without refining it for the particular bits that are being changed.

This means that whenever we enable/disable a particular interrupt we end
up disabling all of the others as a side effect.

Change-Id: I3b0f2574315f3655c183c21143b0bca7cdd9f6fa
Signed-off-by: John Keeping <john@metanate.com>
(cherry picked from commit c7647f8681feeb6c0957e3cf5daed1fbf8b3a5af)
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

UPSTREAM: drm/rockchip: Don't build rockchip_drm_vop as modules

rockchip_drm_vop's module init had moved to rockchip_vop_reg.c
so no need to build rockchip_drm_vop.ko

Change-Id: I36da6a2741a250f3344b9febcd0c74539a861798
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit ce90d092bcd96b646b370121f0f1508270627f98)

UPSTREAM: drm: rockchip: Support Synopsys DW MIPI DSI

Add support for Synopsys DesignWare MIPI DSI controller which is
embedded in the rk3288 SoCs.

Change-Id: Ic450633c683520361926a676191426349376803e
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit 84e05408fcfefb9b28050f701e1e94fe9f86804b)

UPSTREAM: drm/rockchip: return a true clock rate to adjusted_mode

Since the mipi dsi driver need to use the clock of vop to make the
calculation of Blanking. But sometimes the clock driver can not set a
accurate clock_rate for vop, get it by clk_round_rate before mode_set,
so we can get the true value.

Change-Id: I04e6a499763258c2e16a09e3a59cf3a1e4593706
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit b59b8de3149736e5094cb786978a1ba8d6d55b34)

UPSTREAM: drm/rockchip: vop: export vop_component_ops to modules

Fixes: a67719d18229 ("drm/rockchip: vop: spilt register related into rockchip_reg_vop.c")
Change-Id: I4c855f65e684c08f8648547dcf16aa657c6ae5db
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 54255e818ef7a5e968c0230bc75649a68932d8ca)

UPSTREAM: drm/rockchip: vop: add rk3036 vop support

RK3036 registers layout is quite difference with rk3288 layout,
The IC design with different framework, rk3036 vop is VOP LITE,
and rk3288 is VOP FULL.

RK3036 support two overlay plane and one hwc plane, max output
resolution is 1080p. it support IOMMU, and its IOMMU same as
rk3288's.

Change-Id: Ib713b252dc6f2d4bffa3183698768c6f23236ccf
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit f7673453506035a904b6fb7a36dd6fb101366cd7)

UPSTREAM: drm/rockchip: vop: spilt scale regsters

There are two version scale control register found on vop,
scale full version found on rk3288, support extension registers.
and scale little version found on rk3036, only support common scale.

Change-Id: Iea1f253f363e062d49390fa51c304a2c109c39c6
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit 1194fffbb102b1683bcbfc893df20bbf8a038468)

UPSTREAM: drm/rockchip: vop: spilt register related into rockchip_reg_vop.c

No functional updates. Spilt register related into another file
would be nice to multi vop driver,

Change-Id: I811b12a57b03c24eb420d0c3fa0833f412bd258c
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit a67719d182291bf62c6093545b9af27f0431cbeb)

UPSTREAM: drm/rockchip: vop: move interrupt registers into vop_data

Move interrupt registers into vop_data, so it can use at multi-vop driver

Change-Id: I3183fb3c97e76d58dbdab2f2df34480ee2e74b31
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit dbb3d94444eaa56cb1a6c9790f2fbe14b14310aa)

UPSTREAM: drm/rockchip: vop: merge vop cfg_done into vop_data

Move cfg_done register into vop_data, so it can use at multi-vop driver

Change-Id: Id92d69302a4fc9e28b96099bf0297674f2abfb33
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit 0cf33fe33d4e9fdbbdd0b93101b078b03d0ba9b5)

UPSTREAM: drm/rockchip: dw_hdmi: use encoder enable function

encoder.enable is more compatible to atomic api than encoder.prepare/commit

Change-Id: Idacd1c44df94110b4a4b2cc66be9ce0eda8a2ad9
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit a8eef71d38da2bb03e187d3284aac6d3e0540f0f)

UPSTREAM: drm/rockchip: direct config connecter gate and out_mode

Both connecter gate and out_mode are not conflict with mode set
configure. Direct setting connecter gate and out_mode, that allow
connector do rockchip_drm_crtc_mode_config after mode set.

Change-Id: I6f7af59b7cbff2ae55830f31155e34e041cc74f8
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit d0e20d0ebfe40a4eba52bef2e1e03e91fce88528)

UPSTREAM: drm/rockchip: support atomic asynchronous commit

If drm core requests a async commit, rockchip_drm_atomic_commit
will schedule a work task to update later.

Change-Id: I8d35b157b817f2e7f810968e7b18043414cb17e6
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit f32fad51eec51ad816cecdc3723ab443cd69b61f)

UPSTREAM: drm/rockchip: Optimization vop mode set

Rk3288 vop timing registers is immediately register, when configure
timing on display active time, will cause tearing. use dclk reset is
not a good idea to avoid this tearing. we can avoid tearing by using
standby register.

Vop standby register will take effect at end of current frame, and
go back to work immediately when exit standby.

So we can use standby register to protect this context.

Change-Id: Ib65433900c67f9fbd3957c4b0506d6172474e5c2
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit ce3887ed0d996e6353d739e8139b8e5faeb726d5)

UPSTREAM: drm/rockchip: Convert to support atomic API

Rockchip vop not support hw vblank counter, needed check the committed
register if it's really take effect.

Change-Id: Ia291cdf75bc2f7397881f0e5f42debeae1c04f03
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit 63ebb9fa7ff06d194362ed4a5d0a31ac7612a89c)

UPSTREAM: drm/rockchip: vop: replace dpms with enable/disable

For vop, power by enable/disable is more suitable then legacy dpms
function, and enable/disable more closely to the new atomic API.

Change-Id: Ief6e31f023a2e2af84aba773edac51fccd487a2c
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit 0ad3675d9c8f7c7306c954a9c50dc12385d8a508)

UPSTREAM: drm/rockchip: Use new vblank api drm_crtc_vblank_*

No functional update, drm_vblank_* is the legacy version of
drm_crtc_vblank_*. and use new api make driver more clean.

Change-Id: Ia93ec8124333d59446d1507f7567be2775bea144
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(cherry picked from commit b5f7b75503efa5499080e51eb5c085fe1de1970d)

UPSTREAM: drm/rockchip: Constify function pointer structs

Moves a bunch of junk to .rodata from .data.

 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.ko:
-.rodata                      772
+.rodata                      828
-.data                        148
+.data                         92

 drivers/gpu/drm/rockchip/rockchipdrm.ko:
-.rodata                      748
+.rodata                      760
-.data                        448
+.data                        436

Change-Id: Ic93fc8d334a51618ea8075b4344983b795c7623e
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1450178476-26284-25-git-send-email-boris.brezillon@free-electrons.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 28c508ece6831e49d36cfa868f2a6c9d9f1c920e)

UPSTREAM: drm: Pass 'name' to drm_encoder_init()

Done with coccinelle for the most part. However, it thinks '...' is
part of the semantic patch, so I put an 'int DOTDOTDOT' placeholder
in its place and got rid of it with sed afterwards.

@@
identifier dev, encoder, funcs;
@@
 int drm_encoder_init(struct drm_device *dev,
                      struct drm_encoder *encoder,
                      const struct drm_encoder_funcs *funcs,
                      int encoder_type
+                     ,const char *name, int DOTDOTDOT
                      )
{ ... }

@@
identifier dev, encoder, funcs;
@@
 int drm_encoder_init(struct drm_device *dev,
                      struct drm_encoder *encoder,
                      const struct drm_encoder_funcs *funcs,
                      int encoder_type
+                     ,const char *name, int DOTDOTDOT
                      );

@@
expression E1, E2, E3, E4;
@@
 drm_encoder_init(E1, E2, E3, E4
+                 ,NULL
                  )

v2: Add ', or NULL...' to @name kernel doc (Jani)
    Annotate the function with __printf() attribute (Jani)

Change-Id: Id28ae2a6848fe1bd46905287b68f5d2c61d70039
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1449670818-2966-1-git-send-email-ville.syrjala@linux.intel.com
(cherry picked from commit 13a3d91f17a5f7ed2acd275d18b6acfdb131fb15)

UPSTREAM: drm: Pass 'name' to drm_universal_plane_init()

Done with coccinelle for the most part. It choked on
msm/mdp/mdp5/mdp5_plane.c like so:
"BAD:!!!!!  enum drm_plane_type type;"
No idea how to deal with that, so I just fixed that up
by hand.

Also it thinks '...' is part of the semantic patch, so I put an
'int DOTDOTDOT' placeholder in its place and got rid of it with
sed afterwards.

I didn't convert drm_plane_init() since passing the varargs through
would mean either cpp macros or va_list, and I figured we don't
care about these legacy functions enough to warrant the extra pain.

@@
typedef uint32_t;
identifier dev, plane, possible_crtcs, funcs, formats, format_count, type;
@@
 int drm_universal_plane_init(struct drm_device *dev,
                              struct drm_plane *plane,
                              unsigned long possible_crtcs,
                              const struct drm_plane_funcs *funcs,
                              const uint32_t *formats,
                              unsigned int format_count,
                              enum drm_plane_type type
+                             ,const char *name, int DOTDOTDOT
                              )
{ ... }

@@
identifier dev, plane, possible_crtcs, funcs, formats, format_count, type;
@@
 int drm_universal_plane_init(struct drm_device *dev,
                              struct drm_plane *plane,
                              unsigned long possible_crtcs,
                              const struct drm_plane_funcs *funcs,
                              const uint32_t *formats,
                              unsigned int format_count,
                              enum drm_plane_type type
+                             ,const char *name, int DOTDOTDOT
                              );

@@
expression E1, E2, E3, E4, E5, E6, E7;
@@
 drm_universal_plane_init(E1, E2, E3, E4, E5, E6, E7
+                         ,NULL
                          )

v2: Split crtc and plane changes apart
    Pass NUL for no-name instead of ""
    Leave drm_plane_init() alone
v3: Add ', or NULL...' to @name kernel doc (Jani)
    Annotate the function with __printf() attribute (Jani)

Change-Id: I65fa347937ec17d21ac3fa28ec9c58c3ce97d496
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1449670795-2853-1-git-send-email-ville.syrjala@linux.intel.com
(cherry picked from commit b0b3b7951114315d65398c27648705ca1c322faa)

UPSTREAM: drm: Pass 'name' to drm_crtc_init_with_planes()

Done with coccinelle for the most part. However, it thinks '...' is
part of the semantic patch, so I put an 'int DOTDOTDOT' placeholder
in its place and got rid of it with sed afterwards.

I didn't convert drm_crtc_init() since passing the varargs through
would mean either cpp macros or va_list, and I figured we don't
care about these legacy functions enough to warrant the extra pain.

@@
identifier dev, crtc, primary, cursor, funcs;
@@
 int drm_crtc_init_with_planes(struct drm_device *dev,
                               struct drm_crtc *crtc,
                               struct drm_plane *primary, struct drm_plane *cursor,
                               const struct drm_crtc_funcs *funcs
+                              ,const char *name, int DOTDOTDOT
                               )
{ ... }

@@
identifier dev, crtc, primary, cursor, funcs;
@@
 int drm_crtc_init_with_planes(struct drm_device *dev,
                               struct drm_crtc *crtc,
                               struct drm_plane *primary, struct drm_plane *cursor,
                               const struct drm_crtc_funcs *funcs
+                              ,const char *name, int DOTDOTDOT
                               );

@@
expression E1, E2, E3, E4, E5;
@@
 drm_crtc_init_with_planes(E1, E2, E3, E4, E5
+                          ,NULL
                           )

v2: Split crtc and plane changes apart
    Pass NULL for no-name instead of ""
    Leave drm_crtc_init() alone
v3: Add ', or NULL...' to @name kernel doc (Jani)
    Annotate the function with __printf() attribute (Jani)

Link: http://patchwork.freedesktop.org/patch/msgid/1449670771-2751-1-git-send-email-ville.syrjala@linux.intel.com
(cherry picked from commit f98828769c8838f526703ef180b3088a714af2f9)

Change-Id: I8eb2a67b3a01bd0cb49e552f05a5ee5c6ac99d40
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

ARM64: dts: rockchip: add io-domain support for rk3399-tb

Change-Id: Ib72983eb50c416649a35be4393a889bc72e2457a
Signed-off-by: David Wu <david.wu@rock-chips.com>

ARM64: dts: rockchip: add backlight support for rk3399-tb

Change-Id: I99314db0fe7a31b4bb652749c35c738100bdf344
Signed-off-by: David Wu <david.wu@rock-chips.com>

ARM64: dts: rockchip: add key support for rk3399-monkey

Change-Id: I1897555009fae4401d52eab443b59ff572b43879
Signed-off-by: David Wu <david.wu@rock-chips.com>

POWER: AVS: rockchip: add rk3399 io domain support

Change-Id: If4ccc31372f1cdbea84fc27009c1b8f9238ee1e9
Signed-off-by: David Wu <david.wu@rock-chips.com>

ARM64: dts: rk3366: add pmu node

Change-Id: I8ab43d9d6a1361ba1546363c4d16cfa3f87b3e3c
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM64: dts: rk3399: sort nodes and fix spi reg

Change-Id: Icb71adf3ebfcee57be46886672a0fe1afe77473f
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM64: dts: rockchip: add pmic node for RK3399

add pmic rk808 node for rk3399.
add pwm regulator node for rk3399.

Change-Id: I00b33363ba513064eb0a235c646df9a46062941c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: rockchip_defconfig: enable selinux

Change-Id: I0142795593483474ee157ed2d64cc0fb18f2ef44
Fixes: 361ddf2d6908 ("arm64: rockchip: rockchip_defconfig updates for 4.4")
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM64: dts: rockchip: add USB2.0 host nodes for rk3399

Change-Id: Id18a8b43210e439add8c5af8a18a3a62e0d06cc9
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

ARM64: dts: rockchip: add dts files for rk3399

The dts files include three level:
- rk3399.dtsi
  includes nodes who closed to SoC, such as cpu\pmu\cru\i2c\pinctl\iommu...

- rk3399-tb.dtsi
  includes nodes who required by main board, they are common nodes for both
  chromeos and android; also to enable node from rk3399.dtsi if needs

- rk3399-monkey.dts
  used by evb board with android system

- rk3399-chrome.dts
  used by evb board with chromeos system

Change-Id: I02e21a8d184e74c96807f3b8b72075d466e1027f
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

arm64: dts: rk3366-tb: add bt node and enable it

Change-Id: I2969aed08d0ca822d717c13680af71630bd57699
Signed-off-by: huweiguo <hwg@rock-chips.com>

ARM64: dts: rockchip: add power domain node for RK3399 Soc

add pd node for RK3399 Soc
create power domain tree

Change-Id: I5a455034f56b6d88860c3ed2decd8c6dc94896a3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: dts: rockchip: add emmc, sdio and sdmmc node for rk3399

This patch add emmc, sdio and sdmmc node to support
mmc stuff on rk3399 platform.

Change-Id: I717855dded5f5161127ba29e34b9ff2106009c55
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

phy: rockchip-emmc: fix compile issue on arm64 platform

This patch rename "reg" property to "reg_offset".
We rename it to fix the compile issue on ARM64 platform:
(reg_format): "reg" property in /phy has invalid length (4 bytes)
(#address-cells == 2, #size-cells == 2)

This's because "reg" is very special one which should keep the
*-cells with its parent node and can't be overwrited even if we
do that explicitly. On 32-bit plafform, the default *-cells
fit for what we assign to "reg". But that's not correct for 64-bit
platform. So we can see two possible solutions to fix this problem:
A) make phy-rockchip-emmc as a child phy node and overwrite its
parent's #address-cells and #size-cells.
B) avoid using this special property.

we use it just for passing on a offset for different Socs, and there's
no requirement to change the code to make phy-rockchip-emmc as a child
node. so choose option B) is sane.

Change-Id: Ib6a10cb8c3629ec3983854f1bfb7c2426edf79d2
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM64: rockchip_defconfig: enable sdhci controller

Change-Id: Iec8f07c898ed651f662847d0605954f3c356c55e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

pwm: rockchip: add pwm support for rk3399

Change-Id: I0658d1b69b5799c2ef6604563c41b5a0d87ddce2
Signed-off-by: David Wu <david.wu@rock-chips.com>

ARM64: dts: rockchip: add saradc support for rk3399

Change-Id: I786e6efe31a45568d581baf09093f56409c0151f
Signed-off-by: David Wu <david.wu@rock-chips.com>

ARM64: dts: rockchip: add pwm support for rk3399

Change-Id: I243cbf417cf78f39b97e12f66c916502fe72fe31
Signed-off-by: David Wu <david.wu@rock-chips.com>

ARM64: dts: rockchip: add i2c node for rk3399

Change-Id: I3a662d25927fc9c2c4f756963f1522c24fce70d6
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

iio: adc: rockchip_saradc: add saradc support for rk3399

Change-Id: I1d60583f02cc4b4cac8a8a1c1fb22bfeb5e52647
Signed-off-by: David Wu <david.wu@rock-chips.com>

net: rkwifi: Modify driver loading way to reduce boot time

Change-Id: Ie569aeedb5544cb0131ab48818db6a5b0dde05bb
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

ARM64: dts: rk3366-tb: enable nandc

Change-Id: I2b563214e9ad276524f555a31a408c8995cb63a9
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>

arm64: configs: rockchip_defconfig add nand driver

Change-Id: I3bccfe5710c860841714d6e54aa23ed075d5a584
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>

net: rfkill-bt: auto compatible for uart rts control for all uart bt chip

Change-Id: I9b4d6614160285754ee86c427e8918296b92ddbd
Signed-off-by: huweiguo <hwg@rock-chips.com>

ARM64: nand: update nand drvier for 3366

Change-Id: I96ff59f331591807f8d5b009c933a6c71f62a93b
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>

ARM64: rockchip_defconfig: enable rk808 rtc

add CONFIG_RTC_DRV_RK808=y

Change-Id: I7aae9990c9bbf787a7e42e319116df6b4749c3cd
Signed-off-by: Shengfei xu <xsf@rock-chips.com>

UPSTREAM: clk: rockchip: add new pll-type for rk3399 and similar socs

The rk3399's pll and clock are similar with rk3036's, it different
with base on the rk3066(rk3188, rk3288, rk3368 use it), there are
different adjust foctors and control registers, so these should be
independent and separate from the series of rk3066s.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git
v4.7-clk/next commit 95e0c473a0ac1bdac25f55678dc602eb50dae684)

Change-Id: I77872b5fb33eb92402e9036b97b185ea56eb45c6
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: release io resource when failing to init clk

We should call iounmap to relase reg_base since it's not going
to be used any more if failing to init clk.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git
v4.7-clk/next commit 86609a6613c64ee9272da1fd2f578d4beab2174e)

Conflicts:

drivers/clk/rockchip/clk-rk3228.c
[zx: there is no rk3228 clock controller, and apply this patch for
clk-rk3366 manually.]

Change-Id: I2d73c90eb6f43150725c81417af37a6a562cd329
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: remove redundant checking of device_node

rockchip_clk_of_add_provider is used by sub-clk driver which
already call of_iomap before calling it. If device_node does
not exist, of_iomap returns NULL which will fail to init the
sub-clk driver. So really it's redundant.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git
v4.7-clk/next commit a96edf5a5243e1bdf642492b783221aa498f1e49)

Change-Id: I9a51ed269fe26742da2ae84d99cf9689f49add1b
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: fix warning reported by kernel-doc

./scripts/kernel-doc -man -v drivers/clk/rockchip/clk.h > /dev/null

drivers/clk/rockchip/clk.h:133: warning: missing initial short
description on line:
 * struct rockchip_clk_provider: information about clock provider
drivers/clk/rockchip/clk.h:133: info: Scanning doc for struct
drivers/clk/rockchip/clk.h:164: warning: missing initial short
description on line:
 * struct rockchip_pll_clock: information about pll clock
drivers/clk/rockchip/clk.h:164: info: Scanning doc for struct
drivers/clk/rockchip/clk.h:194: warning: No description found for
parameter 'parent_names'
drivers/clk/rockchip/clk.h:194: warning: No description found for
parameter 'num_parents'
drivers/clk/rockchip/clk.h:194: warning: Excess struct/union/enum/typedef
member 'parent_name' description in 'rockchip_pll_clock'
drivers/clk/rockchip/clk.h:235: warning: missing initial short
description on line:
 * struct rockchip_cpuclk_reg_data: describes register offsets and
masks of the cpuclock

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git
v4.7-clk/next commit 1c908b320055e1ce706e91121dbb2ce7934c788f)

Change-Id: I18dbd45ebd528fe2a871c98a1561dd0c0bf41e13
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: remove mux_core_reg from rockchip_cpuclk_reg_data

mux_core_reg isn't been used anywhere, let's remove it.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git
v4.7-clk/next commit 72478f190fec9f2358b62f32ce5e27e6f323fa53)

Change-Id: Ib6d8ee5bca61d1ada6215660862d2d728927a948
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: Add support for multiple clock providers

There are need to support Multi-CRUs probability in future, but
it is not supported on the current Rockchip Clock Framework.

Therefore, this patch add support a provider as the parameter
handler when we call the clock register functions for per CRU.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git
v4.7-clk/next commit d509ddf2e57c99ae760d1a289b85f1e0d729f864)

Conflicts:

drivers/clk/rockchip/clk-rk3036.c
drivers/clk/rockchip/clk-rk3188.c
drivers/clk/rockchip/clk-rk3228.c
drivers/clk/rockchip/clk-rk3366.c
[zx: keep calling clk_register_fixed_factor previouslly, and there
is no rk3228 clock controller, add support for clk-rk3366 manually,
because it is not in the upstream codes.]

Change-Id: I94976f38fb6edd88f334479d6e44fef5bcdfc16a
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: allow varying mux parameters for cpuclk pll-sources

Thers are only two parent PLLs that APLL and GPLL for core on the
previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
GPLL as alternate parent when core is switching freq.

Since RK3399 big.LITTLE architecture, we need to select and adapt
more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next
 commit 0fda2be634398f4b8d53c0436311f99557e56c4e)

Conflicts:

drivers/clk/rockchip/clk-rk3228.c
[zx: there is no rk3228 clock controller, apply this patch for
clk-rk3366.]

Change-Id: I48fde9facccd41585873c997b0b02a7a73972717

UPSTREAM: clk: rockchip: only enter pll slow-mode directly before reboots on rk3288

As commit 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before
reboot for rk3288") states, switching the PLLs to slow-mode is only
necessary when rebooting using the soft-reset done through the CRU.

The dwc2 controllers used create really big number of interrupts in
special constellations involving usb-hubs and their number is so high,
it can even overwhelm the interrupt handler if the cpu-speed os to low.

Right now the PLLs are put into slow-mode in a shutdown syscore_ops
callback which means it happens on all reboots (not only the soft-reset
ones) and even on poweroff actions.

This can result in the system not powering off and getting stuck instead,
so we should move the slow-mode change nearer to the actual reboot action.

For this we introduce the possiblity to also set a callback that gets
called from the restart-handler directly prior to restarting the system
and move the shutdown-callback to this new option.

With this the slow-mode switch is done only on the necessary reboots
and also has a smaller possibility of causing artifacts.

Fixes: 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288")
Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
(cherry picked from commit dfff24bde7fb8d57482e907d5dfb0be3a9e28119)

Conflicts:

drivers/clk/rockchip/clk-rk3228.c
[zx: there is no rk3228 clock controller, apply for clk-rk3366]

Change-Id: I2e91afd893c87eb3ab8a41db1fe81f5c43409951
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: switch PLLs to slow mode before reboot for rk3288

We've been seeing some crashes at reboot test on rk3288-based systems,
which boards have not reset pin connected to NPOR, they reboot by
setting 0xfdb9 to RK3288_GLB_SRST_FST register. If the APLL works in
a high frequency mode, some IPs might hang during soft reset.
It appears that we can fix the problem by switching to slow mode before
reboot, just like what we did before suspend.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 1d33929e2a2b69ae6d40e09ccfc8c7d705a543ba)

Change-Id: Ic01f80e6f33ae84cc87e954aae35f26b6f1a5434
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: dts: rockchip: rk3366: add usb2.0 phy node

Change-Id: Ib1bc0add32d99de9ed78e70c29526cef926c7cad
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

phy: rockchip-usb: support InnoSilicon usb2.0 phy

For InnoSilicon usb2.0 phy, there is no siddq bit for operating,
what is more, when we control usb phy to suspend, its Plls will
not be affected. So we can operate resume/suspend bits directly
when it is going to power on/off.

Change-Id: I6bfe6b1a90b1bdcb0b0d5b670d579a625b22c0ba
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

Documentation: bindings: add compatible entry for Rockchip USB2.0 PHY

Compatible "rockchip,rk336x-usb-phy" support to RK3368 & RK3366.

Change-Id: I435ecd0a9f1c2a50836f7e3c44b6089ba49d728a
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

UPSTREAM: clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type

Because there are some frac clock mux nodes don't have a gate node on
the RK3399.

Change-Id: I4791b90a08faab286743a5cba30738cfb046594c
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next
 commit ffd9d4d39ef7ff90364d3abd6c39919e6582b605)

clk: rockchip: add clock ids for mpll_src and 32k on RK3366

Set the newly added id for mpll_src and 32k, so that they can be called
in other parts.

Change-Id: Ief82231215a147b62abcfbb5565054470fc9ea37
Signed-off-by: Feng Xiao <xf@rock-chips.com>