Move the ARM so_imm encoding into a custom operand encoder and remove the
explicit handling of the instructions referencing it from the MC code
emitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116367 91177308-0d34-0410-b5e6-96231b3b80d8

Be nitpicky and line up the comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116365 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor some of the encoding logic into a base class. This keeps us from having
to add 10+ lines to every instruction.

It may turn out that we can move this base class into it's parent class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116362 91177308-0d34-0410-b5e6-96231b3b80d8

Add custom encoder for the 's' bit denoting whether an ARM arithmetic
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116360 91177308-0d34-0410-b5e6-96231b3b80d8

Add encoding for VSUB and VCMP.

Fear not! I'm going to try a refactoring right now. :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116359 91177308-0d34-0410-b5e6-96231b3b80d8

Don't need to specify calling convention. Add 'readnone' to functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116354 91177308-0d34-0410-b5e6-96231b3b80d8

Allow targets to optionally specify custom binary encoder functions for
operand values. This is useful for operands which require additional trickery
to encode into the instruction. For example, the ARM shifted immediate and
shifted register operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116353 91177308-0d34-0410-b5e6-96231b3b80d8

Encoding for VADDD. Plus a test for the VFP instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116348 91177308-0d34-0410-b5e6-96231b3b80d8

Split out the "size" field from the encoding. The newer documentation has it as
a separate bit in the coding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116347 91177308-0d34-0410-b5e6-96231b3b80d8

Fix thinko in arm fast isel alloca rewrite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116339 91177308-0d34-0410-b5e6-96231b3b80d8

Encoding for ARM-mode VADD.F32 instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116338 91177308-0d34-0410-b5e6-96231b3b80d8

Begin adding static dependence information to passes, which will allow us to
perform initialization without static constructors AND without explicit initialization
by the client.  For the moment, passes are required to initialize both their
(potential) dependencies and any passes they preserve.  I hope to be able to relax
the latter requirement in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116334 91177308-0d34-0410-b5e6-96231b3b80d8

Combine these together - should probably have some text associated
that says what why what we just asserted is wrong.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116333 91177308-0d34-0410-b5e6-96231b3b80d8

KillTheDoctor: Fix VS2008 build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116330 91177308-0d34-0410-b5e6-96231b3b80d8

Mark variable 'NoImplicitFloatOps' used only in an assert as used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116323 91177308-0d34-0410-b5e6-96231b3b80d8

Comment grammar tweakage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116322 91177308-0d34-0410-b5e6-96231b3b80d8

Add MOVi ARM encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116321 91177308-0d34-0410-b5e6-96231b3b80d8

Initial va_arg support for x86-64. Patch by David Meyer!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116319 91177308-0d34-0410-b5e6-96231b3b80d8

Nuke unused wrapper function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116318 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions.

The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.

The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116314 91177308-0d34-0410-b5e6-96231b3b80d8

Add encoding information for the remainder of the generic arithmetic
ARM instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116313 91177308-0d34-0410-b5e6-96231b3b80d8

PR8359: The ARM backend may end up allocating registers D16 to D31 when
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers.  Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116310 91177308-0d34-0410-b5e6-96231b3b80d8

Rework alloca handling so that we can load or store from casted
address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116296 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the last two commits to configure - configure is a generated file.
Made necessary edits to configure.ac and regenerated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116291 91177308-0d34-0410-b5e6-96231b3b80d8

Handle a wider arrangement of loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116284 91177308-0d34-0410-b5e6-96231b3b80d8

Fix spelling error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116282 91177308-0d34-0410-b5e6-96231b3b80d8

Delete a redundant check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116280 91177308-0d34-0410-b5e6-96231b3b80d8

More SmallVectorImpls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116279 91177308-0d34-0410-b5e6-96231b3b80d8

Shrink a SmallVector with a known maximum size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116278 91177308-0d34-0410-b5e6-96231b3b80d8

Constify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116277 91177308-0d34-0410-b5e6-96231b3b80d8

Use SmallVectorImpl in a bunch of places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116276 91177308-0d34-0410-b5e6-96231b3b80d8

Disable warning C4267 for MSVC. Otherwise it generate literally thousands of warnings when targeting x64. The warning occurs because int is 32 bit but size_t is 64 bit on Win64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116274 91177308-0d34-0410-b5e6-96231b3b80d8

Add a simple testcase for tbaa.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116272 91177308-0d34-0410-b5e6-96231b3b80d8

More ARM scheduling itinerary fixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116266 91177308-0d34-0410-b5e6-96231b3b80d8

Support AA chaining.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116264 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the pass manager's search order for immutable passes, and make it
stop searching when it has found a match.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116262 91177308-0d34-0410-b5e6-96231b3b80d8

MC machine encoding for simple aritmetic instructions that use a shifted
register operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8

Second set of ARM/MC/ELF changes.

Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116257 91177308-0d34-0410-b5e6-96231b3b80d8

Clang's #include handling apparently doesn't work for libstdc++'s
fenv.h. See PR6907 for details. Work around this in FEnv.h to fix
the seflhost build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116256 91177308-0d34-0410-b5e6-96231b3b80d8

Unit Tests: Missed this error. MSVC and clang didn't complain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116252 91177308-0d34-0410-b5e6-96231b3b80d8

Proper VST scheduling itineraries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116251 91177308-0d34-0410-b5e6-96231b3b80d8

Use a sane mechanism for that assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116249 91177308-0d34-0410-b5e6-96231b3b80d8

System: Add SwapByteOrder and update Support/MathExtras.h to use it.

This time correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116247 91177308-0d34-0410-b5e6-96231b3b80d8

Replace FindLiveRangeContaining() with getVNInfoAt() in LiveIntervalAnalysis.

This helps hiding the LiveRange class which really should be private.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116244 91177308-0d34-0410-b5e6-96231b3b80d8

The assert() should reference to machine instr operand number, too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116243 91177308-0d34-0410-b5e6-96231b3b80d8

Revert "System: Add SwapByteOrder and update Support/MathExtras.h to use it."

This reverts commit 116234.

It compiled just fine with MSVC and clang...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116242 91177308-0d34-0410-b5e6-96231b3b80d8

We're not going to handle dynamic allocas anywhere else.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116240 91177308-0d34-0410-b5e6-96231b3b80d8

Change explicit search Apple specific code to only reference __eprintf on x86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116239 91177308-0d34-0410-b5e6-96231b3b80d8

Make sure to use the machine instruction operand number. It doesn't always
map one-to-one with the CodeGenInstruction operand number.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116238 91177308-0d34-0410-b5e6-96231b3b80d8

Reduce dpendencies for SupportTests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116235 91177308-0d34-0410-b5e6-96231b3b80d8

System: Add SwapByteOrder and update Support/MathExtras.h to use it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116234 91177308-0d34-0410-b5e6-96231b3b80d8

Make sure that the call stack adjustments have default operands. Also
leave custom lowerings for later.

Fixes some nightly tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116232 91177308-0d34-0410-b5e6-96231b3b80d8

PR8297

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116223 91177308-0d34-0410-b5e6-96231b3b80d8

PowerPC varargs functions store live-in registers on the stack. Make sure we use
virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.

This fixes PR8357.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116222 91177308-0d34-0410-b5e6-96231b3b80d8

Found a bug turning this on by default. Disable again for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116220 91177308-0d34-0410-b5e6-96231b3b80d8

Remove now non-existent option.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116219 91177308-0d34-0410-b5e6-96231b3b80d8

Fix help text.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116218 91177308-0d34-0410-b5e6-96231b3b80d8

Change flag from Enable to Disable since we're enabled by default.
Also don't use fast-isel on non-darwin since it's untested.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116217 91177308-0d34-0410-b5e6-96231b3b80d8

Add KillTheDoctor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116216 91177308-0d34-0410-b5e6-96231b3b80d8

trailing whitespace cleanup

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116215 91177308-0d34-0410-b5e6-96231b3b80d8

Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116214 91177308-0d34-0410-b5e6-96231b3b80d8

More binary encoding stuff, taking advantage of the new "by name" operand
matching in tblgen to do the predicate operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116213 91177308-0d34-0410-b5e6-96231b3b80d8

Turn on arm fast isel by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116212 91177308-0d34-0410-b5e6-96231b3b80d8

When figuring out which operands match which encoding fields in an instruction,
try to match them by name first. If there is no by-name match, fall back to
assuming they are in order (this was the previous behavior).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116211 91177308-0d34-0410-b5e6-96231b3b80d8

Properly handle reloading and spilling around partial redefines in
LocalRewriter.

This is a bit of a hack that adds an implicit use operand to model the
read-modify-write nature of a partial redef. Uses and defs are rewritten in
separate passes, and a single operand would never be processed twice.

<rdar://problem/8518892>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116210 91177308-0d34-0410-b5e6-96231b3b80d8

remove dead prototype, PR8351

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116209 91177308-0d34-0410-b5e6-96231b3b80d8

MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116201 91177308-0d34-0410-b5e6-96231b3b80d8

Copy and pasteo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116198 91177308-0d34-0410-b5e6-96231b3b80d8

Whitespace cleanup in ARM fast isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116197 91177308-0d34-0410-b5e6-96231b3b80d8

Add srem libcall support to ARM fast isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116196 91177308-0d34-0410-b5e6-96231b3b80d8

Add i8 sdiv support for ARM fast isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116195 91177308-0d34-0410-b5e6-96231b3b80d8

Implement select handling for ARM fast-isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116194 91177308-0d34-0410-b5e6-96231b3b80d8

tweak comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116192 91177308-0d34-0410-b5e6-96231b3b80d8

Per discussion with Sanjiv, remove the PIC16 target from mainline.  When/if
it comes back, it will be largely a rewrite, so keeping the old codebase
in tree isn't helping anyone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116190 91177308-0d34-0410-b5e6-96231b3b80d8

X86: Call ulldiv and ftol2 on Windows instead of their libgcc eqivilents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116188 91177308-0d34-0410-b5e6-96231b3b80d8

X86: MinGW should always use libgcc on Windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116177 91177308-0d34-0410-b5e6-96231b3b80d8

X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116174 91177308-0d34-0410-b5e6-96231b3b80d8

Fix Whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116173 91177308-0d34-0410-b5e6-96231b3b80d8

force a triple, varargs isn't supported with the SVR4 ABI the buildbot tells me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116170 91177308-0d34-0410-b5e6-96231b3b80d8

fix the default va_arg expansion (in the realignment case) to not implicitly
truncate the stack pointer to 32-bits on a 64-bit machine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116169 91177308-0d34-0410-b5e6-96231b3b80d8

fix the expansion of va_arg instruction on PPC to know the arg
alignment for PPC32/64, avoiding some masking operations.

llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116168 91177308-0d34-0410-b5e6-96231b3b80d8

clarify that zero sized vectors are illegal, PR8340

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116167 91177308-0d34-0410-b5e6-96231b3b80d8

Now using a variant of the existing inlining heuristics to decide whether to create a given specialization of a function in PartialSpecialization.  If the total performance bonus across all callsites passing the same constant exceeds the specialization cost, we create the specialization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116158 91177308-0d34-0410-b5e6-96231b3b80d8

Fix dead link.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116157 91177308-0d34-0410-b5e6-96231b3b80d8

Silence compiler warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116156 91177308-0d34-0410-b5e6-96231b3b80d8

MC-COFF: Fix .bss section size. Fixes PR8335. Patch by NAKAMUTA Takumi!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116155 91177308-0d34-0410-b5e6-96231b3b80d8

Don't test a removed function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116154 91177308-0d34-0410-b5e6-96231b3b80d8

syntax-highlighting: Fix module asm keyword.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116152 91177308-0d34-0410-b5e6-96231b3b80d8

MC-COFF: Implement InitSections. Fixes PR8335.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116151 91177308-0d34-0410-b5e6-96231b3b80d8

MC-COFF: Add COFFAsmParser. Completes PR8343.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116150 91177308-0d34-0410-b5e6-96231b3b80d8

Fix Whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116149 91177308-0d34-0410-b5e6-96231b3b80d8

MC-COFF: Assert on non-coff sections.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116148 91177308-0d34-0410-b5e6-96231b3b80d8

Add Kate syntax highlighting files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116146 91177308-0d34-0410-b5e6-96231b3b80d8

Add VLD4 scheduling itineraries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116143 91177308-0d34-0410-b5e6-96231b3b80d8

MC: Move ParseDirectiveELFType into ELFAsmParser. COFF uses .type for something else.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116142 91177308-0d34-0410-b5e6-96231b3b80d8

Finish vld3 and vld4.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116140 91177308-0d34-0410-b5e6-96231b3b80d8

Complete vld2 instruction itineries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116136 91177308-0d34-0410-b5e6-96231b3b80d8

Multiply instructions are issued on pipeline 0. They do not need to reserve pipeline 1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116135 91177308-0d34-0410-b5e6-96231b3b80d8

Correct some load / store instruction itinerary mistakes:
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116134 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify test and move into a generic "crash" ll file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116130 91177308-0d34-0410-b5e6-96231b3b80d8