Hal Finkel [Wed, 27 Mar 2013 13:20:52 +0000 (13:20 +0000)]
Print PPC ZERO as 0 (not r0) even on Darwin
It seems that the Darwin PPC assembler requires r0 to be written as 0 when it
means 0 (at least in lwarx/stwcx.). Fixes PR15605.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178142
91177308-0d34-0410-b5e6-
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Tim Northover [Wed, 27 Mar 2013 13:15:08 +0000 (13:15 +0000)]
Switch to LLVM support function abs64 to keep VS2008 happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178141
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Evgeniy Stepanov [Wed, 27 Mar 2013 13:11:12 +0000 (13:11 +0000)]
Disable ASan/MSan symbolization of reports in tests.
It was using an instrumented symbolizer binary, which is a potential fork bomb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178139
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Hal Finkel [Wed, 27 Mar 2013 13:00:56 +0000 (13:00 +0000)]
Fix target-customized spilling in the register scavenger
This is a follow-up to r178073 (which should actually make target-customized
spilling work again).
I still don't have a regression test for this (but it would be good to have
one; Thumb 1 and Mips16 use this callback as well).
Patch by Richard Sandiford.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178137
91177308-0d34-0410-b5e6-
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Evgeniy Stepanov [Wed, 27 Mar 2013 12:50:49 +0000 (12:50 +0000)]
Disable Initialize.MultipleThreads test under MemorySanitizer.
Fails due to insufficient thread stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178135
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Silviu Baranga [Wed, 27 Mar 2013 12:38:44 +0000 (12:38 +0000)]
Enabling the generation of dependency breakers for partial updates on Cortex-A15. Also fixing a small bug in getting the update clearence for VLD1LNd32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178134
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Jyotsna Verma [Wed, 27 Mar 2013 11:14:24 +0000 (11:14 +0000)]
Hexagon: Disable optimizations at O0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178132
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James Molloy [Wed, 27 Mar 2013 10:23:32 +0000 (10:23 +0000)]
Improve performance of LinkModules when linking with modules with large numbers of functions which link lazily. Instead of creating and destroying function prototypes irrespective of if they are used, only create them if they are used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178130
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Christian Konig [Wed, 27 Mar 2013 09:12:59 +0000 (09:12 +0000)]
R600/SI: add cummuting of rev instructions
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178127
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Christian Konig [Wed, 27 Mar 2013 09:12:51 +0000 (09:12 +0000)]
R600/SI: add mulhu/mulhs patterns
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178126
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Christian Konig [Wed, 27 Mar 2013 09:12:44 +0000 (09:12 +0000)]
R600/SI: add srl/sha patterns for SI
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178125
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Hal Finkel [Wed, 27 Mar 2013 06:52:27 +0000 (06:52 +0000)]
Allocate r0 on PPC
The R0 register can now be allocated because instructions
that cannot use R0 as a GPR have been appropriately marked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178123
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Hal Finkel [Wed, 27 Mar 2013 06:36:55 +0000 (06:36 +0000)]
Use the PPC no-r0 class on the TOC LD pseudos
The register parameter in these instructions becomes the base register in an
r+i ld instruction (and, thus, cannot be r0).
This is not yet testable because we don't yet allocate r0 (and even then any
test would be very fragile).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178121
91177308-0d34-0410-b5e6-
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Hal Finkel [Wed, 27 Mar 2013 05:57:58 +0000 (05:57 +0000)]
Apply the no-r0 register class to the PPC SELECT_CC_I[4|8] pseudos
Either operand of these pseudo instructions can be transformed into the first
operand of an isel instruction (and this operand cannot be r0).
This is not yet testable because we don't yet allocate r0 (and even when we do,
any test would be very fragile).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178119
91177308-0d34-0410-b5e6-
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Hal Finkel [Wed, 27 Mar 2013 05:57:56 +0000 (05:57 +0000)]
Apply the no-r0 class to PPC TOC ADDI[S] pseudo instructions
Like the addi/addis instructions themselves, these pseudo instructions also
cannot have r0 as their register parameter (because it will be interpreted as
the value 0).
This is not yet testable because we don't yet allocate r0 (and even when we do,
any regression test would be very fragile because it would depend on the
register allocator heuristics).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178118
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Bill Schmidt [Wed, 27 Mar 2013 02:40:14 +0000 (02:40 +0000)]
Remove the link register from the GPR classes on PowerPC.
Some implementation detail in the forgotten past required the link
register to be placed in the GPRC and G8RC register classes. This is
just wrong on the face of it, and causes several extra intersection
register classes to be generated. I found this was having evil
effects on instruction scheduling, by causing the wrong register class
to be consulted for register pressure decisions.
No code generation changes are expected, other than some minor changes
in instruction order. Seven tests in the test bucket required minor
tweaks to adjust to the new normal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178114
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Michael Gottesman [Wed, 27 Mar 2013 00:09:58 +0000 (00:09 +0000)]
Added back in the test for arc-annotations.
The test was removed since I had not turned off the test during release
builds. This fails since ARC annotations support is conditionally
compiled out during release builds. I added the proper requires header
to assuage this issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178101
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David Blaikie [Wed, 27 Mar 2013 00:07:26 +0000 (00:07 +0000)]
Adding DIImportedModules to DIScopes.
This is just the basic groundwork for supporting DW_TAG_imported_module but I
wanted to commit this before pushing support further into Clang or LLVM so that
this rather churny change is isolated from the rest of the work. The major
churn here is obviously adding another field (within the common DIScope prefix)
to all DIScopes (files, classes, namespaces, lexical scopes, etc). This should
be the last big churny change needed for DW_TAG_imported_module/using directive
support/PR14606.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178099
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Hal Finkel [Wed, 27 Mar 2013 00:02:20 +0000 (00:02 +0000)]
Don't spill PPC VRSAVE on non-Darwin (even in SjLj)
As Bill Schmidt pointed out to me, only on Darwin do we need to spill/restore
VRSAVE in the SjLj code. For non-Darwin, don't spill/restore VRSAVE (and I've
added some asserts to make sure that we're not).
As it turns out, we're not currently handling the Darwin case correctly (I've
added a FIXME in the test case). I've tried adding various implied register
definitions/uses to force the spill without success, so I'll need to address
this later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178096
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David Blaikie [Tue, 26 Mar 2013 23:46:39 +0000 (23:46 +0000)]
Make DIBuilder::createClassType more type safe by returning DICompositeType rather than DIType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178091
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David Blaikie [Tue, 26 Mar 2013 23:46:36 +0000 (23:46 +0000)]
DebugInfo: more support for mutating DICompositeType to reduce magic number usage in Clang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178090
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Chad Rosier [Tue, 26 Mar 2013 23:35:00 +0000 (23:35 +0000)]
Add a boolean parameter to the ExecuteAndWait static function to indicated
if execution failed. ExecuteAndWait returns -1 upon an execution failure, but
checking the return value isn't sufficient because the wait command may
return -1 as well. This new parameter is to be used by the clang driver in a
subsequent commit.
Part of rdar://
13362359
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178087
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Bill Wendling [Tue, 26 Mar 2013 22:47:50 +0000 (22:47 +0000)]
Use the full path when outputting the `.gcda' file.
If we compile a single source program, the `.gcda' file will be generated where
the program was executed. This isn't desirable, because that place may be at an
unpredictable place (the program could call `chdir' for instance).
Instead, we will output the `.gcda' file in the same place we output the `.gcno'
file. I.e., the directory where the executable was generated. This matches GCC's
behavior.
<rdar://problem/
13061072> & PR11809
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178084
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Michael Liao [Tue, 26 Mar 2013 22:47:01 +0000 (22:47 +0000)]
Add XTEST codegen support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178083
91177308-0d34-0410-b5e6-
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Michael Liao [Tue, 26 Mar 2013 22:46:02 +0000 (22:46 +0000)]
Add HLE target feature
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178082
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Jakob Stoklund Olesen [Tue, 26 Mar 2013 22:19:12 +0000 (22:19 +0000)]
Enable SandyBridgeModel for all modern Intel P6 descendants.
All Intel CPUs since Yonah look a lot alike, at least at the granularity
of the scheduling models. We can add more accurate models for
processors that aren't Sandy Bridge if required. Haswell will probably
need its own.
The Atom processor and anything based on NetBurst is completely
different. So are the non-Intel chips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178080
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David Blaikie [Tue, 26 Mar 2013 21:59:17 +0000 (21:59 +0000)]
Debug Info: Provide a means to update the members of a composite type
This will be used to factor out some uses of magic number operand offsets
inside Clang where these fields were updated in an effort to resolve forward
declarations/circular references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178078
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Hal Finkel [Tue, 26 Mar 2013 21:50:26 +0000 (21:50 +0000)]
Restore real bit lengths on PPC register numbers
As suggested by Bill Schmidt (in reviewing r178067), use the real register
number bit lengths (which is self-documenting, and prevents using illegal
numbers), and set only the relevant bits in HWEncoding (which defaults to 0).
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178077
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Andrew Trick [Tue, 26 Mar 2013 21:36:39 +0000 (21:36 +0000)]
TableGen SubtargetEmitter fix to allow A9 and Swift to coexist.
Allow variants to be defined only for some processors on a target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178074
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Hal Finkel [Tue, 26 Mar 2013 21:20:15 +0000 (21:20 +0000)]
Fix the register scavenger for targets that provide custom spilling
As pointed out by Richard Sandiford, my recent updates to the register
scavenger broke targets that use custom spilling (because the new code assumed
that if there were no valid spill slots, than spilling would be impossible).
I don't have a test case, but it should be possible to create one for Thumb 1,
Mips 16, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178073
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Hal Finkel [Tue, 26 Mar 2013 20:08:20 +0000 (20:08 +0000)]
PPC: Use HWEncoding and TRI->getEncodingValue
As pointed out by Jakob, we don't need to maintain a separate
register-numbering table. Instead we should let TableGen generate the table for
us from the information (already present) in PPCRegisterInfo.td.
TRI->getEncodingValue is now used to access register-encoding values.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178067
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NAKAMURA Takumi [Tue, 26 Mar 2013 19:42:48 +0000 (19:42 +0000)]
R600/SIMCCodeEmitter.cpp: Prune a couple of unused members, STI and Ctx. [-Wunused-private-field]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178065
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Hal Finkel [Tue, 26 Mar 2013 18:57:22 +0000 (18:57 +0000)]
Use multiple virtual registers in PPC CR spilling
Now that the register scavenger can support multiple spill slots, and PEI can
use virtual-register-based scavenging for multiple simultaneous registers, we
can use a virtual register for the transfer register in the CR spilling code.
This should eliminate the last place (outside of the prologue/epilogue) where
we depend on the unconditional availability of the r0 register. We will soon be
able to allocate it (in a somewhat restricted sense) as a GPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178060
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Hal Finkel [Tue, 26 Mar 2013 18:57:20 +0000 (18:57 +0000)]
Update PPCRegisterInfo's use of virtual registers to be SSA
PPC's use of PEI's virtual-register-based scavenging functionality had
redefined the virtual registers (it was non-SSA). Now that PEI supports
dealing with instructions with multiple virtual registers, this can be
cleanup up to use multiple virtual registers and keep SSA form.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178059
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Hal Finkel [Tue, 26 Mar 2013 18:56:54 +0000 (18:56 +0000)]
Update PEI's virtual-register-based scavenging to support multiple simultaneous mappings
The previous algorithm could not deal properly with scavenging multiple virtual
registers because it kept only one live virtual -> physical mapping (and
iterated through operands in order). Now we don't maintain a current mapping,
but rather use replaceRegWith to completely remove the virtual register as
soon as the mapping is established.
In order to allow the register scavenger to return a physical register killed
by an instruction for definition by that same instruction, we now call
RS->forward(I) prior to eliminating virtual registers defined in I. This
requires a minor update to forward to ignore virtual registers.
These new features will be tested in forthcoming commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178058
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Jakob Stoklund Olesen [Tue, 26 Mar 2013 18:24:22 +0000 (18:24 +0000)]
Annotate the remaining x86 instructions with SchedRW lists.
Now all x86 instructions that have itinerary classes also have SchedRW
lists. This is required before the new scheduling models can be used.
There are still unannotated instructions remaining, but they don't have
itinerary classes either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178051
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Jakob Stoklund Olesen [Tue, 26 Mar 2013 18:24:20 +0000 (18:24 +0000)]
Annotate x87 and mmx instructions with SchedRW lists.
This only covers the instructions that were given itinerary classes for
the Atom model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178050
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Jakob Stoklund Olesen [Tue, 26 Mar 2013 18:24:17 +0000 (18:24 +0000)]
Annotate control instructions with SchedRW lists.
This could definitely be more granular. I am not sure if it makes a
difference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178049
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Jakob Stoklund Olesen [Tue, 26 Mar 2013 18:24:15 +0000 (18:24 +0000)]
Annotate the rest of X86InstrInfo.td with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178048
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Michael Liao [Tue, 26 Mar 2013 18:15:45 +0000 (18:15 +0000)]
Fix PRFCHW test on non-x86 builds
- 'prefetch' intrinsics are only lowered when SSE is available. On non-X86
builds, 'generic' CPU is used and stops lowering any prefetch intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178046
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Arnold Schwaighofer [Tue, 26 Mar 2013 18:07:53 +0000 (18:07 +0000)]
BasicAA: Only query twice if the result of the more general query was MayAlias
This is a compile time optimization. Before the patch we would do two traversals
on each call to aliasGEP - one with a set size parameter one with UnknownSize.
We can do better by first checking the result of the alias query with
UnknownSize.
Only if this one returns MayAlias do we query a second time using size and type.
This recovers an about 7% compile time regression on spec/ammp.
radar://
12349960
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178045
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Michael Liao [Tue, 26 Mar 2013 17:47:11 +0000 (17:47 +0000)]
Add PREFETCHW codegen support
- Add 'PRFCHW' feature defined in AVX2 ISA extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178040
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Ulrich Weigand [Tue, 26 Mar 2013 17:30:02 +0000 (17:30 +0000)]
Add test case for commit r178031.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178038
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Jyotsna Verma [Tue, 26 Mar 2013 15:43:57 +0000 (15:43 +0000)]
Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178032
91177308-0d34-0410-b5e6-
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Ulrich Weigand [Tue, 26 Mar 2013 15:36:14 +0000 (15:36 +0000)]
Make InstCombineCasts.cpp:OptimizeIntToFloatBitCast endian safe.
The OptimizeIntToFloatBitCast converts shift-truncate sequences
into extractelement operations. The computation of the element
index to be used in the resulting operation is currently only
correct for little-endian targets.
This commit fixes the element index computation to be correct
for big-endian targets as well. If the target byte order is
unknown, the optimization cannot be performed at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178031
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Jyotsna Verma [Tue, 26 Mar 2013 15:34:22 +0000 (15:34 +0000)]
Hexagon: Remove HexagonMCInst.h file. It has been replaced with MCTargetDesc/HexagonMCInst.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178030
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Arnold Schwaighofer [Tue, 26 Mar 2013 15:14:04 +0000 (15:14 +0000)]
Revert ARM Scheduler Model: Add resources instructions, map resources
This reverts commit r177968. It is causing failures in a local build bot.
"fatal error: error in backend: Expected a variant SchedClass"
Original commit message:
Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178028
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Tue, 26 Mar 2013 14:17:42 +0000 (14:17 +0000)]
Remove default case from fully covered switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178025
91177308-0d34-0410-b5e6-
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Christian Konig [Tue, 26 Mar 2013 14:04:17 +0000 (14:04 +0000)]
R600/SI: improve post ISel folding
Not only fold immediates, but avoid unnecessary copies as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178024
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Christian Konig [Tue, 26 Mar 2013 14:04:12 +0000 (14:04 +0000)]
R600/SI: improve vector interpolation
Prevent loading M0 multiple times.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178023
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Christian Konig [Tue, 26 Mar 2013 14:04:07 +0000 (14:04 +0000)]
R600/SI: avoid unecessary subreg extraction in IMAGE_SAMPLE
Just define the address as unknown instead of VReg_32.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178022
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Christian Konig [Tue, 26 Mar 2013 14:04:02 +0000 (14:04 +0000)]
R600/SI: switch back to RegPressure scheduling
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178021
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Christian Konig [Tue, 26 Mar 2013 14:03:57 +0000 (14:03 +0000)]
R600/SI: mark most intrinsics as readnone v2
They read from constant register space anyway.
v2: fix lit tests
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178020
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Christian Konig [Tue, 26 Mar 2013 14:03:50 +0000 (14:03 +0000)]
R600/SI: replace WQM intrinsic
Just enable WQM when we see an LDS interpolation instruction.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178019
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Christian Konig [Tue, 26 Mar 2013 14:03:44 +0000 (14:03 +0000)]
R600/SI: fix ELSE pseudo op handling
Restore the EXEC mask early, otherwise a copy might end up not beeing executed.
Candidate for the mesa stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178018
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Joe Abbey [Tue, 26 Mar 2013 13:58:53 +0000 (13:58 +0000)]
Patch by Gordon Keiser!
If PC or SP is the destination, the disassembler erroneously failed with the
invalid encoding, despite the manual saying that both are fine.
This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a
postindexed load, where the offset 0xc is applied to SP after the load occurs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178017
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Alexey Samsonov [Tue, 26 Mar 2013 13:05:41 +0000 (13:05 +0000)]
[ASan] Change the ABI of __asan_before_dynamic_init function: now it takes pointer to private string with module name. This string serves as a unique module ID in ASan runtime. LLVM part
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178013
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Ulrich Weigand [Tue, 26 Mar 2013 10:57:16 +0000 (10:57 +0000)]
PowerPC: Mark patterns as isCodeGenOnly.
There remain a number of patterns that cannot (and should not)
be handled by the asm parser, in particular all the Pseudo patterns.
This commit marks those patterns as isCodeGenOnly.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178008
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Ulrich Weigand [Tue, 26 Mar 2013 10:56:47 +0000 (10:56 +0000)]
PowerPC: Simplify handling of fixups.
MCTargetDesc/PPCMCCodeEmitter.cpp current has code like:
if (isSVR4ABI() && is64BitMode())
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_toc16));
else
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_lo16));
This is a problem for the asm parser, since it requires knowledge of
the ABI / 64-bit mode to be set up. However, more fundamentally,
at this point we shouldn't make such distinctions anyway; in an assembler
file, it always ought to be possible to e.g. generate TOC relocations even
when the main ABI is one that doesn't use TOC.
Fortunately, this is actually completely unnecessary; that code was added
to decide whether to generate TOC relocations, but that information is in
fact already encoded in the VariantKind of the underlying symbol.
This commit therefore merges those fixup types into one, and then decides
which relocation to use based on the VariantKind.
No changes in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178007
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Ulrich Weigand [Tue, 26 Mar 2013 10:56:22 +0000 (10:56 +0000)]
PowerPC: Simplify FADD in round-to-zero mode.
As part of the the sequence generated to implement long double -> int
conversions, we need to perform an FADD in round-to-zero mode. This is
problematical since the FPSCR is not at all modeled at the SelectionDAG
level, and thus there is a risk of getting floating point instructions
generated out of sequence with the instructions to modify FPSCR.
The current code handles this by somewhat "special" patterns that in part
have dummy operands, and/or duplicate existing instructions, making them
awkward to handle in the asm parser.
This commit changes this by leaving the "FADD in round-to-zero mode"
as an atomic operation on the SelectionDAG level, and only split it up into
real instructions at the MI level (via custom inserter). Since at *this*
level the FPSCR *is* modeled (via the "RM" hard register), much of the
"special" stuff can just go away, and the resulting patterns can be used by
the asm parser.
No significant change in generated code expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178006
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Ulrich Weigand [Tue, 26 Mar 2013 10:55:45 +0000 (10:55 +0000)]
PowerPC: Remove LDrs pattern.
The LDrs pattern is a duplicate of LD, except that it accepts memory
addresses where the displacement is a symbolLo64. An operand type
"memrs" is defined for just that purpose.
However, this wouldn't be necessary if the default "memrix" operand
type were to simply accept 64-bit symbolic addresses directly.
The only problem with that is that it uses "symbolLo", which is
hardcoded to 32-bit.
To fix this, this commit changes "memri" and "memrix" to use new
operand types for the memory displacement, which allow iPTR
instead of i32. This will also make address parsing easier to
implment in the asm parser.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178005
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Ulrich Weigand [Tue, 26 Mar 2013 10:55:20 +0000 (10:55 +0000)]
PowerPC: Remove ADDIL patterns.
The ADDI/ADDI8 patterns are currently duplicated into ADDIL/ADDI8L,
which describe the same instruction, except that they accept a
symbolLo[64] operand instead of a s16imm[64] operand.
This duplication confuses the asm parser, and it actually not really
needed, since symbolLo[64] already accepts immediate operands anyway.
So this commit removes the duplicate patterns.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178004
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Ulrich Weigand [Tue, 26 Mar 2013 10:54:54 +0000 (10:54 +0000)]
PowerPC: Use CCBITRC operand for ISEL patterns.
This commit changes the ISEL patterns to use a CCBITRC operand
instead of a "pred" operand. This matches the actual instruction
text more directly, and simplifies use of ISEL with the asm parser.
In addition, this change allows some simplification of handling
the "pred" operand, as this is now only used by BCC.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178003
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Ulrich Weigand [Tue, 26 Mar 2013 10:53:27 +0000 (10:53 +0000)]
PowerPC: Simplify BLR pattern.
The BLR pattern cannot be recognized by the asm parser in its current form.
This complexity is due to an apparent attempt to enable conditional BLR
variants. However, none of those can ever be generated by current code;
the pattern is only ever created using the default "pred" operand.
To simplify the pattern and allow it to be recognized by the parser,
this commit removes those attempts at conditional BLR support.
When we later come back to actually add real conditional BLR, this
should probably be done via a fully generic conditional branch pattern.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178002
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Ulrich Weigand [Tue, 26 Mar 2013 10:53:03 +0000 (10:53 +0000)]
PowerPC: Move some 64-bit branch patterns.
In PPCInstr64Bit.td, some branch patterns appear in a different sequence
than the corresponding 32-bit patterns in PPCInstrInfo.td.
To simplify future changes that affect both files, this commit moves
those patterns to rearrange them into a similar sequence.
No effect on generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178001
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Christian Konig [Tue, 26 Mar 2013 10:24:20 +0000 (10:24 +0000)]
R600: fix DenseMap with pointer key iteration in the structurizer
Use a MapVector on types where the iteration order matters.
Otherwise we doesn't always produce a deterministic output.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177999
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Alexey Samsonov [Tue, 26 Mar 2013 08:27:39 +0000 (08:27 +0000)]
Add asan/msan to the list of available features in LIT test runner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177994
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Alexey Samsonov [Tue, 26 Mar 2013 07:49:46 +0000 (07:49 +0000)]
Add CMake option LLVM_USE_SANITIZER={Address,Memory,MemoryWithOrigins} to simplify bootstrap of LLVM/Clang under ASan/MSan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177992
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Chandler Carruth [Tue, 26 Mar 2013 03:45:47 +0000 (03:45 +0000)]
Manually update the dependencies in the Makefiles. It turns out that all
that work on the LLVMBuild based dependency specification didn't
actually work, we just now maintain dependencies in *3* places instead
of 2. Yay.
There may still be some missing dependencies, I'm still sifting through
the bots and my builds, but this is a step in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177988
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Andrew Trick [Tue, 26 Mar 2013 03:14:53 +0000 (03:14 +0000)]
Fix SCEV forgetMemoizedResults should search and destroy backedge exprs.
Fixes PR15570: SEGV: SCEV back-edge info invalid after dead code removal.
Indvars creates a SCEV expression for the loop's back edge taken
count, then determines that the comparison is always true and
removes it.
When loop-unroll asks for the expression, it contains a NULL
SCEVUnknkown (as a CallbackVH).
forgetMemoizedResults should invalidate the loop back edges expression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177986
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Chandler Carruth [Tue, 26 Mar 2013 02:25:37 +0000 (02:25 +0000)]
Split out the IRReader header and the utility functions it provides into
its own library. These functions are bridging between the bitcode reader
and the ll parser which are in different libraries. Previously we didn't
have any good library to do this, and instead played fast and loose with
a "header only" set of interfaces in the Support library. This really
doesn't work well as evidenced by the recent attempt to add timing logic
to the these routines.
As part of this, make them normal functions rather than weird inline
functions, and sink the implementation into the library. Also clean up
the header to be nice and minimal.
This requires updating lots of build system dependencies to specify that
the IRReader library is needed, and several source files to not
implicitly rely upon the header file to transitively include all manner
of other headers.
If you are using IRReader.h, this commit will break you (the header
moved) and you'll need to also update your library usage to include
'irreader'. I will commit the corresponding change to Clang momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177971
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Arnold Schwaighofer [Tue, 26 Mar 2013 02:01:42 +0000 (02:01 +0000)]
ARM Scheduler Model: Add resources instructions, map resources in subtargets
Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177968
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Arnold Schwaighofer [Tue, 26 Mar 2013 02:01:39 +0000 (02:01 +0000)]
ARM Scheduler Model: Partial implementation of the new machine scheduler model
This is very much work in progress. Please send me a note if you start to depend
on the added abstract read/write resources. They are subject to change until
further notice.
The old itinerary is still the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177967
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Nick Lewycky [Tue, 26 Mar 2013 01:29:15 +0000 (01:29 +0000)]
Add missing file to cmake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177963
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Nick Lewycky [Tue, 26 Mar 2013 01:27:52 +0000 (01:27 +0000)]
Add a new watchdog timer interface. The interface does not permit handling timeouts, so
it's only really useful if you're going to crash anyways. Use it in the pretty stack trace
printer to kill the compiler if we hang while printing the stack trace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177962
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Bill Wendling [Tue, 26 Mar 2013 01:10:03 +0000 (01:10 +0000)]
Remove testcase. It's failing on some platforms but not others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177956
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Bill Wendling [Tue, 26 Mar 2013 01:08:02 +0000 (01:08 +0000)]
Hmm...not failing...odd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177955
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Bill Wendling [Tue, 26 Mar 2013 00:46:31 +0000 (00:46 +0000)]
Temporarily XFAIL this test until Michael can look at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177953
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Michael Gottesman [Tue, 26 Mar 2013 00:42:09 +0000 (00:42 +0000)]
[ObjCARC Annotations] Added support for displaying the state of pointers at the bottom/top of BBs of the ARC dataflow analysis for both bottomup and topdown analyses.
This will allow for verification and analysis of the merge function of
the data flow analyses in the ARC optimizer.
The actual implementation of this feature is by introducing calls to
the functions llvm.arc.annotation.{bottomup,topdown}.{bbstart,bbend}
which are only declared. Each such call takes in a pointer to a global
with the same name as the pointer whose provenance is being tracked and
a pointer whose name is one of our Sequence states and points to a
string that contains the same name.
To ensure that the optimizer does not consider these annotations in any
way, I made it so that the annotations are considered to be of IC_None
type.
A test case is included for this commit and the previous
ObjCARCAnnotation commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177952
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Michael Gottesman [Tue, 26 Mar 2013 00:42:04 +0000 (00:42 +0000)]
[ObjCARC Annotations] Implemented ARC annotation metadata to expose the ARC data flow analysis state in the IR via metadata.
Previously the inner works of the data flow analysis in ObjCARCOpts was hard to
get out of the optimizer for analysis of bugs or testing. All of the current ARC
unit tests are based off of testing the effect of the data flow
analysis (i.e. what statements are removed or moved, etc.). This creates
weakness in the current unit testing regimem since we are not actually testing
what effects various instructions have on the modeled pointer state.
Additionally in order to analyze a bug in the optimizer, one would need to track
by hand what the optimizer was actually doing either through use of DEBUG
statements or through the usage of a debugger, both yielding large loses in
developer productivity.
This patch deals with these two issues by providing ARC annotation
metadata that annotates instructions with the state changes that they cause in
various pointers as well as provides metadata to annotate provenance sources.
Specifically, we introduce the following metadata types:
1. llvm.arc.annotation.bottomup.
2. llvm.arc.annotation.topdown.
3. llvm.arc.annotation.provenancesource.
llvm.arc.annotation.{bottomup,topdown}: These annotations describes a state
change in a pointer when we are visiting instructions bottomup/topdown
respectively. The output format for both is the same:
!1 = metadata !{metadata !"(test,%x)", metadata !"S_Release", metadata !"S_Use"}
The first element is a string tuple with the following format:
(function,variable name)
The second two elements of the metadata show the previous state of the
pointer (in this case S_Release) and the new state of the pointer (S_Use). We
write the metadata in such a manner to ensure that it is easy for outside tools
to parse. This is important since I am currently working on a tool for taking
this information and pretty printing it besides the IR and that can be used for
LIT style testing via the generation of an index.
llvm.arc.annotation.provenancesource: This metadata is used to annotate
instructions which act as provenance sources, i.e. ones that introduce a
new (from the optimizer's perspective) non-argument pointer to track. This
enables cross-referencing in between provenance sources and the state changes
that occur to them.
This is still a work in progress. Additionally I plan on committing
later today additions to the annotations that annotate at the top/bottom
of basic blocks the state of the various pointers being tracked.
*NOTE* The metadata support is conditionally compiled into libObjCARCOpts only
when we are producing a debug build of llvm/clang and even so are
disabled by default. To enable the annotation metadata, pass in
-enable-objc-arc-annotations to opt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177951
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Michael Gottesman [Tue, 26 Mar 2013 00:34:27 +0000 (00:34 +0000)]
Added documentation to LangRef for the intrinsic llvm.ptr.annotation.* which for some reason was never written.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177950
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Michael Liao [Mon, 25 Mar 2013 23:50:10 +0000 (23:50 +0000)]
Revise alignment checking/calculation on 256-bit unaligned memory access
- It's still considered aligned when the specified alignment is larger
than the natural alignment;
- The new alignment for the high 128-bit vector should be min(16,
alignment) as the pointer is advanced by 16, a power-of-2 offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177947
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Michael Liao [Mon, 25 Mar 2013 23:47:35 +0000 (23:47 +0000)]
Enhance folding of (extract_subvec (insert_subvec V1, V2, IIdx), EIdx)
- Handle the case where the result of 'insert_subvect' is bitcasted
before 'extract_subvec'. This removes the redundant insertf128/extractf128
pair on unaligned 256-bit vector load/store on vectors of non 64-bit integer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177945
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Jakob Stoklund Olesen [Mon, 25 Mar 2013 23:43:23 +0000 (23:43 +0000)]
Add an -mcpu option to a test that is apparently scheduler-sensitive.
This should fix the clang-atom-d2700-ubuntu-rel buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177943
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Jakob Stoklund Olesen [Mon, 25 Mar 2013 23:37:17 +0000 (23:37 +0000)]
Add a scheduling model for Intel Sandy Bridge microarchitecture.
The model isn't hooked up by this patch because the instruction set
isn't fully annotated yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177942
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Douglas Gregor [Mon, 25 Mar 2013 23:14:19 +0000 (23:14 +0000)]
Introduce a tiny CMake project to gather Subversion revision information and place it into a header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177938
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Jakob Stoklund Olesen [Mon, 25 Mar 2013 23:12:41 +0000 (23:12 +0000)]
Remove IIC_DEFAULT from X86Schedule.td
All the instructions tagged with IIC_DEFAULT had nothing in common, and
we already have a NoItineraries class to represent untagged
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177937
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Jakob Stoklund Olesen [Mon, 25 Mar 2013 23:07:35 +0000 (23:07 +0000)]
Annotate X86InstrCompiler.td with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177936
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Jakob Stoklund Olesen [Mon, 25 Mar 2013 23:07:32 +0000 (23:07 +0000)]
Annotate shifts and rotates with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177935
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Shuxin Yang [Mon, 25 Mar 2013 22:52:29 +0000 (22:52 +0000)]
Disable some unsafe-fp-math DAG-combine transformation after legalization.
For instance, following transformation will be disabled:
x + x + x => 3.0f * x;
The problem of these transformations is that it introduces a FP constant, which
following Instruction-Selection pass cannot handle.
Reviewed by Nadav, thanks a lot!
rdar://
13445387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177933
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John McCall [Mon, 25 Mar 2013 22:09:52 +0000 (22:09 +0000)]
Add an optimizer-side test case for ARC bug <rdar://
13195034>, fixed
in the frontend with @clang.arc.use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177928
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Eric Christopher [Mon, 25 Mar 2013 21:26:36 +0000 (21:26 +0000)]
Couple more sets of tidying.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177920
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Jyotsna Verma [Mon, 25 Mar 2013 21:15:11 +0000 (21:15 +0000)]
Disable profiling tests for Hexagon since it doesn't support JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177917
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NAKAMURA Takumi [Mon, 25 Mar 2013 21:07:53 +0000 (21:07 +0000)]
llvm/test/CodeGen/X86/atomic{32|64}.ll: Unmark them out of XFAIL:win32.
I know it is incorrect and they'd fail with +Asserts for win32 targets, though.
I'll try to fix them tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177914
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Jyotsna Verma [Mon, 25 Mar 2013 21:04:16 +0000 (21:04 +0000)]
XFAIL some of the generic CodeGen tests for Hexagon.
test/CodeGen/Generic/2008-02-20-MatchingMem.ll: Test contains inline assembly not supported by Hexagon.
Following tests are XFAILed due to multiple return values which Hexagon doesn't support.
test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll
test/CodeGen/Generic/select-cc.ll
test/CodeGen/Generic/vector.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177912
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NAKAMURA Takumi [Mon, 25 Mar 2013 20:55:49 +0000 (20:55 +0000)]
X86DisassemblerDecoder.c: Make this C89-compliant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177910
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NAKAMURA Takumi [Mon, 25 Mar 2013 20:55:43 +0000 (20:55 +0000)]
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177909
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Shuxin Yang [Mon, 25 Mar 2013 20:43:41 +0000 (20:43 +0000)]
Fix a bug in fast-math fadd/fsub simplification.
The problem is that the code mistakenly took for granted that following constructor
is able to create an APFloat from a *SIGNED* integer:
APFloat::APFloat(const fltSemantics &ourSemantics, integerPart value)
rdar://
13486998
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177906
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Shankar Easwaran [Mon, 25 Mar 2013 20:26:47 +0000 (20:26 +0000)]
[ELF] dont compute symbolname size in every loop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177903
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Jyotsna Verma [Mon, 25 Mar 2013 20:20:34 +0000 (20:20 +0000)]
XFAIL DebugInfo tests for Hexagon.
Hexagon does not support -filetype=obj(direct object generation) flag. Therefore,
the following tests are being XFAILed:
test/DebugInfo/dwarf-public-names.ll
test/DebugInfo/member-pointers.ll
test/DebugInfo/two-cus-from-same-file.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177901
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