new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26458 91177308-0d34-0410-b5e6-96231b3b80d8

Remove extra comma from enum list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26457 91177308-0d34-0410-b5e6-96231b3b80d8

Remove comma from enum list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26456 91177308-0d34-0410-b5e6-96231b3b80d8

Switch back to using actual dwarf tags.  Simplifies code without loss to other
debug forms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26455 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a typo evan noticed

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26454 91177308-0d34-0410-b5e6-96231b3b80d8

Use context and not compile unit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26453 91177308-0d34-0410-b5e6-96231b3b80d8

I guess I can handle large type sizes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26452 91177308-0d34-0410-b5e6-96231b3b80d8

Basic array support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26451 91177308-0d34-0410-b5e6-96231b3b80d8

Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26450 91177308-0d34-0410-b5e6-96231b3b80d8

load (x|y)  -> load (x+y)  iff x and y have no common bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26449 91177308-0d34-0410-b5e6-96231b3b80d8

add a note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26448 91177308-0d34-0410-b5e6-96231b3b80d8

Compile this:

void foo(float a, int *b) { *b = a; }

to this:

_foo:
        fctiwz f0, f1
        stfiwx f0, 0, r4
        blr

instead of this:

_foo:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        stw r2, 0(r4)
        blr

This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26447 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase.  These functions shouldn't touch the stack if stfiwx use
is enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26446 91177308-0d34-0410-b5e6-96231b3b80d8

Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26445 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase.  There should be no accesses to the stack for these functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26444 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for target-specific dag combines

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26443 91177308-0d34-0410-b5e6-96231b3b80d8

Add interfaces for targets to provide target-specific dag combiner optimizations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26442 91177308-0d34-0410-b5e6-96231b3b80d8

Add a new AddToWorkList method, start using it

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26441 91177308-0d34-0410-b5e6-96231b3b80d8

Pull shifts by a constant through multiplies (a form of reassociation),
implementing Regression/CodeGen/X86/mul-shift-reassoc.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26440 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26439 91177308-0d34-0410-b5e6-96231b3b80d8

Vector op lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26438 91177308-0d34-0410-b5e6-96231b3b80d8

New vector type v2f32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26437 91177308-0d34-0410-b5e6-96231b3b80d8

Vector ops lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26436 91177308-0d34-0410-b5e6-96231b3b80d8

New type v2f32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26435 91177308-0d34-0410-b5e6-96231b3b80d8

Missing a cast previously.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26434 91177308-0d34-0410-b5e6-96231b3b80d8

- Added v2f32, not used by any target currently. Only for testing purpose.
- Minor bug fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26433 91177308-0d34-0410-b5e6-96231b3b80d8

- Added VConstant as an abstract version of ConstantVec.
- All abstrct vector nodes must have # of elements and element type as their
first two operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26432 91177308-0d34-0410-b5e6-96231b3b80d8

Add a test case for left shift by 1. We should not be using lea for this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26431 91177308-0d34-0410-b5e6-96231b3b80d8

Another entry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26430 91177308-0d34-0410-b5e6-96231b3b80d8

Don't match x << 1 to LEAL. It's better to emit x + x.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26429 91177308-0d34-0410-b5e6-96231b3b80d8

Add const, volatile, restrict support.
Add array of debug descriptor support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26428 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a regression in a patch from a couple of days ago.  This fixes
Transforms/InstCombine/2006-02-28-Crash.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26427 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26426 91177308-0d34-0410-b5e6-96231b3b80d8

8 spaces -> tab.  Reported by Wink Saville

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26425 91177308-0d34-0410-b5e6-96231b3b80d8

evan's recent x86 isel improvements have fixed this, though not in the way
originally envisioned :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26422 91177308-0d34-0410-b5e6-96231b3b80d8

Add a subtarget feature for the stfiwx instruction.  I know the G5 has it,
but I don't know what other PPC impls do.  If someone could update the proc
table, I would appreciate it :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26421 91177308-0d34-0410-b5e6-96231b3b80d8

new testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26420 91177308-0d34-0410-b5e6-96231b3b80d8

Compile:
unsigned foo4(unsigned short *P) { return *P & 255; }
unsigned foo5(short *P) { return *P & 255; }

to:

_foo4:
        lbz r3,1(r3)
        blr
_foo5:
        lbz r3,1(r3)
        blr

not:

_foo4:
        lhz r2, 0(r3)
        rlwinm r3, r2, 0, 24, 31
        blr
_foo5:
        lhz r2, 0(r3)
        rlwinm r3, r2, 0, 24, 31
        blr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26419 91177308-0d34-0410-b5e6-96231b3b80d8

remove implemented item

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26418 91177308-0d34-0410-b5e6-96231b3b80d8

Fold "and (LOAD P), 255" -> zextload.  This allows us to compile:

unsigned foo3(unsigned *P) { return *P & 255; }
as:
_foo3:
        lbz r3, 3(r3)
        blr

instead of:

_foo3:
        lwz r2, 0(r3)
        rlwinm r3, r2, 0, 24, 31
        blr

and:

unsigned short foo2(float a) { return a; }

as:
_foo2:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lhz r3, -2(r1)
        blr

instead of:

_foo2:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        rlwinm r3, r2, 0, 16, 31
        blr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26417 91177308-0d34-0410-b5e6-96231b3b80d8

fold (sra (sra x, c1), c2) -> (sra x, c1+c2)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26416 91177308-0d34-0410-b5e6-96231b3b80d8

Implement rem.ll:test[7-9] and PR712

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26415 91177308-0d34-0410-b5e6-96231b3b80d8

new testcases for PR712

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26414 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify some code now that the RHS of a rem can't be 0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26413 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26412 91177308-0d34-0410-b5e6-96231b3b80d8

Rearrange some code, fold "rem X, 0", implementing rem.ll:test6

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26411 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for output memory constraints.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26410 91177308-0d34-0410-b5e6-96231b3b80d8

Qualify dwarf namespace inside llvm namespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26409 91177308-0d34-0410-b5e6-96231b3b80d8

readme updates

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26405 91177308-0d34-0410-b5e6-96231b3b80d8

Partial enabling of functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26404 91177308-0d34-0410-b5e6-96231b3b80d8

Don't print constant initializers, they may span lines now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26403 91177308-0d34-0410-b5e6-96231b3b80d8

Supporting multiple compile units.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26402 91177308-0d34-0410-b5e6-96231b3b80d8

Re-orging file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26401 91177308-0d34-0410-b5e6-96231b3b80d8

Pretty print large struct constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26400 91177308-0d34-0410-b5e6-96231b3b80d8

Removed dependency on how operands are printed (want multi-line.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26399 91177308-0d34-0410-b5e6-96231b3b80d8

Use -emit-llvm -S to get .ll file output from llvm-gcc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26397 91177308-0d34-0410-b5e6-96231b3b80d8

Merge two almost-identical pieces of code.

Make this code more powerful by using ComputeMaskedBits instead of looking
for an AND operand.  This lets us fold this:

int %test23(int %a) {
        %tmp.1 = and int %a, 1
        %tmp.2 = seteq int %tmp.1, 0
        %tmp.3 = cast bool %tmp.2 to int  ;; xor tmp1, 1
        ret int %tmp.3
}

into: xor (and a, 1), 1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26396 91177308-0d34-0410-b5e6-96231b3b80d8

new testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26395 91177308-0d34-0410-b5e6-96231b3b80d8

Fold (A^B) == A  ->  B == 0
and  (A-B) == A  ->  B == 0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26394 91177308-0d34-0410-b5e6-96231b3b80d8

New testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26393 91177308-0d34-0410-b5e6-96231b3b80d8

Implement bit propagation through sub nodes, this (re)implements
PowerPC/div-2.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26392 91177308-0d34-0410-b5e6-96231b3b80d8

Reenable this

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26391 91177308-0d34-0410-b5e6-96231b3b80d8

remove some completed notes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26390 91177308-0d34-0410-b5e6-96231b3b80d8

Check RHS simplification before LHS simplification to avoid infinitely looping
on PowerPC/small-arguments.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26389 91177308-0d34-0410-b5e6-96231b3b80d8

Just like we use the RHS of an AND to simplify the LHS, use the LHS to
simplify the RHS.  This allows for the elimination of many thousands of
ands from multisource, and compiles CodeGen/PowerPC/and-elim.ll:test2
into this:

_test2:
        srwi r2, r3, 1
        xori r3, r2, 40961
        blr

instead of this:

_test2:
        rlwinm r2, r3, 31, 17, 31
        xori r2, r2, 40961
        rlwinm r3, r2, 0, 16, 31
        blr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26388 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26387 91177308-0d34-0410-b5e6-96231b3b80d8

Add a bunch of missed cases.  Perhaps the most significant of which is that
assertzext produces zero bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26386 91177308-0d34-0410-b5e6-96231b3b80d8

Fold (X|C1)^C2 -> X^(C1|C2) when possible.  This implements
InstCombine/or.ll:test23.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26385 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26384 91177308-0d34-0410-b5e6-96231b3b80d8

Reverting. Didn't realize some developers were embedding constants in their
target assembler code gen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26383 91177308-0d34-0410-b5e6-96231b3b80d8

ConstantPoolIndex is now the displacement portion of the address (rather
than base).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26382 91177308-0d34-0410-b5e6-96231b3b80d8

Print ConstantPoolSDNode offset field.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26381 91177308-0d34-0410-b5e6-96231b3b80d8

Fixed ConstantPoolIndex operand asm print bug. This fixed 2005-07-17-INT-To-FP
and 2005-05-12-Int64ToFP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26380 91177308-0d34-0410-b5e6-96231b3b80d8

Format large struct constants for readability.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26379 91177308-0d34-0410-b5e6-96231b3b80d8

New test case: use lea for imul by some constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26378 91177308-0d34-0410-b5e6-96231b3b80d8

lea.ll is XFAIL until we implement convertToThreeAddress.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26377 91177308-0d34-0410-b5e6-96231b3b80d8

* Cleaned up addressing mode matching code.
* Cleaned up and tweaked LEA cost analysis code. Removed some hacks.
* Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and
  they need to be matched before LEA.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26376 91177308-0d34-0410-b5e6-96231b3b80d8

Updates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26375 91177308-0d34-0410-b5e6-96231b3b80d8

* Allow mul, shl nodes to be codegen'd as LEA (if appropriate).
* Add patterns to handle GlobalAddress, ConstantPool, etc.
  MOV32ri to materialize these nodes in registers.
  ADD32ri to handle %reg + GA, etc.
  MOV32mi to handle store GA, etc. to memory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26374 91177308-0d34-0410-b5e6-96231b3b80d8

ConstantPoolIndex is now the displacement field of addressing mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26373 91177308-0d34-0410-b5e6-96231b3b80d8

Added a common about the need for X86ISD::Wrapper.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26372 91177308-0d34-0410-b5e6-96231b3b80d8

Added an offset field to ConstantPoolSDNode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26371 91177308-0d34-0410-b5e6-96231b3b80d8

this fails, mark it as such

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26370 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a bug that Evan exposed with some changes he's making, and that was
exposed with a fastcc problem (breaking pcompress2 on x86 with -enable-x86-fastcc).

When reloading a reused reg, make sure to invalidate the reloaded reg, and
check to see if there are any other pending uses of the same register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26369 91177308-0d34-0410-b5e6-96231b3b80d8

Remove debugging printout :)

Add a minor compile time win, no codegen change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26368 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor some code from being inline to being out in a new class with methods.
This gets rid of two gotos, which is always nice, and also adds some comments.

No functionality change, this is just a refactor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26367 91177308-0d34-0410-b5e6-96231b3b80d8

Fix an obvious bug exposed when we are doing
ADD X, 4
==>
MOV32ri $X+4, ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26366 91177308-0d34-0410-b5e6-96231b3b80d8

Add memory printing support for PPC.  Input memory operands now work with
inline asms! :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26365 91177308-0d34-0410-b5e6-96231b3b80d8

Use the PrintAsmMemoryOperand to print addressing modes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26364 91177308-0d34-0410-b5e6-96231b3b80d8

Add a PrintAsmMemoryOperand method for printing addresses

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26363 91177308-0d34-0410-b5e6-96231b3b80d8

Pass all the flags to the asm printer, not just the # operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26362 91177308-0d34-0410-b5e6-96231b3b80d8

rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope.

Add support for addressing modes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26361 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor operand adding out to a new AddOperand method

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26358 91177308-0d34-0410-b5e6-96231b3b80d8

add a method

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26357 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a problem that Nate noticed that boils down to an over conservative check
in the code that does "select C, (X+Y), (X-Y) --> (X+(select C, Y, (-Y)))".
We now compile this loop:

LBB1_1: ; no_exit
        add r6, r2, r3
        subf r3, r2, r3
        cmpwi cr0, r2, 0
        addi r7, r5, 4
        lwz r2, 0(r5)
        addi r4, r4, 1
        blt cr0, LBB1_4 ; no_exit
LBB1_3: ; no_exit
        mr r3, r6
LBB1_4: ; no_exit
        cmpwi cr0, r4, 16
        mr r5, r7
        bne cr0, LBB1_1 ; no_exit

into this instead:

LBB1_1: ; no_exit
        srawi r6, r2, 31
        add r2, r2, r6
        xor r6, r2, r6
        addi r7, r5, 4
        lwz r2, 0(r5)
        addi r4, r4, 1
        add r3, r3, r6
        cmpwi cr0, r4, 16
        mr r5, r7
        bne cr0, LBB1_1 ; no_exit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26356 91177308-0d34-0410-b5e6-96231b3b80d8

Add pointer and reference types.  Added short-term code to ignore NULL types
(to allow llvm-gcc4 to build.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26355 91177308-0d34-0410-b5e6-96231b3b80d8

Get VC++ building again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26351 91177308-0d34-0410-b5e6-96231b3b80d8

Implement (most of) selection of inline asm memory operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26350 91177308-0d34-0410-b5e6-96231b3b80d8

Select inline asm memory operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26349 91177308-0d34-0410-b5e6-96231b3b80d8

Implement selection of inline asm memory operands

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26348 91177308-0d34-0410-b5e6-96231b3b80d8