Revert "iommu: rk-iovmm: change compatible name to a unified name"

This reverts commit 3a1bdfa3a4bd6e3bb0a1328ef50a4d3278560222.

This patch broken old rkfb driver, so revert it.

Change-Id: I7ccd93d8ff2086cca9c1b31932278435cbffc59f

arm64: rockchip: remove unused files

Change-Id: Ied0e45214df40f8b278114ddcb5cad4d4ce9dc81
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM64: dts: rk3366: support arm64 cpuidle-dt

Change-Id: Ia5a0bf96609092c22f3bdb327cdfde6f505163c6
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>

ARM64: dts: rockchip: configure clock frequency for rk3399 tsadc

As the rk3399 SoCs requires initial configuration for tsadc clock
frequency. The tsadc can be specified in a device tree node through
assigned-clocks.

The tsadc clock needs 500KHz~800KHz frequency to work on rk3399 SoCs.
We can add the assigned-clock to prevent the firmware
or loader has *not* set the division frequency from the source clock.

Change-Id: Ieb4cd5aad7d299baab20a9fb9d39211fe00896ff
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rockchip: add the grf found on rk3399 tsadc

This patch adds the rockchip,grf to match the driver.

Change-Id: If477634fd38f1ebc539ade6c620a63d0cfee9111
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

thermal: rockchip: handle the power sequence for rk3399 SoCs

This adds the grf property to handle the tsadc power sequence on
rk3399 SoCs.

The rk3399 tsadc can work with this patch on now.

while true; do grep "" /sys/class/thermal/thermal_zone[0-1]/temp;sleep .5; done
/sys/class/thermal/thermal_zone0/temp:40555
/sys/class/thermal/thermal_zone1/temp:41111
/sys/class/thermal/thermal_zone0/temp:40555
/sys/class/thermal/thermal_zone1/temp:41111
/sys/class/thermal/thermal_zone0/temp:40555
/sys/class/thermal/thermal_zone1/temp:41666
/sys/class/thermal/thermal_zone0/temp:40555
/sys/class/thermal/thermal_zone1/temp:41111
/sys/class/thermal/thermal_zone0/temp:40555
/sys/class/thermal/thermal_zone1/temp:41111
/sys/class/thermal/thermal_zone0/temp:40555

Change-Id: I0155826bddf0017ea4985920268b333a20278bbe
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

UPSTREAM: mmc: core: fix __mmc_switch timeout caused by preempt

there is a time window between __mmc_send_status() and time_afer(),
on some eMMC chip, the timeout_ms is only 10ms, if this thread was
scheduled out during this period, then, even card has already changes
to transfer state by the result of CMD13, this part of code also treat
it to timeout error.
So, need calculate timeout first, then call __mmc_send_status(), if
already timeout and card still in programing state, then treat it to
the real timeout error.

Change-Id: I7499d3d41711ea5abe6baec780d2988dc60dfc5b
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 3bbb0deea6d5c6d5ed38ae927a5bf9b0cd7c8639)

UPSTREAM: mmc: sdhci: Fix override of timeout clk wrt max_busy_timeout

Normally the timeout clock frequency is read from the capabilities
register.  It is also possible to set the value prior to calling
sdhci_add_host() in which case that value will override the
capabilities register value.  However that was being done after
calculating max_busy_timeout so that max_busy_timeout was being
calculated using the wrong value of timeout_clk.

Fix that by moving the override before max_busy_timeout is
calculated.

The result is that the max_busy_timeout and max_discard
increase for BSW devices so that, for example, the time for
mkfs.ext4 on a 64GB eMMC drops from about 1 minute 40 seconds
to about 20 seconds.

Note, in the future, the capabilities setting will be tidied up
and this override won't be used anymore.  However this fix is
needed for stable.

Change-Id: Ifd327b7c534a346f3537432d7bce7d8f1aebef3f
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: stable@vger.kernel.org # v3.18+
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 995136247915c5cee633d55ba23f6eebf67aa567)

thermal: rockchip: update the tsadc table for rk3399

This patch fixes the incorrect conversion table.
The Code to Temperature mapping is updated based on sillcon results.

Change-Id: If8ae3f5fb59786a8db8bf79276ecea44ab92ffc9
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rk3399-monkey: set usbdrd_dwc3_0 in peripheral mode

Set dwc3_0 in peripheral only mode until Type-C function is
ready, and then we can set dwc3_0 in drd mode.

Change-Id: I0ccb92db97244d7a34dd17c58757fc5aa1b11dac
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

ARM64: dts: rk3399: add pmu node

Change-Id: I9128738f72518bcb04f7e5d3fdb6638f476df667
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

Revert "ARM64: dts: rk3399: add pmu node"

This reverts commit 0b622df3499e3dcaebd619fa966b13588131b83d.

arm pmu driver do not support PPI in two
cluster well. So drop it.

Change-Id: I69f43ad1703589805c7e86749badda8bf802d51a

iommu/rockchip: add map_sg callback for rk_iommu_ops

Change-Id: I7a677ba0c06c4031661681a26333b1e9a2aafd26
Signed-off-by: Simon <xxm@rock-chips.com>

iommu/rockchip: fix devm_request_irq and devm_free_irq parameter

When rk_iommu_attach_device or rk_iommu_detach_device be called, the second
parameter "dev" represent the device who own the iommu, so it is not resonable
using "dev" for devm_request_irq's first parameter. To avoid potential error,
we must use iommu device itself "iommu->dev" instead, the same as devm_free_irq.

Change-Id: Id9f4097d6f1b916308475854dcf75ce86d9494fc
Signed-off-by: Simon <xxm@rock-chips.com>

ARM64: dts: rockchip: rk3399: add usb2.0 phy node

Change-Id: Ie972043ecc62f9cbca5083e3047268f91be73b2c
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

phy: rockchip-usb: support usb2.0 phy for rk3399 SoC

1. Add a new compatible for rk3399;
2. Support gpio operation for vbus-drv.

Change-Id: I2eb1ac377db0bcb907d009c56fba22f1951c128e
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

Documentation: bindings: update one property for Rockchip usb-phy

vbus_drv-gpio property updated

Change-Id: I528b10f1c41cbadff2b4f0d1b1b63f7d2cb51a97
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

drivers: firmware: psci: notify regulators on system-suspend

On some systems regulators need to do special actions on suspend/resume.
These get set from the generic regulator_suspend_prepare and
regulator_suspend_finish functions so these should be called from the
psci suspend ops as well.

Change-Id: I6fbf7b39ceae936ed5bd9df6719ccd3cd360840f
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Shengfei xu <xsf@rock-chips.com>

ARM64: dts: rk3399: add some properties to config dwc3

RK3399 dwc3 has some hardware properties, which is platform
dependent, including the following properties:
1. Set PHYIF to 1 to use 16-bit UTMI+ interface;
2. Clear ENBLSLPM to 0 to disable sleep and l1 suspend;
3. Clear U2_FREECLK_EXITSTS to 0;
4. Clear DEV_FORCE_20_CLK_FOR_30_CLK to 0;
5. Clear DELAYP1TRANS to 0;

Change-Id: I85de326e3c2177c66966f1239bcab838df01492d
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

usb: dwc3: add dis_del_phy_power_chg_quirk

Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether delay PHY power change from P0
to P1/P2/P3 when link state changing from U0 to U1/U2/U3
respectively.

Change-Id: I23e33f8b13001d6f86d6473ad43a261d9bda8f79
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

usb: dwc3: add DWC3_GUCTL1 reg

Change-Id: I67dfabf539b85281904b9c4dfbc764bacecb7ac3
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

clk: rockchip: rk3399: add peri hp/lp0/lp1 noc clocks into critical

Change-Id: Id136016c27b17944fc33a848fb137c3452dd6289
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: rk3399: Keep critical independently for the PMUCRU and CRU

Fix add critical clock for PMUCRU too late in the rk3399_clk_init. It
will be crash if there is one clock want to disable its parent which is
the PPLL.

Change-Id: I3fa236ab78571c8c8ec5d423228d00dbb02f24e6
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: rt5640: Correct the digital interface data select

this patch corrects the interface adc/dac control register definition
according to datasheet.

Change-Id: I0777577d365140b642141596112b662d3a80538b
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
(cherry picked from git.kernel.org broonie/sound.git for-next
 commit 653aa4645244042826f105aab1be3d01b3d493ca)

ARM64: dts: rockchip: rk3399: set each cpu's opp-microvolt to 900000uV

In order to lower the temperature, lower the voltage.

Change-Id: Iae2d103c88ab5b72c3d003c1f84f74e1694c7e1e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rk3399: fix PPLL is redefined and ID shouldn't be 0

PPLL is 8 and redefined by SCLK_I2C4_PMU, and clock IDs shouldn't be 0.

Change-Id: I50f89487034c1f1ef41d257de00b7f3ec53f7f4c
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

usb: dwc3: make usb2 phy interface configurable in DT

Add snps,phyif_utmi_16_bits devicetree property. USB2 phy
interface is hardware property, and it's platform dependent,
so we need to configure it in devicetree to set the core to
support a UTMI+ PHY with an 8- or 16-bit interface.

And according to dwc3 databook, the GUSB2PHYCFG.USBTRDTIM
must set to the required values for the usb2 phy interface.

Change-Id: If1c636edc6be3c9a79b4b0b89737a925d8dd3abe
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

usb: dwc3: add dis_u2_freeclk_exists_quirk

Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.

Change-Id: I84ea6eeccb9fc2ea6d13ef586f1166d5fa132606
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

Merge branch 'linux-linaro-lsk-v4.4-android' of git://git.linaro.org/kernel/linux-linaro-stable.git

* linux-linaro-lsk-v4.4-android: (477 commits)
  arm64: vdso: Mark vDSO code as read-only
  ARM/vdso: Mark the vDSO code read-only after init
  x86/vdso: Mark the vDSO code read-only after init
  lkdtm: Verify that '__ro_after_init' works correctly
  arch: Introduce post-init read-only memory
  x86/mm: Always enable CONFIG_DEBUG_RODATA and remove the Kconfig option
  mm/init: Add 'rodata=off' boot cmdline parameter to disable read-only kernel mappings
  asm-generic: Consolidate mark_rodata_ro()
  Linux 4.4.6
  ld-version: Fix awk regex compile failure
  target: Drop incorrect ABORT_TASK put for completed commands
  block: don't optimize for non-cloned bio in bio_get_last_bvec()
  MIPS: smp.c: Fix uninitialised temp_foreign_map
  MIPS: Fix build error when SMP is used without GIC
  ovl: fix getcwd() failure after unsuccessful rmdir
  ovl: copy new uid/gid into overlayfs runtime inode
  userfaultfd: don't block on the last VM updates at exit time
  powerpc/powernv: Fix OPAL_CONSOLE_FLUSH prototype and usages
  powerpc/powernv: Add a kmsg_dumper that flushes console output on panic
  powerpc: Fix dedotify for binutils >= 2.26
  ...

ARM64: dts: rockchip: rk3399: add cpul/cpub assingment clk rate

set clk_cpul:816M clk_cpub:1008M when clk tree init

Change-Id: I8f493ce8479fc670aa05d651db5be354d6870c98
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: dts: rk3399-tb: limit emmc freq to 50MHz

Change-Id: Ib9b7c7d7574077e9c265e292b61e6eb0a4511bd8
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

clk: rockchip: rk3399: fix the incorrect name of uart1~3

Change-Id: I32764eb21d31e4527dc90239cb3d4a450f2def6d
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: dts: rk3366: update gpu's opp table

Change-Id: I1c3ccc7b896b4fe95f834a957a4ebe2aef482806
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>

ARM64: defconfig: add the basic config for 3399 ChromeOS

With this defconfig which inherits from rockchip_defconfig,
ChromeOS boots up to command line.

Change-Id: I646fea9b26d9c235da16d0d2b559290ee5029a12
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>

ARM64: dts: rk3366-tb: add regulator-ramp-delay of vdd_arm

Change-Id: If4eb8f964592d2f6c0e418659b12f672dc9abb94
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

Documentation: bindings: add compatible entry for Rockchip USB2.0 PHY

1. Compatible "rockchip,rk3399-usb-phy" support to RK3399;
2. Add host_drv_gpio optional property for usb2.0 vbus control.

Change-Id: Idfc6898ca2c519c46dae66d396f501b38e8d73bd
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

ARM64: rockchip_defconfig: enable dwc3 and xhci drivers

Change-Id: I3c3dae4bf999cb3e7141d88bdfa60e50ab46e2fd
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

usb: dwc3: rockchip: Add device tree binding

Rockchip USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.

Change-Id: I116b66c3b417cfecc968414db9912813a0ef2c5d
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

usb: dwc3: of-simple: add compatible for rk3399

Change-Id: I0a74fcd97c5be7887b4d14bb708a58a10f70e71c
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

ARM64: dts: rk3399: enable usbdrd3_0 and usbdrd3_1

Change-Id: I2321c1b0651a1a0ad1352e1409d8c9cef1428a67
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

ARM64: dts: rk3399: add usbdrd3_0 and usbdrd3_1 nodes

Change-Id: I4b940966e3b054e072de90f6943ab20006848495
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

ARM64: dts: rk3366: update cpu's opp table

Change-Id: Id0d722d90672f78941073a4ad7e45615893b1e90
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>

ARM64: rockchip_defconfig: enable rk808 regulator

set CONFIG_REGULATOR_RK808=y

Change-Id: I9cfc60fc82a4cb7dc4056bd13f3d678d6a0f7faf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: fix pmu cru register name error

Change-Id: I4ab865326657dceaf8759b37d02d80de9e3071c0
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: add some clock IDs for reference

Change-Id: I8ce291b7145a56aea9d8f5b5742506a581f26912
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: fix PLL table and add pclk DFLAG for rk3399

Change-Id: Id89c7099b24fdcff967528a3741af2e84fa1a754
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

video: rockchip: fb: the default state of FBDC is closed

Change-Id: I6c1a4e47daa00089bfeb7b7316dbe6bac4409a5c
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: lcdc: 3368: update for FBDC

FBDC state |= win[i]->area[0]->fbdc_en;

Change-Id: I2ddfdea66061ad67b876369c130b8cfa6e3bda55
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: fb: init saved_list

Change-Id: I2da026cfcef25c6ae44356d0c3869e482cb97e11
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: lcdc: 3366: add more format for gather

Change-Id: I5d20a52f1bd680af4083672b0607fa95332d7146
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

iommu: rk-iovmm: change compatible name to a unified name

To make android platform iommu work well, we need a unified compatible
name to match the new iommu definition in dtsi

Change-Id: Ied581653e1261fd0a21577f4e9ce3b915af135cd
Signed-off-by: Simon <xxm@rock-chips.com>

video: rockchip: mipi: remove the function of get dsi host id

The rk3288, rk3368 and rk3366 have the same physical dsi id 0x3133302A,
so do not need to get dsi host id.

Change-Id: I0de1e9b7c0250b37ffdc2c39155c5f16afb48956
Signed-off-by: xubilv <xbl@rock-chips.com>

ARM64: dts: rk3366: mipi: modify compatible

Change-Id: I05bb54c00019310fb57a0bc3fb0bd365aaed10dd
Signed-off-by: xubilv <xbl@rock-chips.com>

video: rockchip: rk3366: add mipi support

Change-Id: Ibf70a23ba2fe02cff5e66932bc802264768d05cf
Signed-off-by: xubilv <xbl@rock-chips.com>

ARM64: dts: rk3366: assign rates for aclk_bus and aclk_peri

Assign rates for aclk_bus and aclk_peri according to our original design.

Change-Id: Iab4961d485421151be5dbdacf6929800150ab342
Signed-off-by: Feng Xiao <xf@rock-chips.com>

clk: rockchip: rk3366: modify cpuclk_rate_table

add 1296MHz, 1104MHz and 216MHz to the cpuclk_rate_table list

Change-Id: I1ea7ee432b7c69b89cb3c11a74e67d9d6af1a5dd
Signed-off-by: Feng Xiao <xf@rock-chips.com>

clk: rockchip: fix big/LITTLE cores alternate parent failed

Change-Id: Iebe33903ad5a06f276454ffe12654866bd9567eb
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: fix pclk_pmu_src clock for rk3399

Change-Id: I1e9c04366af370664d864d2877fa87a385da44a6
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: fix uart4_pmu and mipidphy_ref clock for rk3399

Change-Id: I307e4480cb4eb52c447b2db47643b478d4292500
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

video: rockchip: hdmi: v2: modify phy reg to pass CTS signal quality test

Change-Id: Ife9f9808dcc29320f628bf91005e16f22bbe3c50
Signed-off-by: xuhuicong <xhc@rock-chips.com>

ARM64: dts: rk3399-tb: enable emmc_phy and sdhci

Change-Id: I0693b5e3f194b3fb0aed73784d0242ebf89d4ebe
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM64: dts: rk3366: assigned parents for clk_32k

Change-Id: I1742823658aa46226e3112969d3eabc695921fb5
Signed-off-by: Feng Xiao <xf@rock-chips.com>

ARM64: dts: rk3366: assigned parents for vop dclks

For sheep board, we have decided to assign vop full for
use with HDMI. And we can also change it in the board
dts in the further.

Change-Id: Id966615c84cef50f0e8d849e3840434ba7f7b7ec
Signed-off-by: Feng Xiao <xf@rock-chips.com>

clk: rockchip: rk3366: leave npll for VOP only

We will need a pll to support all kinds of clock rate requirement
for HDMI which may change the rate at run time.

In order not to affect other clocks, remove the npll from the
parent list of other clocks and only DCLK_VOP(FULL or LITE) can
select npll as parent. Also add the ability for DCLK_VOP to set
the rate of its parent (which is now forced to NPLL).

Change-Id: I1e13ef1c4f1b9728f9c173454d5056780c47a95e
Signed-off-by: Feng Xiao <xf@rock-chips.com>

phy: rockchip-emmc: add init function

We need to init some signal related stuff
to make sure the SI meet the requirement.

Change-Id: I829203fb9cd2e93aa6acaa5288667f600370d781
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

arm64: dts: rockchip: add compatible for rk3399evb board

Coreboot choose dtb by its compatible string.
Add "google,rk3399evb-rev*" accordingly.

Support more versions for rk3399evb in the future.
If we later find we need to introduce differences between versions,
it's easy to change things.

Change-Id: I049b4f113b1694577a1f0be68f6b635ae13653c0
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>

clk: rockchip: fix cci src clocks for rk3399

Change-Id: I9c22a270c64feaf52436117e47fb874000361100
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: add some critical clocks for rk3399

Change-Id: I1a04f11f881764929d9e5801626ce398bc3b193e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: update dt-binding header for rk3399 pmucru IDs

Change-Id: I302dc97a3ec5ef5cd7609ecff929c6fea25f005b
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

Merge branch 'linux-linaro-lsk-v4.4' into linux-linaro-lsk-v4.4-android

Merge branch 'v4.4/topic/ro-vdso' into linux-linaro-lsk-v4.4

arm64: vdso: Mark vDSO code as read-only

commit 88d8a7994e564d209d4b2583496631c2357d386b upstream.

Although the arm64 vDSO is cleanly separated by code/data with the
code being read-only in userspace mappings, the code page is still
writable from the kernel.  There have been exploits (such as
http://itszn.com/blog/?p=21) that take advantage of this on x86 to go
from a bad kernel write to full root.

Prevent this specific exploit on arm64 by putting the vDSO code page
in read-only memory as well.

Before the change:
[    3.138366] vdso: 2 pages (1 code @ ffffffc000a71000, 1 data @ ffffffc000a70000)
---[ Kernel Mapping ]---
0xffffffc000000000-0xffffffc000082000         520K     RW NX SHD AF            UXN MEM/NORMAL
0xffffffc000082000-0xffffffc000200000        1528K     ro x  SHD AF            UXN MEM/NORMAL
0xffffffc000200000-0xffffffc000800000           6M     ro x  SHD AF        BLK UXN MEM/NORMAL
0xffffffc000800000-0xffffffc0009b6000        1752K     ro x  SHD AF            UXN MEM/NORMAL
0xffffffc0009b6000-0xffffffc000c00000        2344K     RW NX SHD AF            UXN MEM/NORMAL
0xffffffc000c00000-0xffffffc008000000         116M     RW NX SHD AF        BLK UXN MEM/NORMAL
0xffffffc00c000000-0xffffffc07f000000        1840M     RW NX SHD AF        BLK UXN MEM/NORMAL
0xffffffc800000000-0xffffffc840000000           1G     RW NX SHD AF        BLK UXN MEM/NORMAL
0xffffffc840000000-0xffffffc87ae00000         942M     RW NX SHD AF        BLK UXN MEM/NORMAL
0xffffffc87ae00000-0xffffffc87ae70000         448K     RW NX SHD AF            UXN MEM/NORMAL
0xffffffc87af80000-0xffffffc87af8a000          40K     RW NX SHD AF            UXN MEM/NORMAL
0xffffffc87af8b000-0xffffffc87b000000         468K     RW NX SHD AF            UXN MEM/NORMAL
0xffffffc87b000000-0xffffffc87fe00000          78M     RW NX SHD AF        BLK UXN MEM/NORMAL
0xffffffc87fe00000-0xffffffc87ff50000        1344K     RW NX SHD AF            UXN MEM/NORMAL
0xffffffc87ff90000-0xffffffc87ffa0000          64K     RW NX SHD AF            UXN MEM/NORMAL
0xffffffc87fff0000-0xffffffc880000000          64K     RW NX SHD AF            UXN MEM/NORMAL

After:
[    3.138368] vdso: 2 pages (1 code @ ffffffc0006de000, 1 data @ ffffffc000a74000)
---[ Kernel Mapping ]---
0xffffffc000000000-0xffffffc000082000         520K     RW NX SHD AF            UXN MEM/NORMAL
0xffffffc000082000-0xffffffc000200000        1528K     ro x  SHD AF            UXN MEM/NORMAL
0xffffffc000200000-0xffffffc000800000           6M     ro x  SHD AF        BLK UXN MEM/NORMAL
0xffffffc000800000-0xffffffc0009b8000        1760K     ro x  SHD AF            UXN MEM/NORMAL
0xffffffc0009b8000-0xffffffc000c00000        2336K     RW NX SHD AF            UXN MEM/NORMAL
0xffffffc000c00000-0xffffffc008000000         116M     RW NX SHD AF        BLK UXN MEM/NORMAL
0xffffffc00c000000-0xffffffc07f000000        1840M     RW NX SHD AF        BLK UXN MEM/NORMAL
0xffffffc800000000-0xffffffc840000000           1G     RW NX SHD AF        BLK UXN MEM/NORMAL
0xffffffc840000000-0xffffffc87ae00000         942M     RW NX SHD AF        BLK UXN MEM/NORMAL
0xffffffc87ae00000-0xffffffc87ae70000         448K     RW NX SHD AF            UXN MEM/NORMAL
0xffffffc87af80000-0xffffffc87af8a000          40K     RW NX SHD AF            UXN MEM/NORMAL
0xffffffc87af8b000-0xffffffc87b000000         468K     RW NX SHD AF            UXN MEM/NORMAL
0xffffffc87b000000-0xffffffc87fe00000          78M     RW NX SHD AF        BLK UXN MEM/NORMAL
0xffffffc87fe00000-0xffffffc87ff50000        1344K     RW NX SHD AF            UXN MEM/NORMAL
0xffffffc87ff90000-0xffffffc87ffa0000          64K     RW NX SHD AF            UXN MEM/NORMAL
0xffffffc87fff0000-0xffffffc880000000          64K     RW NX SHD AF            UXN MEM/NORMAL

Inspired by https://lkml.org/lkml/2016/1/19/494 based on work by the
PaX Team, Brad Spengler, and Kees Cook.

Signed-off-by: David Brown <david.brown@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
[catalin.marinas@arm.com: removed superfluous __PAGE_ALIGNED_DATA]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

ARM64: dts: rk3399: fix incorrect pmucru reference

Change-Id: I4e6743eecf14597cc3391fd4f80ad329ee7b5785
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: fix and add some critical clocks for rk3399

Change-Id: I1db9ab40ba9c25d5054a4011eee1ea14f1207443
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

clk: rockchip: update dt-binding header for rk3399 pmucru clock IDs

Change-Id: Ic19ea01466ab4d90210cedbbb1d0bce21e3800e1
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

iommu/rockchip: fix bool operation error and probe warning

Bool type true is exactly BIT(0), so
bool enable = true;
enable &= BIT(2);
enable will be false, which isn't the result we expected in this case.
Change bool type to u32.

The other fix is checking the res in probe() to skip the irq resource.

Change-Id: I2947c9f1e15cb92f03096d26a44759c107bfacd1
Reported-by: Simon <xxm@rock-chips.com>
Suggested-by: Simon <xxm@rock-chips.com>
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>

ARM64: dts: rk3399-monkey: fix uart2 address error

Change-Id: Id857682e49063fb4d47253385b930acb59327046
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

rockchip: clk: rk3399: fix up clk tree assigned error

add some clk id.

Change-Id: Iffc3fbfa557e5d01f70ab0be2d84a85cff7ac34c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

video: rockchip: hdmi: v2: modify phy clock rate to reduce tdms clock jitter

set hdmi phy clock as 148.5Mhz when dclk rate over this frequency

Change-Id: I416b2b98fe42fafc45491b66252f245aed0f1364
Signed-off-by: xuhuicong <xhc@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: Fix the possible dead lock in bridge disable time

It may caused a dead lock if we flush the hpd work in bridge disable time.

The normal flow would like:
  IN --> DRM IOCTL
        1. Acquire crtc_ww_class_mutex (DRM IOCTL)
  IN --> analogix_dp_bridge
        2. Acquire hpd work lock (Flush hpd work)
        3. HPD work already in idle, no need to run the work function.
  OUT <-- analogix_dp_bridge
  OUT <-- DRM IOCTL

The dead lock flow would like:
  IN --> DRM IOCTL
        1. Acquire crtc_ww_class_mutex (DRM IOCTL)
  IN --> analogix_dp_bridge
        2. Acquire hpd work lock (Flush hpd work)
  IN --> analogix_dp_hotplug
  IN --> drm_helper_hpd_irq_event
        3. Acquire mode_config lock (This lock already have been acquired in previous step 1)
** Dead Lock Now **

It's wrong to flush the hpd work in bridge->disable time, I guess the
original code just want to ensure the delay work must be finish before
encoder disabled.

The flush work in bridge disable time is try to ensure the HPD event
won't be missed before display card disabled, actually we can take a
fast respond way(interrupt thread) to update DRM HPD event to fix the
delay update and possible dead lock.

(am from https://patchwork.kernel.org/patch/8313001/)

Change-Id: Id7b357de0f497ff8c9f259fe31dc28be34f17083
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: add panel prepare/unprepare in suspend/resume time

Turn off the panel power in suspend time would help to reduce
power waste.

(am from https://patchwork.kernel.org/patch/8312971/)

Change-Id: Iac01ac4041a2486e0347ed0377abcc094ab493ea
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: add edid modes parse in get_modes method

Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.

Note: Gustavo Padovan try to remove the controller and phy
power on function in bind time at bellow commit:
drm/exynos: do not start enabling DP at bind() phase

But for now driver need to read edid message in .get_modes()
function, so controller must be inited in bind time, so we
need to add controller init back.

(am from https://patchwork.kernel.org/patch/8312921/)

Change-Id: I32abee21665a7e1470f2898b7fbc925108f9d768
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: move hpd detect to connector detect function

This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().

Note: Gustavo Padovan try to remove the controller and phy
power on function in bind time at bellow commit:
drm/exynos: do not start enabling DP at bind() phase

But for now the connector status don't hardcode to connected,
need to operate dp phy in .detect function, so we need to revert
parts if Gustavo Padovan's changes, add phy poweron
function in bind time.

(am from https://patchwork.kernel.org/patch/8312901/)

Change-Id: I0ed1be541210f85883477f1b2a88bd8d57e390d6
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: try force hpd after plug in lookup failed

Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.

This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.

(am from https://patchwork.kernel.org/patch/8313081/)

Change-Id: If99d29936aafd996c98568d6e184aee6d9c8bc47
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288

There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.

(am from https://patchwork.kernel.org/patch/8312881/)

Change-Id: Id1432af874eb0a6dec819d7b7e735c1040f4bf5c
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: add some rk3288 special registers setting

RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.

(am from https://patchwork.kernel.org/patch/8312861/)

Change-Id: I422216f58a18f2c2fee187b4f19de7b9d0fcd05a
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: dt-bindings: add document for rockchip variant of analogix_dp

Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.

(am from https://patchwork.kernel.org/patch/8312841/)

Change-Id: If7a422554ac09cd3ed40eac8191369df532c58bf
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: rockchip: dp: add rockchip platform dp driver

Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.

(am from https://patchwork.kernel.org/patch/8615371/)

Change-Id: Ibe22447ab881b7421e999479cbdfd529d183f6b4
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver

After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
for Exynos DTS file for dp-controller.

Beside the backward compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.

(am from https://patchwork.kernel.org/patch/8312821/)

Change-Id: I79adafdb4a086d4a357678282cc653a7e3432da9
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: dt-bindings: add document for analogix display port driver

Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt

Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.

(am from https://patchwork.kernel.org/patch/8312811/)

Change-Id: Ia1d47783b735868a4f56231660d8309cf9c75923
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range

Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.

But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.

(am from https://patchwork.kernel.org/patch/8312791/)

Change-Id: Ia7f37daf40fa2d0516d5c44737ad36b5822c6015
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count

link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.

Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}.

(am from https://patchwork.kernel.org/patch/8312771/)

Change-Id: I8cbf7146d70143bb5d30b3fa971e19f034c30e62
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: fix some obvious code style

Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.

(am from https://patchwork.kernel.org/patch/8615381/)

Change-Id: I49198f28156ae5761ba0aa8e8479bbdc963d9b25
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: rename register constants

In the original split we kept the register constants intact to keep the
diff small. Still the constants are Analogix-specific, so rename them now.

(am from https://patchwork.kernel.org/patch/8312781/)

Change-Id: I714d60bc941b7a992dd34d4c0804576bd07ca84d
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: drm: bridge: analogix/dp: split exynos dp driver to bridge directory

Split the dp core driver from exynos directory to bridge directory,
and rename the core driver to analogix_dp_*, rename the platform
code to exynos_dp.

Beside the new analogix_dp driver would export six hooks.
"analogix_dp_bind()" and "analogix_dp_unbind()"
"analogix_dp_suspned()" and "analogix_dp_resume()"
"analogix_dp_detect()" and "analogix_dp_get_modes()"

The bind/unbind symbols is used for analogix platform driver to connect
with analogix_dp core driver. And the detect/get_modes is used for analogix
platform driver to init the connector.

They reason why connector need register in helper driver is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.

(am from https://patchwork.kernel.org/patch/8615401/)

Change-Id: Iad075ae92ba9fa08674fb3d36488f7691909fead
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

UPSTREAM: drm/exynos: removed optional dummy encoder mode_fixup function.

mode_fixup function for encoder drivers became optional with patch
http://patchwork.freedesktop.org/patch/msgid/1455106522-32307-1-git-send-email-palminha@synopsys.com

This patch set nukes all the dummy mode_fixup implementations.

(made on top of Daniel topic/drm-misc branch)

(cherry picked from commit 586236251464a9fcf44757f8639e531d8af628f9)

Change-Id: I58ea3c6042f4ceca0bdf0cbac57175fdb53d05b2
Signed-off-by: Carlos Palminha <palminha@synopsys.com>
[danvet: Squash in 2nd exynos patch.]
Link: http://patchwork.freedesktop.org/patch/msgid/3768b670931572de51fca1102efa18d20dd770ee.1455540137.git.palminha@synopsys.com
Link: http://patchwork.freedesktop.org/patch/msgid/4906a9925eebbe55489b1005c449b426a61c09bd.1455540137.git.palminha@synopsys.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

UPSTREAM: drm/exynos: dp: Fix panel and bridge lookup logic

Commit a9fa852886fd ("drm/exynos: dp: add of_graph dt binding support
for panel") made the Exynos DP DT binding more consistent since the OF
graph could be used to lookup either a panel or a bridge device node.

Before that commit, a panel would be looked up using a phandle and a
bridge using the OF graph which made the DT binding not consistent.

But the patch broke the later case since not finding a panel dev node
would cause the driver's to do a probe deferral instead of attempting
to lookup a bridge device node associated with the remote endpoint.

So instead of returning a -EPROBE_DEFER if a panel is not found, check
if there's a bridge and only do a probe deferral if both aren't found.

(cherry picked from commit 37e110625eeeaba83e8cb763ab7645f0678c6f8e)

Change-Id: If8b66d792447d4e3455f99dc38b04f334b8b65a6
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Michal Suchanek <hramrach@gmail.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

UPSTREAM: drm/exynos: Constify function pointer structs

Moves a bunch of junk to .rodata from .data.

 drivers/gpu/drm/exynos/exynosdrm.ko:
-.text                       125792
+.text                       125788
-.rodata                      10972
+.rodata                      11748
-.data                         6720
+.data                         5944

(cherry picked from commit 800ba2b58182e4b0e8dc826a27362d45499068b1)

Change-Id: I8261dbe53224b581a20102253b162cc3a2563b58
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1450178476-26284-19-git-send-email-boris.brezillon@free-electrons.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

UPSTREAM: drm/exynos: dp: add of_graph dt binding support for panel

This patch adds of_graph dt binding support for panel device
and also keeps the backward compatibility.

i.e.,
The dts file for Exynos5800 based peach pi board
has a panel property so we need to keep the backward compatibility.

Changelog v3:
- bind only one of two nodes outbound - panel or bridge.

Changelog v2:
- return -EINVAL if getting a port node failed.

(cherry picked from commit a9fa852886fd5a7ccec3b7e9eff75f85072f009c)

Change-Id: Ie300bdc95027269f4a6b0d7fef8d6f0ca4017f06
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

UPSTREAM: drm/exynos: add pm_runtime to DP

Let pm_runtime handle the enabling/disabling of the device with
proper refcnt instead of rely on specific flags to track the enabled
state.

Chnagelog v3:
- revive dpms_mode to keep current dpms mode.

Changelog v2:
- no change

(cherry picked from commit 613d3853c2aca6cfd990e8bd0b436833b6c76db6)

Change-Id: Ieac8db078030f9331135ff0bc43a3a41d56d3b62
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>