Benjamin Kramer [Tue, 28 Aug 2012 13:59:23 +0000 (13:59 +0000)]
InstCombine: Defensively avoid undefined shifts by limiting the amount to the bit width.
No test case, undefined shifts get folded early, but can occur when other
transforms generate a constant. Thanks to Duncan for bringing this up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162755
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Tue, 28 Aug 2012 13:08:13 +0000 (13:08 +0000)]
InstCombine: Guard the transform introduced in r162743 against large ints and non-const shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162751
91177308-0d34-0410-b5e6-
96231b3b80d8
Nadav Rotem [Tue, 28 Aug 2012 12:23:22 +0000 (12:23 +0000)]
Make sure that we don't call getZExtValue on values > 64 bits.
Thanks Benjamin for noticing this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162749
91177308-0d34-0410-b5e6-
96231b3b80d8
Nadav Rotem [Tue, 28 Aug 2012 10:01:43 +0000 (10:01 +0000)]
Teach InstCombine to canonicalize [SU]div+[AL]shl patterns.
For example:
%1 = lshr i32 %x, 2
%2 = udiv i32 %1, 100
rdar://
12182093
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162743
91177308-0d34-0410-b5e6-
96231b3b80d8
Bill Wendling [Tue, 28 Aug 2012 07:36:46 +0000 (07:36 +0000)]
The commutative flag is already correctly set within the multiclass. If we set
it here, then a 'register-memory' version would wrongly get the commutative
flag.
<rdar://problem/
12180135>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162741
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 28 Aug 2012 07:30:47 +0000 (07:30 +0000)]
Convert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162740
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 28 Aug 2012 07:05:28 +0000 (07:05 +0000)]
Merge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162738
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Tue, 28 Aug 2012 04:04:29 +0000 (04:04 +0000)]
llvm/test/CodeGen/X86/pr12312.ll: Add -mtriple=x86_64-unknown-unknown.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162736
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Liao [Tue, 28 Aug 2012 03:34:40 +0000 (03:34 +0000)]
Fix PR12312
- Add a target-specific DAG optimization to recognize a pattern PTEST-able.
Such a pattern is a OR'd tree with X86ISD::OR as the root node. When
X86ISD::OR node has only its flag result being used as a boolean value and
all its leaves are extracted from the same vector, it could be folded into an
X86ISD::PTEST node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162735
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Tue, 28 Aug 2012 03:26:49 +0000 (03:26 +0000)]
Check all patterns for missing instruction flags.
Both single-instruction and multi-instruction patterns can be checked
for missing mayLoad / mayStore, and hasSideEffects flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162734
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Tue, 28 Aug 2012 03:11:32 +0000 (03:11 +0000)]
Remove extra MayLoad/MayStore flags from atomic_load/store.
These extra flags are not required to properly order the atomic
load/store instructions. SelectionDAGBuilder chains atomics as if they
were volatile, and SelectionDAG::getAtomic() sets the isVolatile bit on
the memory operands of all atomic operations.
The volatile bit is enough to order atomic loads and stores during and
after SelectionDAG.
This means we set mayLoad on atomic_load, mayStore on atomic_store, and
mayLoad+mayStore on the remaining atomic read-modify-write operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162733
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Tue, 28 Aug 2012 03:11:27 +0000 (03:11 +0000)]
Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM."
This wasn't the right way to enforce ordering of atomics.
We are already setting the isVolatile bit on memory operands of atomic
operations which is good enough to enforce the correct ordering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162732
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Tue, 28 Aug 2012 03:03:05 +0000 (03:03 +0000)]
Fix mips' long branch pass.
Instructions emitted to compute branch offsets now use immediate operands
instead of symbolic labels. This change was needed because there were problems
when R_MIPS_HI16/LO16 relocations were used to make shared objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162731
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Tue, 28 Aug 2012 02:49:14 +0000 (02:49 +0000)]
Split several PPC instruction classes.
Slight reorganisation of PPC instruction classes for scheduling. No
functionality change for existing subtargets.
- Clearly separate load/store-with-update instructions from regular loads and stores.
- Split IntRotateD -> IntRotateD and IntRotateDI
- Split out fsub and fadd from FPGeneral -> FPAddSub
- Update existing itineraries
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162729
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Tue, 28 Aug 2012 02:12:42 +0000 (02:12 +0000)]
Fix bug 13532.
In SelectionDAGLegalize::ExpandLegalINT_TO_FP, expand INT_TO_FP nodes without
using any f64 operations if f64 is not a legal type.
Patch by Stefan Kristiansson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162728
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Tue, 28 Aug 2012 02:10:33 +0000 (02:10 +0000)]
Allow remat of LI on PPC.
Allow load-immediates to be rematerialised in the register coalescer for
PPC. This makes test/CodeGen/PowerPC/big-endian-formal-args.ll fail,
because it relies on a register move getting emitted. The immediate load is
equivalent, so change this test case.
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162727
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Tue, 28 Aug 2012 02:10:30 +0000 (02:10 +0000)]
Add the Freescale vendor to Triple.
Adds the vendor 'fsl' (used by Freescale SDK) to Triple. This will allow
clang support for Freescale cross-compile configurations.
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162726
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Tue, 28 Aug 2012 02:10:27 +0000 (02:10 +0000)]
Eliminate redundant CR moves on PPC32.
The 32-bit ABI requires CR bit 6 to be set if the call has fp arguments and
unset if it doesn't. The solution up to now was to insert a MachineNode to
set/unset the CR bit, which produces a CR vreg. This vreg was then copied
into CR bit 6. When the register allocator saw a bunch of these in the same
function, it allocated the set/unset CR bit in some random CR register (1
extra instruction) and then emitted CR moves before every vararg function
call, rather than just setting and unsetting CR bit 6 directly before every
vararg function call. This patch instead inserts a PPCcrset/PPCcrunset
instruction which are then matched by a dedicated instruction pattern.
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162725
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Tue, 28 Aug 2012 02:10:15 +0000 (02:10 +0000)]
Optimize zext on PPC64.
The zeroextend IR instruction is lowered to an 'and' node with an immediate
mask operand, which in turn gets legalised to a sequence of ori's & ands.
This can be done more efficiently using the rldicl instruction.
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162724
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Tue, 28 Aug 2012 01:17:46 +0000 (01:17 +0000)]
Temporarily revert this to bring back the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162722
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Tue, 28 Aug 2012 00:02:01 +0000 (00:02 +0000)]
More missing mayLoad flags on AVX multiclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162714
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Mon, 27 Aug 2012 23:58:52 +0000 (23:58 +0000)]
Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.
It is not safe to use normal LDR instructions because they may be
reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag
that prevents reordering.
Atomic loads are also prevented from participating in rematerialization
and load folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162713
91177308-0d34-0410-b5e6-
96231b3b80d8
Sebastian Pop [Mon, 27 Aug 2012 23:05:06 +0000 (23:05 +0000)]
Add --program-prefix support to build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162707
91177308-0d34-0410-b5e6-
96231b3b80d8
Marshall Clow [Mon, 27 Aug 2012 22:53:35 +0000 (22:53 +0000)]
Fix compile error when building with C++11 - clang thinks that PRIx64 is a user-defined suffix or something
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162704
91177308-0d34-0410-b5e6-
96231b3b80d8
Bill Wendling [Mon, 27 Aug 2012 22:12:44 +0000 (22:12 +0000)]
Make sure we add the predicate after all of the registers are added.
<rdar://problem/
12183003>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162703
91177308-0d34-0410-b5e6-
96231b3b80d8
Dan Gohman [Mon, 27 Aug 2012 18:31:36 +0000 (18:31 +0000)]
Don't use for loops for code that is only intended to execute once. No
intended functionality change. Thanks to Ahmed Charles for spotting it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162686
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Mon, 27 Aug 2012 16:04:24 +0000 (16:04 +0000)]
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162678
91177308-0d34-0410-b5e6-
96231b3b80d8
Danil Malyshev [Mon, 27 Aug 2012 15:34:01 +0000 (15:34 +0000)]
Fix comment for function RuntimeDyldImpl.resolveRelocation()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162677
91177308-0d34-0410-b5e6-
96231b3b80d8
Hongbin Zheng [Mon, 27 Aug 2012 13:49:24 +0000 (13:49 +0000)]
Remove the the block_node_iterator of Region, replace it by the block_iterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162672
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Atanasyan [Mon, 27 Aug 2012 12:29:01 +0000 (12:29 +0000)]
Support MIPS DSP Rev2 intrinsics.
The patch reviewed by Akira Hatanaka.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162668
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Mon, 27 Aug 2012 11:50:26 +0000 (11:50 +0000)]
llvm/test/CodeGen/X86/fma.ll: Add -march=x86, or two tests would fail on non-x86 hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162667
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Mon, 27 Aug 2012 10:10:10 +0000 (10:10 +0000)]
DWARFDebugRangeList.cpp: Use PRIx64 for uint64_t as format string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162665
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Mon, 27 Aug 2012 09:37:54 +0000 (09:37 +0000)]
llvm/test/CodeGen/X86/fma_patterns.ll: Add -mtriple=x86_64. It was incompatible on i686 and Windows x64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162664
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 27 Aug 2012 08:08:30 +0000 (08:08 +0000)]
Remove MMX shift intrinsic handling code that also exists in SelectionDAGBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162661
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 27 Aug 2012 07:55:50 +0000 (07:55 +0000)]
Commit test change for r162658.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162660
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Samsonov [Mon, 27 Aug 2012 07:24:43 +0000 (07:24 +0000)]
[DebugInfo] fixup for r162657: update CMakeLists.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162659
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 27 Aug 2012 07:19:59 +0000 (07:19 +0000)]
Don't allow vextractf128 to be folded with unaligned stores. We don't fold unaligned loads so shouldn't fold unaligned stores as it can cause an alignment fault to occur.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162658
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Samsonov [Mon, 27 Aug 2012 07:17:47 +0000 (07:17 +0000)]
Add basic support for .debug_ranges section to LLVM's DebugInfo library.
This section (introduced in DWARF-3) is used to define instruction address
ranges for functions that are not contiguous and can't be described
by low_pc/high_pc attributes (this is the usual case for inlined subroutines).
The patch is the first step to support fetching complete inlining info from DWARF.
Reviewed by Benjamin Kramer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162657
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 27 Aug 2012 07:04:50 +0000 (07:04 +0000)]
Fold some patterns into instruction definitons so tablegen can infer flags removing the need for an explicit 'neverHasSideEffects = 1'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162656
91177308-0d34-0410-b5e6-
96231b3b80d8
Anitha Boyapati [Mon, 27 Aug 2012 06:59:01 +0000 (06:59 +0000)]
FMA3 tests on bdver2 target for changes made in rev 162012. Also made
corresponding changes to existing tests for darwin triple to ensure that
same pattern is tested for bdver2 target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162655
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 27 Aug 2012 06:08:57 +0000 (06:08 +0000)]
Add HasAVX1Only predicate and use it for patterns that have an AVX1 instruction and an AVX2 instruction rather than relying on AddedComplexity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162654
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 27 Aug 2012 03:38:15 +0000 (03:38 +0000)]
Make sure that FMA3 is favored even when FMA4 is also enabled. Test case for r162454.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162653
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Mon, 27 Aug 2012 03:03:07 +0000 (03:03 +0000)]
Pass -lLTO after gold-plugin.o so that it gets used in systems that default to
--as-needed.
Patch by Felix Geyer. Fixes pr13262.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162652
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 26 Aug 2012 22:01:42 +0000 (22:01 +0000)]
Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ReadArgMem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649
91177308-0d34-0410-b5e6-
96231b3b80d8
Richard Smith [Fri, 24 Aug 2012 23:29:28 +0000 (23:29 +0000)]
Fix integer undefined behavior due to signed left shift overflow in LLVM.
Reviewed offline by chandlerc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 24 Aug 2012 23:29:07 +0000 (23:29 +0000)]
Add missing mayLoad flags to a large class of AVX *_Int instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162622
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 24 Aug 2012 22:46:55 +0000 (22:46 +0000)]
Missed tLEApcrelJT.
ARMConstantIslandPass expects this instruction to stay in the same basic
block as the jump table branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162615
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 24 Aug 2012 22:46:53 +0000 (22:46 +0000)]
Infer instruction properties from single-instruction patterns.
Previously, instructions without a primary patterns wouldn't get their
properties inferred. Now, we use all single-instruction patterns for
inference, including 'def : Pat<>' instances.
This causes a lot of instruction flags to change.
- Many instructions no longer have the UnmodeledSideEffects flag because
their flags are now inferred from a pattern.
- Instructions with intrinsics will get a mayStore flag if they already
have UnmodeledSideEffects and a mayLoad flag if they already have
mayStore. This is because intrinsics properties are linear.
- Instructions with atomic_load patterns get a mayStore flag because
atomic loads can't be reordered. The correct workaround is to create
pseudo-instructions instead of using normal loads. PR13693.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162614
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 24 Aug 2012 21:44:11 +0000 (21:44 +0000)]
Explicitly mark LEApcrel pseudos with hasSideEffects.
It's not clear that they should be marked as such, but tbb formation
fails if t2LEApcrelJT is hoisted of of a loop.
This doesn't change the flags on these instructions,
UnmodeledSideEffects was already inferred from the missing pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162603
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 24 Aug 2012 21:08:09 +0000 (21:08 +0000)]
Stop inferring isVariadic from instruction patterns.
Instructions are now only marked as variadic if they use variable_ops in
their ins list.
A variadic SDNode is typically used for call nodes that have the call
arguments as operands.
A variadic MachineInstr can actually encode a variable number of
operands, for example ARM's stm/ldm instructions. A call instruction
does not have to be variadic. The call argument registers are added as
implicit operands.
This change remove the MCID::Variadic flags from most call and return
instructions, allowing us to better verify their operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162599
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 24 Aug 2012 20:52:46 +0000 (20:52 +0000)]
Fix call instruction operands in ARMFastISel.
The ARM BL and BLX instructions don't have predicate operands, but the
thumb variants tBL and tBLX do.
The argument registers should be added as implicit uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162593
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 24 Aug 2012 20:52:44 +0000 (20:52 +0000)]
Mark X86::RET and RETI instructions as variadic.
There is special magic happening when returning floating point values on
the x87 stack. The RET instructions get extra f80 operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162592
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 24 Aug 2012 20:52:42 +0000 (20:52 +0000)]
Avoid including explicit uses when counting SDNode imp-uses.
It is legal to have a register node as an explicit operand, it shouldn't
be counted as an implicit use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162591
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Fri, 24 Aug 2012 20:40:15 +0000 (20:40 +0000)]
Disable Mips' delay slot filler when optimization level is O0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162589
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Fri, 24 Aug 2012 20:21:49 +0000 (20:21 +0000)]
In MipsDAGToDAGISel::SelectAddr, fold add node into address operand, if its
second operand is MipsISD::GPRel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162584
91177308-0d34-0410-b5e6-
96231b3b80d8
Manman Ren [Fri, 24 Aug 2012 18:40:00 +0000 (18:40 +0000)]
Forgot to check in ProfileDataTypes.h in r162576
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162578
91177308-0d34-0410-b5e6-
96231b3b80d8
Manman Ren [Fri, 24 Aug 2012 18:31:44 +0000 (18:31 +0000)]
Profile: move a single enum out of ProfileInfoTypes.h into a new
ProfileDataTypes.h header.
With this patch the old and new profiling code can exist side-by-side. The new
profiling code will be submitted soon and it only supports insert-edge-profiling
for now and will not depend on ProfileInfo.
Patch by Alastair Murray.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162576
91177308-0d34-0410-b5e6-
96231b3b80d8
Manman Ren [Fri, 24 Aug 2012 18:14:27 +0000 (18:14 +0000)]
BranchProb: modify the definition of an edge in BranchProbabilityInfo to handle
the case of multiple edges from one block to another.
A simple example is a switch statement with multiple values to the same
destination. The definition of an edge is modified from a pair of blocks to
a pair of PredBlock and an index into the successors.
Also set the weight correctly when building SelectionDAG from LLVM IR,
especially when converting a Switch.
IntegersSubsetMapping is updated to calculate the weight for each cluster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162572
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 24 Aug 2012 17:08:41 +0000 (17:08 +0000)]
Verify explicit instruction properties when they can be inferred.
It is now allowed to explicitly set hasSideEffects, mayStore, and
mayLoad on instructions with patterns.
Verify that the patterns are consistent with the explicit flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162569
91177308-0d34-0410-b5e6-
96231b3b80d8
Kostya Serebryany [Fri, 24 Aug 2012 16:44:47 +0000 (16:44 +0000)]
[asan/tsan] rename FunctionBlackList* to BlackList* as this class is not limited to functions any more
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162566
91177308-0d34-0410-b5e6-
96231b3b80d8
Kostya Serebryany [Fri, 24 Aug 2012 16:40:11 +0000 (16:40 +0000)]
[asan/tsan] extend the functionality of FunctionBlackList to globals and modules. Patch by Reid Watson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162565
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Divacky [Fri, 24 Aug 2012 16:26:02 +0000 (16:26 +0000)]
Lower constant pools and jump tables via TOC on PPC64/SVR4.
In collaboration with Adhemerval Zanella.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162562
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Fri, 24 Aug 2012 15:06:28 +0000 (15:06 +0000)]
GVN: Fix quadratic runtime on the number of switch cases.
No intended behavior change. This was introduced in r162023. With the fixed
algorithm a Release build of ARMInstPrinter.cpp goes from 16s to 10s on a
2011 MBP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162559
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 24 Aug 2012 14:43:30 +0000 (14:43 +0000)]
Fix load/store SDNode flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162558
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 24 Aug 2012 14:43:27 +0000 (14:43 +0000)]
Add missing SDNPSideEffect flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162557
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 24 Aug 2012 14:43:22 +0000 (14:43 +0000)]
Remove more mayLoad workarounds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162556
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Fri, 24 Aug 2012 09:53:43 +0000 (09:53 +0000)]
Try to appease MSVC even more elaborately in the alignment hacking space.
MSVC doesn't support passing by-value parameters with alignment of
16-bytes or higher apparantly. What is deeply confusing is that it seems
to *sometimes* (but not always) apply this to any type whose alignment
is set using __declspec(align(...)). This caused lots of errors when we switch
SmallVector over to use the automatically aligned character array
utilities as they used __declspec(align(...)) heavily.
As a pretty horrible but effective work-around, we instead cherry pick
the smallest alignment sizes with specific types that happen to have the
correct alignment, and then fall back to the attribute solution past
them. This should resolve the MSVC build errors folks have been hitting.
Sorry for that. In good news, it will do this without introducing other
UB I hope. =]
Thanks to Timur Iskhodzhanov for helping me test this!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162549
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 24 Aug 2012 04:03:22 +0000 (04:03 +0000)]
Custom lower FMA intrinsics to target specific nodes and remove the patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162534
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Fri, 24 Aug 2012 01:14:27 +0000 (01:14 +0000)]
Use DW_FORM_flag_present to save space in debug information if we're
not in darwin gdb compat mode.
Fixes rdar://
10975088
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162526
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Fri, 24 Aug 2012 01:14:23 +0000 (01:14 +0000)]
Add support for some missing DW_FORM_*.
TODO: Fix code duplication and coding style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162525
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Fri, 24 Aug 2012 01:14:21 +0000 (01:14 +0000)]
Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162524
91177308-0d34-0410-b5e6-
96231b3b80d8
Richard Smith [Fri, 24 Aug 2012 00:35:46 +0000 (00:35 +0000)]
Fix undefined behavior (negation of INT_MIN) in ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162520
91177308-0d34-0410-b5e6-
96231b3b80d8
Richard Smith [Fri, 24 Aug 2012 00:31:45 +0000 (00:31 +0000)]
Fix floating-point divide by zero, in a case where the value was not going to be used anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162518
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 24 Aug 2012 00:31:20 +0000 (00:31 +0000)]
Remove some spurious mayLoad = 0 flags.
They were inserted to silence TableGen's warning about
redundant properties. That warning is now gone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162517
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 24 Aug 2012 00:31:16 +0000 (00:31 +0000)]
Heed guessInstructionProperties, and stop warning on redundant flags.
Emit TableGen errors if guessInstructionProperties is 0 and
instruction properties can't be inferred from patterns.
Allow explicit instruction properties even when they can be inferred.
This patch doesn't change the TableGen output. Redundant properties
are not yet verified because the tree has errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162516
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 24 Aug 2012 00:31:13 +0000 (00:31 +0000)]
Add missing SDNP properties on the flushw node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162515
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Fri, 24 Aug 2012 00:31:10 +0000 (00:31 +0000)]
X86MemBarrier has unmodeled side effects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162514
91177308-0d34-0410-b5e6-
96231b3b80d8
Richard Smith [Fri, 24 Aug 2012 00:01:19 +0000 (00:01 +0000)]
Fix undefined behavior (signed integer overflow) when Clang parses a hexfloat with an enormous exponent. Caught by an existing unit test + -ftrapv.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162505
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Thu, 23 Aug 2012 23:26:57 +0000 (23:26 +0000)]
Formatting cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162499
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Thu, 23 Aug 2012 23:21:11 +0000 (23:21 +0000)]
Add an assert here in case parsing gave us a NULL compile unit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162498
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Thu, 23 Aug 2012 22:52:55 +0000 (22:52 +0000)]
Remove the DW_AT_MIPS_linkage name attribute when we don't need it
output (we're emitting a specification already and the information
isn't changing) and we're not in old gdb compat mode.
Saves 1% on the debug information for a build of llvm.
Fixes rdar://
11043421
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162493
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Thu, 23 Aug 2012 22:36:40 +0000 (22:36 +0000)]
Turn these two options in to trinary state so that they can be
turned on and off separate from the platform if you're on darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162487
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Thu, 23 Aug 2012 22:36:36 +0000 (22:36 +0000)]
Add a flag to DwarfDebug to allow it to communicate whether or not
we're using the darwin old gdb compat mode for emitting dwarf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162486
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Thu, 23 Aug 2012 22:36:31 +0000 (22:36 +0000)]
Preserve operand flags in convertToThreeAddress() by copying operands.
No test case, this is a generalization of r160260.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162485
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Thu, 23 Aug 2012 19:34:46 +0000 (19:34 +0000)]
Tristate mayLoad, mayStore, and hasSideEffects.
Keep track of the set/unset state of these bits along with their
true/false values, but treat '?' as '0' for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162461
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Thu, 23 Aug 2012 19:34:41 +0000 (19:34 +0000)]
Add CodeGenTarget::guessInstructionProperties.
Currently, TableGen just guesses instruction properties when it can't
infer them form patterns.
This adds a guessInstructionProperties flag to the instruction set
definition that will be used to disable guessing. The flag is intended
as a migration aid. It will be removed again when no more targets need
their properties guessed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162460
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Thu, 23 Aug 2012 19:21:38 +0000 (19:21 +0000)]
Fix attributes on X86 store intrinsics.
These intrinsics don't have unmodeled side effects, they are just
stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162459
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 23 Aug 2012 19:06:23 +0000 (19:06 +0000)]
Fix a stub signature. HeuristicReduce should return a bool.
This should fix a -Wdocumentation warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162458
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 23 Aug 2012 18:14:30 +0000 (18:14 +0000)]
Favor FMA3 over FMA4 if both are enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162454
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Thu, 23 Aug 2012 16:54:08 +0000 (16:54 +0000)]
Fix a bunch of -Wdocumentation warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162446
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Thu, 23 Aug 2012 07:32:06 +0000 (07:32 +0000)]
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162438
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Thu, 23 Aug 2012 07:32:02 +0000 (07:32 +0000)]
Only emit the __debug_inlined section if we're trying to be compatible
with older gdbs on darwin.
rdar://
10975874
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162436
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Thu, 23 Aug 2012 07:18:46 +0000 (07:18 +0000)]
Make this darwin specific to try to silence the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162435
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Thu, 23 Aug 2012 07:10:56 +0000 (07:10 +0000)]
Emit pubtypes only when going for darwin gdb compatibility.
rdar://
10393214
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162434
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Thu, 23 Aug 2012 07:10:51 +0000 (07:10 +0000)]
Filecheck-ize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162433
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Thu, 23 Aug 2012 07:10:46 +0000 (07:10 +0000)]
Add an option for darwin gdb compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162432
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 23 Aug 2012 07:00:48 +0000 (07:00 +0000)]
Make the setInst method take its MCInst parameter by reference, a la Jim's
change in r162404.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162431
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 23 Aug 2012 04:57:36 +0000 (04:57 +0000)]
Use a switch statement instead of a bunch of if-else checks and pull out the common function call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162428
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 23 Aug 2012 04:45:31 +0000 (04:45 +0000)]
Remove unused private field to silence build warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162426
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Thu, 23 Aug 2012 00:52:51 +0000 (00:52 +0000)]
80-col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162422
91177308-0d34-0410-b5e6-
96231b3b80d8