Bill Wendling [Mon, 1 Nov 2010 20:41:43 +0000 (20:41 +0000)]
When we look at instructions to convert to setting the 's' flag, we need to look
at more than those which define CPSR. You can have this situation:
(1) subs ...
(2) sub r6, r5, r4
(3) movge ...
(4) cmp r6, 0
(5) movge ...
We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:
(1) sub r1, r2, r3
(2) sub r4, r5, r6
(3) cmp r4, ...
(5) movge ...
(6) cmp r1, ...
(7) movge ...
We cannot convert (1) to "subs" because of the intervening use of CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117950
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Jakob Stoklund Olesen [Mon, 1 Nov 2010 19:49:57 +0000 (19:49 +0000)]
Don't assign new registers created during a split to the same stack slot, but
give them individual stack slots once the are actually spilled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117945
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Jakob Stoklund Olesen [Mon, 1 Nov 2010 19:49:52 +0000 (19:49 +0000)]
Add basic LiveStacks verification.
When an instruction refers to a spill slot with a LiveStacks entry, check that
the spill slot is live at the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117944
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Owen Anderson [Mon, 1 Nov 2010 18:33:37 +0000 (18:33 +0000)]
Use ARM-style comment syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117941
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Bob Wilson [Mon, 1 Nov 2010 18:31:39 +0000 (18:31 +0000)]
NEON does not support truncating vector stores. Radar
8598391.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117940
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Owen Anderson [Mon, 1 Nov 2010 18:30:39 +0000 (18:30 +0000)]
Covert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117939
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Owen Anderson [Mon, 1 Nov 2010 18:26:43 +0000 (18:26 +0000)]
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117938
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Owen Anderson [Mon, 1 Nov 2010 18:13:11 +0000 (18:13 +0000)]
Covert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117937
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Jim Grosbach [Mon, 1 Nov 2010 18:11:14 +0000 (18:11 +0000)]
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117936
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Owen Anderson [Mon, 1 Nov 2010 18:03:16 +0000 (18:03 +0000)]
Covert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117935
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Rafael Espindola [Mon, 1 Nov 2010 17:10:53 +0000 (17:10 +0000)]
Fix test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117932
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Jim Grosbach [Mon, 1 Nov 2010 17:08:58 +0000 (17:08 +0000)]
Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates
codegen using the patterns; the latter gates the assembler recognizing the
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117931
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Rafael Espindola [Mon, 1 Nov 2010 17:07:14 +0000 (17:07 +0000)]
Write the line info to .debug_line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117930
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Jim Grosbach [Mon, 1 Nov 2010 16:59:54 +0000 (16:59 +0000)]
Mark ARM subtarget features that are available for the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117929
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Jim Grosbach [Mon, 1 Nov 2010 16:44:21 +0000 (16:44 +0000)]
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117927
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Rafael Espindola [Mon, 1 Nov 2010 16:27:31 +0000 (16:27 +0000)]
Move EmitInstruction to MCObjectStreamer so that ELF and MachO can share it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117925
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Jim Grosbach [Mon, 1 Nov 2010 15:59:52 +0000 (15:59 +0000)]
The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the
patterns as such
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117923
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Rafael Espindola [Mon, 1 Nov 2010 15:29:07 +0000 (15:29 +0000)]
Add support for .value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117922
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Rafael Espindola [Mon, 1 Nov 2010 14:28:48 +0000 (14:28 +0000)]
Implement .weakref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117911
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Bill Wendling [Mon, 1 Nov 2010 06:00:39 +0000 (06:00 +0000)]
Move instruction encoding bits into the parent class and remove the temporary
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117906
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Bill Wendling [Mon, 1 Nov 2010 05:59:43 +0000 (05:59 +0000)]
More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when the
peephole optimizer is disabled. That's not good at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117905
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Bill Wendling [Mon, 1 Nov 2010 05:50:55 +0000 (05:50 +0000)]
The testcase is now XFAILed. Sorry about the breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117904
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Bill Wendling [Mon, 1 Nov 2010 05:48:44 +0000 (05:48 +0000)]
Disable because peephole is disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117903
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Chris Lattner [Mon, 1 Nov 2010 05:41:10 +0000 (05:41 +0000)]
"mov[zs]x (mem), GR16" are not ambiguous: the mem
must be 8 bits. Support this memory form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117902
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Chris Lattner [Mon, 1 Nov 2010 05:34:34 +0000 (05:34 +0000)]
Implement enough of the missing instalias support to get
aliases installed and working. They now work when the
matched pattern and the result instruction have exactly
the same operand list.
This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://
8017633 and PR7459.
Note that we do not accept instructions like:
movzx 0(%rsp), %rsi
GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand. It could be 8/16/32 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117901
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Owen Anderson [Mon, 1 Nov 2010 05:23:58 +0000 (05:23 +0000)]
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117900
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Chris Lattner [Mon, 1 Nov 2010 05:06:45 +0000 (05:06 +0000)]
rename InstructionInfo -> MatchableInfo since it now
represents InstAliases as well. Rename
isAssemblerInstruction -> Validate since that is what
it does (modulo the ARM $lane hack).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117899
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Chris Lattner [Mon, 1 Nov 2010 04:53:48 +0000 (04:53 +0000)]
refactor initialization of InstructionInfo to be sharable between
instructions and InstAliases. Start creating InstructionInfo's
for Aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117898
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Chris Lattner [Mon, 1 Nov 2010 04:44:29 +0000 (04:44 +0000)]
make the asm matcher emitter reject instructions that have comments
in their asmstring. Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117897
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Chris Lattner [Mon, 1 Nov 2010 04:34:44 +0000 (04:34 +0000)]
refactor InstructionInfo to not have a pointer to CodeGenInstruction
member, and make isAssemblerInstruction() a method (pushing some code
around inside it).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117895
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Chris Lattner [Mon, 1 Nov 2010 04:05:41 +0000 (04:05 +0000)]
define a new CodeGenInstAlias. It has an asmstring and operand list for now,
todo: the result field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117894
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Chris Lattner [Mon, 1 Nov 2010 04:03:32 +0000 (04:03 +0000)]
factor the operand list (and related fields/operations) out of
CodeGenInstruction into its own helper class. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117893
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Chris Lattner [Mon, 1 Nov 2010 03:19:09 +0000 (03:19 +0000)]
avoid needless throw/catch/rethrow, stringref'ize some simple stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117892
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Chris Lattner [Mon, 1 Nov 2010 02:15:23 +0000 (02:15 +0000)]
eliminate the old InstFormatName which is always "AsmString",
simplify CodeGenInstruction. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117891
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Chris Lattner [Mon, 1 Nov 2010 02:09:21 +0000 (02:09 +0000)]
all predicates on an MnemonicAlias must be AssemblerPredicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117890
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Chris Lattner [Mon, 1 Nov 2010 01:47:07 +0000 (01:47 +0000)]
change the singleton register handling code to be based on Record*'s
instead of strings, simplifying it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117889
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Chris Lattner [Mon, 1 Nov 2010 01:37:30 +0000 (01:37 +0000)]
Give AsmMatcherInfo a CodeGenTarget, which simplifies a bunch of
argument passing. Consolidate all SingletonRegister detection
and handling into a new
InstructionInfo::getSingletonRegisterForToken method instead of
having it scattered about. No change in generated .inc files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117888
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Chris Lattner [Mon, 1 Nov 2010 01:07:14 +0000 (01:07 +0000)]
move FlattenVariants out of AsmMatcherEmitter into a shared
CodeGenInstruction::FlattenAsmStringVariants method. Use it
to simplify the code in AsmWriterInst, which now no longer
needs to worry about variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117886
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Chris Lattner [Mon, 1 Nov 2010 00:51:32 +0000 (00:51 +0000)]
add a FIXME, $lane in ARM is an issue that needs to be resolved before
this can start rejecting instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117885
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Chris Lattner [Mon, 1 Nov 2010 00:46:16 +0000 (00:46 +0000)]
reject instructions that contain a \n in their asmstring. Mark
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117884
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Chandler Carruth [Sun, 31 Oct 2010 22:57:03 +0000 (22:57 +0000)]
Add a specialization for 'long', a hole in the set of fundamental
specializations provided here. This is a little annoying because its size
changes from platform to platform. If possible, I may follow up with a patch
that uses standard constants to simplify much of this, but assuming for now
that was avoided for a reason.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117880
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Eric Christopher [Sun, 31 Oct 2010 22:42:55 +0000 (22:42 +0000)]
Revert r117876 for now, it's causing more testsuite failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117879
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Bill Wendling [Sun, 31 Oct 2010 22:07:12 +0000 (22:07 +0000)]
Disable the peephole optimizer until 186.crafty on armv6 is fixed. This is what
looks like is happening:
Without the peephole optimizer:
(1) sub r6, r6, #32
orr r12, r12, lr, lsl r9
orr r2, r2, r3, lsl r10
(x) cmp r6, #0
ldr r9, LCPI2_10
ldr r10, LCPI2_11
(2) sub r8, r8, #32
(a) movge r12, lr, lsr r6
(y) cmp r8, #0
LPC2_10:
ldr lr, [pc, r10]
(b) movge r2, r3, lsr r8
With the peephole optimizer:
ldr r9, LCPI2_10
ldr r10, LCPI2_11
(1*) subs r6, r6, #32
(2*) subs r8, r8, #32
(a*) movge r12, lr, lsr r6
(b*) movge r2, r3, lsr r8
(1) is used by (x) for the conditional move at (a). (2) is used by (y) for the
conditional move at (b). After the peephole optimizer, these the flags resulting
from (1*) are ignored and only the flags from (2*) are considered for both
conditional moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117876
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Nicolas Geoffray [Sun, 31 Oct 2010 20:38:38 +0000 (20:38 +0000)]
Attach a GCModuleInfo to a MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117867
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Chris Lattner [Sun, 31 Oct 2010 19:27:15 +0000 (19:27 +0000)]
fix a crash on:
let Constraints = "$val = $dst", Defs = [EFLAGS] in, isCodeGenOnly = 1 {
we now get:
X86InstrCompiler.td:653:52: error: Expected class, def, defm, multiclass or let definition
let Constraints = "$val = $dst", Defs = [EFLAGS] in, isCodeGenOnly = 1 {
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117863
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Chris Lattner [Sun, 31 Oct 2010 19:22:57 +0000 (19:22 +0000)]
fix the !eq operator in tblgen to return a bit instead of an int.
Use this to make the X86 and ARM targets set isCodeGenOnly=1
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117862
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Chris Lattner [Sun, 31 Oct 2010 19:15:18 +0000 (19:15 +0000)]
two changes: make the asmmatcher generator ignore ARM pseudos properly,
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117861
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Chris Lattner [Sun, 31 Oct 2010 19:10:56 +0000 (19:10 +0000)]
reapply r117858 with apparent editor malfunction fixed (somehow I
got a dulicated line).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117860
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Chris Lattner [Sun, 31 Oct 2010 19:05:32 +0000 (19:05 +0000)]
revert r117858 while I check out a failure I missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117859
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Chris Lattner [Sun, 31 Oct 2010 18:48:12 +0000 (18:48 +0000)]
the asm matcher can't handle operands with modifiers (like ${foo:bar}).
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the
instruction 'isCodeGenOnly'.
Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are
doing this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117858
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Chris Lattner [Sun, 31 Oct 2010 18:43:46 +0000 (18:43 +0000)]
sketch out the planned instruction alias mechanism, add some comments about
how the push/pop mnemonic aliases are wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117857
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Duncan Sands [Sun, 31 Oct 2010 13:21:44 +0000 (13:21 +0000)]
Factorize the duplicated logic for choosing the right argument
calling convention out of the fast and normal ISel files, and
into the calling convention TD file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117856
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Duncan Sands [Sun, 31 Oct 2010 13:02:38 +0000 (13:02 +0000)]
Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86,
which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117855
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Duncan Sands [Sun, 31 Oct 2010 10:29:14 +0000 (10:29 +0000)]
Explain the return value of CCAssignFn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117854
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Rafael Espindola [Sun, 31 Oct 2010 00:16:26 +0000 (00:16 +0000)]
Add support for files with more than 65280 sections. No testcase since
it would be a bit too big :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117849
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Eric Christopher [Sat, 30 Oct 2010 21:25:26 +0000 (21:25 +0000)]
Make sure we have a legal type (and simple) before continuing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117848
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Benjamin Kramer [Sat, 30 Oct 2010 21:07:28 +0000 (21:07 +0000)]
Validate HTML.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117847
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Chris Lattner [Sat, 30 Oct 2010 20:21:00 +0000 (20:21 +0000)]
add missing tag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117846
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Chris Lattner [Sat, 30 Oct 2010 20:15:02 +0000 (20:15 +0000)]
have GetAliasRequiredFeatures get its features from
AsmMatcherInfo so we don't have two places that know the
feature -> enum mapping. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117845
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Chris Lattner [Sat, 30 Oct 2010 20:07:57 +0000 (20:07 +0000)]
simplify code that creates SubtargetFeatureInfo, ensuring that features
that are only used by MnemonicAliases will be found.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117844
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Chris Lattner [Sat, 30 Oct 2010 19:57:17 +0000 (19:57 +0000)]
fix a fixme in stringmatcher, having it generate nice looking code if the
'tomatch' code contains \n's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117843
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Chris Lattner [Sat, 30 Oct 2010 19:47:49 +0000 (19:47 +0000)]
fix typos and some serious bugs in feature handling (but not for
cases that are currently exercised). Thanks to Frits van Bommel for
the great review!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117840
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Chris Lattner [Sat, 30 Oct 2010 19:38:20 +0000 (19:38 +0000)]
Resolve a terrible hack in tblgen: instead of hardcoding
"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117831
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Chris Lattner [Sat, 30 Oct 2010 19:23:13 +0000 (19:23 +0000)]
Implement (and document!) support for MnemonicAlias's to have Requires
directives, allowing things like this:
def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
Move the rest of the X86 MnemonicAliases over to the .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117830
91177308-0d34-0410-b5e6-
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Chris Lattner [Sat, 30 Oct 2010 18:57:07 +0000 (18:57 +0000)]
fix build problem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117828
91177308-0d34-0410-b5e6-
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Chris Lattner [Sat, 30 Oct 2010 18:56:12 +0000 (18:56 +0000)]
diagnose targets that define two alises with the same 'from' mnemonic
with a useful error message instead of having tblgen explode with an
assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117827
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Chris Lattner [Sat, 30 Oct 2010 18:48:18 +0000 (18:48 +0000)]
emit the mnemonic aliases in their own helper function instead of
inline into MatchInstructionImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117826
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Chris Lattner [Sat, 30 Oct 2010 18:23:25 +0000 (18:23 +0000)]
really zap alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117824
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Chris Lattner [Sat, 30 Oct 2010 18:22:53 +0000 (18:22 +0000)]
move fcompi alias to .td file and zap some useless code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117823
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Chris Lattner [Sat, 30 Oct 2010 18:17:33 +0000 (18:17 +0000)]
move rep aliases to td file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117822
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Chris Lattner [Sat, 30 Oct 2010 18:14:54 +0000 (18:14 +0000)]
move sal aliases to .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117821
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Chris Lattner [Sat, 30 Oct 2010 18:13:10 +0000 (18:13 +0000)]
fix an encoding mismatch where "sal %eax, 1" was not using the short encoding
for shl. Caught by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117820
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Chris Lattner [Sat, 30 Oct 2010 18:07:17 +0000 (18:07 +0000)]
move a bunch more aliases from .cpp -> .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117819
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Chris Lattner [Sat, 30 Oct 2010 17:56:50 +0000 (17:56 +0000)]
move cmov aliases to .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117818
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Chris Lattner [Sat, 30 Oct 2010 17:51:45 +0000 (17:51 +0000)]
move setcc and jcc aliases from .cpp to .td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117817
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Chris Lattner [Sat, 30 Oct 2010 17:38:55 +0000 (17:38 +0000)]
move some code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117816
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Chris Lattner [Sat, 30 Oct 2010 17:36:36 +0000 (17:36 +0000)]
implement (and document!) the first kind of MC assembler alias, which
just remaps one mnemonic to another. Convert a few of the X86 aliases
from .cpp to .td code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117815
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Chris Lattner [Sat, 30 Oct 2010 17:01:25 +0000 (17:01 +0000)]
add a test for the ud2a alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117803
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Duncan Sands [Sat, 30 Oct 2010 16:12:16 +0000 (16:12 +0000)]
Now that the MallocInst no longer exists, this workaround for
it claiming not to have side-effects is no longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117789
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Jim Grosbach [Sat, 30 Oct 2010 15:57:50 +0000 (15:57 +0000)]
Allow specifying a CPU to llvm-mc, so that we can properly set up subtarget
feature lists for instruction pattern predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117788
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Jim Grosbach [Sat, 30 Oct 2010 14:54:23 +0000 (14:54 +0000)]
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117787
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Jim Grosbach [Sat, 30 Oct 2010 13:48:28 +0000 (13:48 +0000)]
Clean up comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117785
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Jim Grosbach [Sat, 30 Oct 2010 13:46:39 +0000 (13:46 +0000)]
80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117784
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Duncan Sands [Sat, 30 Oct 2010 12:59:44 +0000 (12:59 +0000)]
If a function does a volatile load from a global constant, do not
consider it to be readonly. In fact, don't even consider it to be
readonly if it does a volatile load from an AllocaInst either (it
is debatable as to whether readonly would be correct or not in this
case; play safe for the moment). This fixes PR8279.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117783
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Jim Grosbach [Sat, 30 Oct 2010 12:59:16 +0000 (12:59 +0000)]
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117782
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Chris Lattner [Sat, 30 Oct 2010 05:14:01 +0000 (05:14 +0000)]
Rename alignof -> alignOf to avoid irritating C++'0x compilers,
PR8423, patch by nobled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117774
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Chris Lattner [Sat, 30 Oct 2010 04:57:14 +0000 (04:57 +0000)]
stay out of the reserved namespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117773
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Chris Lattner [Sat, 30 Oct 2010 04:35:59 +0000 (04:35 +0000)]
simplify this code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117771
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Chris Lattner [Sat, 30 Oct 2010 04:09:10 +0000 (04:09 +0000)]
split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117769
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Jim Grosbach [Sat, 30 Oct 2010 01:40:16 +0000 (01:40 +0000)]
Avoid re-evaluating MI.getNumOperands() every iteration of the loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117766
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Jakob Stoklund Olesen [Sat, 30 Oct 2010 01:26:19 +0000 (01:26 +0000)]
Include MachineBasicBlock numbers in viewCFG() output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117765
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Jakob Stoklund Olesen [Sat, 30 Oct 2010 01:26:16 +0000 (01:26 +0000)]
Make sure copies are inserted after any exception handling labels at the top of
a basic block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117764
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Jakob Stoklund Olesen [Sat, 30 Oct 2010 01:26:14 +0000 (01:26 +0000)]
Add SkipPHIsAndLabels from PHIElimination to MachineBasicBlock. It is needed
elsewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117763
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Jakob Stoklund Olesen [Sat, 30 Oct 2010 01:26:11 +0000 (01:26 +0000)]
Disable more of physical register live intervals verification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117762
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Jakob Stoklund Olesen [Sat, 30 Oct 2010 01:26:09 +0000 (01:26 +0000)]
Print out register class of spilled register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117761
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Bob Wilson [Sat, 30 Oct 2010 00:54:37 +0000 (00:54 +0000)]
Overhaul memory barriers in the ARM backend. Radar
8601999.
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain. It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions. Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions. Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756
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Tobias Grosser [Sat, 30 Oct 2010 00:54:26 +0000 (00:54 +0000)]
Add polly support to the build system.
Update the cmake and autoconf build system to compile polly
as a shared library if it is checked out into tools/polly. In case
polly is not checked out, nothing changes.
This models the way clang can be added to llvm if checked out to tools/clang.
Also rebuild configure.
Patch contributed by ether.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117755
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Jim Grosbach [Sat, 30 Oct 2010 00:37:59 +0000 (00:37 +0000)]
Encode the register list operands for ARM mode LDM/STM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117753
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Bill Wendling [Fri, 29 Oct 2010 23:50:21 +0000 (23:50 +0000)]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are
conditional. Check for those instructions explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747
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John Thompson [Fri, 29 Oct 2010 23:37:38 +0000 (23:37 +0000)]
Mult-alt constraint incremental development step 3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117746
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