Fix a bug in the x86-32 code generated for segmented stacks.

Currently LLVM pads the call to __morestack with a add and sub of 8
bytes to esp.  This isn't correct since __morestack expects the call
to be followed directly by a ret.

This commit also adjusts the relevant test-case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145765 91177308-0d34-0410-b5e6-96231b3b80d8

Creating multiple JITs on X86 in multiple threads causes multiple writes (of
the same value) to this variable. This code could be refactored, but it doesn't
matter since the old JIT is going away. Add tsan annotations to ignore the
race.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145745 91177308-0d34-0410-b5e6-96231b3b80d8

[arm-fast-isel] Unaligned stores of floats require special care.
rdar://10510150

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145742 91177308-0d34-0410-b5e6-96231b3b80d8

Fixed deadstoreelimination bug where negative indices were incorrectly causing the optimisation to occur

Turns out long long + unsigned long long is unsigned.  Doh!

Fixes http://llvm.org/bugs/show_bug.cgi?id=11455

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145731 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for constant folding the pow intrinsic.
rdar://10514247

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145730 91177308-0d34-0410-b5e6-96231b3b80d8

ARM NEON VEXT aliases for data type suffices.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145726 91177308-0d34-0410-b5e6-96231b3b80d8

ARM VEXT tighten up operand classes a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145722 91177308-0d34-0410-b5e6-96231b3b80d8

ARM VST1 single lane assembly parsing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145718 91177308-0d34-0410-b5e6-96231b3b80d8

Test cases for 64-bit multiplication and division.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145717 91177308-0d34-0410-b5e6-96231b3b80d8

Fix test cases to use FileCheck.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145716 91177308-0d34-0410-b5e6-96231b3b80d8

Move global variables in TargetMachine into new TargetOptions class. As an API
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8

ARM tests for VLD1 single lane w/ writeback.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145713 91177308-0d34-0410-b5e6-96231b3b80d8

ARM VLD1 single lane assembly parsing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145712 91177308-0d34-0410-b5e6-96231b3b80d8

ARM encoder method needs the physical register number, not the enum.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145711 91177308-0d34-0410-b5e6-96231b3b80d8

TargetMachine: document unnamed bool argument

Its meaning was slightly mysterious without looking at
subclasses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145705 91177308-0d34-0410-b5e6-96231b3b80d8

unittests: add ErrorStr to ExecutionEngine test

Makes failures more self-explanatory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145704 91177308-0d34-0410-b5e6-96231b3b80d8

[arm-fast-isel] After promoting a function parameter be sure to update the
argument value type.  Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145701 91177308-0d34-0410-b5e6-96231b3b80d8

specify cpu for test to fix failure on some darwin systems with a g4+ cpu

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145699 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.

Add the 16-bit lane variants while I'm at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8

Fix quadratic behavior in InlineFunction by fetching the personality function of the callee once and not for every invoke in the caller.

The callee is usually smaller than the caller, too. This reduces the compile
time of ARMDisassembler.cpp by 32% (Release build). It still takes ages to
compile though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145690 91177308-0d34-0410-b5e6-96231b3b80d8

Check for error after InstantiateMultclassDef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145689 91177308-0d34-0410-b5e6-96231b3b80d8

Add XOP feature flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145682 91177308-0d34-0410-b5e6-96231b3b80d8

Reduce duplicate code in isHorizontalBinOp and add some asserts to protect assumptions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145681 91177308-0d34-0410-b5e6-96231b3b80d8

Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145680 91177308-0d34-0410-b5e6-96231b3b80d8

remove unneeded FIXME comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145679 91177308-0d34-0410-b5e6-96231b3b80d8

adjust the instruction ordering in some PPC tests: changes due to postRA haz. rec.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145678 91177308-0d34-0410-b5e6-96231b3b80d8

make sure ScheduleDAGInstrs::EmitSchedule does not crash when the first instruction in Sequence is a Noop

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145677 91177308-0d34-0410-b5e6-96231b3b80d8

update PPC 940 hazard rec. to function in postRA mode

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145676 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a few more places where TargetData/TargetLibraryInfo is not being passed.
Add FIXMEs to places that are non-trivial to fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145661 91177308-0d34-0410-b5e6-96231b3b80d8

ARM start parsing VLD1 single lane instructions.

The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145655 91177308-0d34-0410-b5e6-96231b3b80d8

Abuse of mass replace isn't warranted even when the build is failing.  Thanks
for the suggestion, Eric.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145643 91177308-0d34-0410-b5e6-96231b3b80d8

Fix build by not assuming TLI is guaranteed. Will have to track down cases where
TLI isn't being passed to ensure we don't miss opportunities to fold calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145641 91177308-0d34-0410-b5e6-96231b3b80d8

Prevent library calls from being folded if -fno-builtin has been specified.
rdar://10500969

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145639 91177308-0d34-0410-b5e6-96231b3b80d8

TableGen: fix CMake build s'more

Oops, missed another missing file from r145629.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145636 91177308-0d34-0410-b5e6-96231b3b80d8

CodeGen: fix CMake build

Missing file from r145629.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145634 91177308-0d34-0410-b5e6-96231b3b80d8

ExecutionEngine: honor optimization level

It was getting ignored after r144788.

Also fix an accidental implicit cast from the OptLevel enum
to an optional bool argument. MSVC warned on this, but gcc
didn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145633 91177308-0d34-0410-b5e6-96231b3b80d8

Last bit of TargetLibraryInfo propagation.  Also fixed a case for TargetData
where it appeared beneficial to pass.
More of rdar://10500969

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145630 91177308-0d34-0410-b5e6-96231b3b80d8

Add a deterministic finite automaton based packetizer for VLIW architectures

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145629 91177308-0d34-0410-b5e6-96231b3b80d8

Fix unreachable return & simplify some branches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145627 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-config: Replace with C++ version (was llvm-config-2).
   - Another reapply of r144300, with hopefully one last fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145623 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-config-2: Fix --cflags and --includedir which pointed at the wrong
directory when running from a build directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145622 91177308-0d34-0410-b5e6-96231b3b80d8

Dummy commit to check commit access.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145619 91177308-0d34-0410-b5e6-96231b3b80d8

Improved fix for abs(val) != 0 to check other similar case.  Also fixed style issues and confusing comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145618 91177308-0d34-0410-b5e6-96231b3b80d8

[asan] two minor fixes: use UnreachableInst after the neverreturn function call; use report_fatal_error when blacklist file can not be found

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145611 91177308-0d34-0410-b5e6-96231b3b80d8

Add missing functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145608 91177308-0d34-0410-b5e6-96231b3b80d8

Autodetect bulldozers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145607 91177308-0d34-0410-b5e6-96231b3b80d8

Add a few more functions to TargetLibraryInfo. More of rdar://10500969.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145596 91177308-0d34-0410-b5e6-96231b3b80d8

fix broken tag

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145590 91177308-0d34-0410-b5e6-96231b3b80d8

Revert commit 145449 (ddunbar) since it is breaking the dragonegg buildbots.
Original commit message:
llvm-config: Replace with C++ version (was llvm-config-2).
 - Reapply of r144300, with lots of fixes/migration easement in between.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145582 91177308-0d34-0410-b5e6-96231b3b80d8

For 64-bit the rest of the general regs are ok for the q constraint. Make
sure we can emit both the high and low versions of those registers.

Fixes rdar://10392864

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145579 91177308-0d34-0410-b5e6-96231b3b80d8

Add some missing anchors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145578 91177308-0d34-0410-b5e6-96231b3b80d8

Pass AVX vectors which are arguments to varargs functions on the stack. <rdar://problem/10463281>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145573 91177308-0d34-0410-b5e6-96231b3b80d8

Removed use of grep from test and moved it to be with other icmp tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145570 91177308-0d34-0410-b5e6-96231b3b80d8

Added instcombine pattern to spot comparing -val or val against 0.
(val != 0) == (-val != 0) so "abs(val) != 0" becomes "val != 0"

Fixes <rdar://problem/10482509>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145563 91177308-0d34-0410-b5e6-96231b3b80d8

Propagate TargetLibraryInfo throughout ConstantFolding.cpp and
InstructionSimplify.cpp.  Other fixups as needed.
Part of rdar://10500969

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145559 91177308-0d34-0410-b5e6-96231b3b80d8

Make use of "getScalarType()". No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145556 91177308-0d34-0410-b5e6-96231b3b80d8

Small fix for assembler generation on Darwin PPC64.  Patch by Michael Kostylev.  PR11437.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145553 91177308-0d34-0410-b5e6-96231b3b80d8

Replace an assert() with an actual diagnostic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145535 91177308-0d34-0410-b5e6-96231b3b80d8

make asan work at -O0, llvm part. Patch by glider@google.com

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145530 91177308-0d34-0410-b5e6-96231b3b80d8

Support for encoding all FMA4 instructions and tablegen patterns for all
remaining FMA4 instructions and intrinsics with tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8

Make GlobalMerge honor the preferred alignment on globals without an explicitly specified alignment.

<rdar://problem/10497732>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145523 91177308-0d34-0410-b5e6-96231b3b80d8

More cleanups. No content change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145522 91177308-0d34-0410-b5e6-96231b3b80d8

Minor cleanup. No content change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145521 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the install-clang-c makefile target.

When I did this before it broke a buildbot that was testing that target, but
we've removed that buildbot now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145519 91177308-0d34-0410-b5e6-96231b3b80d8

Remove an XXX which hasn't been fixed yet. It's too late now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145518 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unused variable

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145517 91177308-0d34-0410-b5e6-96231b3b80d8

Add some tests for all-lanes VLD1 parsing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145512 91177308-0d34-0410-b5e6-96231b3b80d8

ARM parsing for VLD1 all lanes, with writeback.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145510 91177308-0d34-0410-b5e6-96231b3b80d8

Add a few functions to TargetLibraryInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145508 91177308-0d34-0410-b5e6-96231b3b80d8

ARM parsing for VLD1 two register all lanes, no writeback.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8

Add test arch to make it pass on non x86 targets

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145498 91177308-0d34-0410-b5e6-96231b3b80d8

X86: Turns out bulldozer also supports sse42 and lzcnt.

While at it remove the barcelona/instanbul/shanghai subtargets, they're
unsupported by GCC and look pretty broken.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145494 91177308-0d34-0410-b5e6-96231b3b80d8

X86: Add subtargets for AMD's bulldozer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145493 91177308-0d34-0410-b5e6-96231b3b80d8

Add a tripple to the test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145489 91177308-0d34-0410-b5e6-96231b3b80d8

X86: PerformOrCombine introduced a vselect node with a wrong order of operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145488 91177308-0d34-0410-b5e6-96231b3b80d8

Add instruction selection support for AVX2 horizontal add/sub instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145487 91177308-0d34-0410-b5e6-96231b3b80d8

Mention that -O4 does result in more optimization when used with
-fplugin-arg-dragonegg-enable-gcc-optzns, though it usually isn't
a win.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145486 91177308-0d34-0410-b5e6-96231b3b80d8

Merge VPERM2F128/VPERM2I128 ISD node types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145485 91177308-0d34-0410-b5e6-96231b3b80d8

Better test case found in duplicate PR10570.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145484 91177308-0d34-0410-b5e6-96231b3b80d8

Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145483 91177308-0d34-0410-b5e6-96231b3b80d8

LSR: handle the expansion of phi operands that use postinc forms of the IV.

Fixes PR11431: SCEVExpander::expandAddRecExprLiterally(const llvm::SCEVAddRecExpr*): Assertion `(!isa<Instruction>(Result) || SE.DT->dominates(cast<Instruction>(Result), Builder.GetInsertPoint())) && "postinc expansion does not dominate use"' failed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145482 91177308-0d34-0410-b5e6-96231b3b80d8

Whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145470 91177308-0d34-0410-b5e6-96231b3b80d8

Alphabetize TargetLibraryInfo enum and fix doxygen comments.  No functional
change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145468 91177308-0d34-0410-b5e6-96231b3b80d8

llvm_unreachable() is not for user diagnostics....

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145465 91177308-0d34-0410-b5e6-96231b3b80d8

ARM parsing aliases for VLD1 single register all lanes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for sqrt, sqrtl, and sqrtf in TargetLibraryInfo.  Disable
(fptrunc (sqrt (fpext x))) -> (sqrtf x) transformation if -fno-builtin is
specified.
rdar://10466410

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145460 91177308-0d34-0410-b5e6-96231b3b80d8

Tidy up a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145458 91177308-0d34-0410-b5e6-96231b3b80d8

Add comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145456 91177308-0d34-0410-b5e6-96231b3b80d8

ARM parsing aliases for data-size suffices on VST1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145454 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheckize.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145452 91177308-0d34-0410-b5e6-96231b3b80d8

Change names for MIPS "generic" processors defined in Mips.td to match what GNU
tools use. Patch by Simon Atanasyan.

"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145451 91177308-0d34-0410-b5e6-96231b3b80d8

ARM assembly parsing and encoding for four-register VST1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-config: Replace with C++ version (was llvm-config-2).
 - Reapply of r144300, with lots of fixes/migration easement in between.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145449 91177308-0d34-0410-b5e6-96231b3b80d8

Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was generating poor code for some SSE builtins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145448 91177308-0d34-0410-b5e6-96231b3b80d8

Enable some VST1 tests and add a few more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145443 91177308-0d34-0410-b5e6-96231b3b80d8

ARM assembly parsing and encoding for three-register VST1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145442 91177308-0d34-0410-b5e6-96231b3b80d8

Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.

Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.

This also makes the AVX variants redundant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145440 91177308-0d34-0410-b5e6-96231b3b80d8

Potential bug in RewriteLoopBodyWithConditionConstant: use iterator should not be changed inside the uses enumeration loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145432 91177308-0d34-0410-b5e6-96231b3b80d8

Update the docs for some of the test-suite configure changes and
be more clear about what to do and how to do it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145426 91177308-0d34-0410-b5e6-96231b3b80d8

If fast-isel fails, remove dead instructions generated during the failed
attempt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145425 91177308-0d34-0410-b5e6-96231b3b80d8