firefly-linux-kernel-4.4.55.git
9 years agoMIPS: ath79: Use the common clk API
Alban Bedel [Sun, 19 Apr 2015 12:30:04 +0000 (14:30 +0200)]
MIPS: ath79: Use the common clk API

Make the code simpler and open the way for device tree clocks.

[ralf@linux-mips.org: Resolved conflict with 2a552da6 (MIPS/IRQCHIP: Move
irq_chip from arch/mips to drivers/irqchip.)]

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9774/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: ath79: Improve the DDR controller interface
Alban Bedel [Sun, 19 Apr 2015 12:30:03 +0000 (14:30 +0200)]
MIPS: ath79: Improve the DDR controller interface

The DDR controller need to be used by the IRQ controller to flush
the write buffer of some devices before running the IRQ handler.
It is also used by the PCI controller to setup the PCI memory windows.

The current interface used to access the DDR controller doesn't
provides any useful abstraction and simply rely on a shared global
pointer.

Replace this by a simple API to setup the PCI memory windows and use
the write buffer flush independently of the SoC type. That remove the
need for the shared global pointer, simplify the IRQ handler code.

[ralf@linux-mips.org: Folded in Alban Bedel's follup fix.]

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9773/
Patchwork: http://patchwork.linux-mips.org/patch/10543/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: ath79: Correctly name the defines for the PLL_FB register
Alban Bedel [Sun, 19 Apr 2015 12:30:02 +0000 (14:30 +0200)]
MIPS: ath79: Correctly name the defines for the PLL_FB register

This register is named PLL_FB and is not a divider but a multiplier.
To make things less confusing rename the ARxxxx_PLL_DIV_SHIFT and
ARxxxx_PLL_DIV_MASK macros to ARxxxx_PLL_FB_SHIFT and
ARxxxx_PLL_FB_MASK.

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9772/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: ath79: Enable ZBOOT support
Alban Bedel [Sun, 19 Apr 2015 12:30:00 +0000 (14:30 +0200)]
MIPS: ath79: Enable ZBOOT support

ZBOOT is working fine, so allow using it.

Signed-off-by: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9770/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS, IRQ: Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc
Jiang Liu [Wed, 20 May 2015 09:59:51 +0000 (17:59 +0800)]
MIPS, IRQ: Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc

Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc while we
already have a pointer to corresponding irq_desc.

Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Acked-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Yinghai Lu <yinghai@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: David Daney <david.daney@cavium.com>
Cc: Christoph Lameter <cl@linux.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86@kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-acpi@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10086/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Alchemy: Remove unneeded cast removing const
Krzysztof Kozlowski [Tue, 28 Apr 2015 04:46:23 +0000 (13:46 +0900)]
MIPS: Alchemy: Remove unneeded cast removing const

Parent names in clock init data is now array of const pointers to const
strings so the cast is not needed.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Barry Song <baohua@kernel.org>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: Chanwoo Choi <cw00.choi@samsung.com>
Cc: Inki Dae <inki.dae@samsung.com>
Patchwork: https://patchwork.linux-mips.org/patch/9903
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: tlbex.c: Remove new instance of __cpuinitdata that crept back in
Paul Gortmaker [Mon, 27 Apr 2015 22:47:59 +0000 (18:47 -0400)]
MIPS: tlbex.c: Remove new instance of __cpuinitdata that crept back in

We removed __cpuinit support (leaving no-op stubs) quite some time ago.
However a new instance was added in commit c5b367835cfc7a8ef53b9670a409ff
("MIPS: Add support for XPA.")

Since we want to clobber the stubs soon, get this removed now.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9894/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: c-r4k: Remove legacy __cpuinit section that crept in
Paul Gortmaker [Mon, 27 Apr 2015 22:47:57 +0000 (18:47 -0400)]
MIPS: c-r4k: Remove legacy __cpuinit section that crept in

We removed __cpuinit support (leaving no-op stubs) quite some time ago.
However a new instance was added in commit 4caa906ee949b7002cc1558bbe3744
("MIPS: mm: c-r4k: Build EVA {d,i}cache flushing functions")

Since we want to clobber the stubs soon, get this removed now.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9893/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BCM77xx: Remove legacy __cpuinit{,data} sections that crept in
Paul Gortmaker [Mon, 27 Apr 2015 22:47:56 +0000 (18:47 -0400)]
MIPS: BCM77xx: Remove legacy __cpuinit{,data} sections that crept in

We removed __cpuinit support (leaving no-op stubs) quite some time ago.
However a few more crept in as of commit 6ee1d93455384cef8a0426effe85da2
("MIPS: BCM47XX: Detect more then 128 MiB of RAM (HIGHMEM)")

Since we want to clobber the stubs soon, get this removed now.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9892/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: ATH25: Remove legacy __cpuinit section that crept in
Paul Gortmaker [Mon, 27 Apr 2015 22:47:55 +0000 (18:47 -0400)]
MIPS: ATH25: Remove legacy __cpuinit section that crept in

We removed __cpuinit support (leaving no-op stubs) quite some time ago.
However this one crept back in as of commit 43cc739fd98b8c517ad45756d869f
("MIPS: ath25: add common parts")

Since we want to clobber the stubs soon, get this removed now.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9891/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Pistachio: Enable USB PHY driver in defconfig
Andrew Bresticker [Tue, 7 Apr 2015 22:04:18 +0000 (15:04 -0700)]
MIPS: Pistachio: Enable USB PHY driver in defconfig

Update pistachio_defconfig to enable Pistachio's USB PHY driver.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hartley <james.hartley@imgtec.com>
Cc: Damien Horsley <Damien.Horsley@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9729/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoPHY: Add driver for Pistachio USB2.0 PHY
Andrew Bresticker [Tue, 7 Apr 2015 22:04:17 +0000 (15:04 -0700)]
PHY: Add driver for Pistachio USB2.0 PHY

Add a driver for the USB2.0 PHY found on the IMG Pistachio SoC.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hartley <james.hartley@imgtec.com>
Cc: Damien Horsley <Damien.Horsley@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9728/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agophy: Add binding document for Pistachio USB2.0 PHY
Andrew Bresticker [Tue, 7 Apr 2015 22:04:16 +0000 (15:04 -0700)]
phy: Add binding document for Pistachio USB2.0 PHY

Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hartley <james.hartley@imgtec.com>
Cc: Damien Horsley <Damien.Horsley@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9727/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Pistachio: Support 8250-based early printk
Ezequiel Garcia [Tue, 28 Apr 2015 22:08:35 +0000 (19:08 -0300)]
MIPS: Pistachio: Support 8250-based early printk

Pistachio SoCs are capable of early printk with generic 8250 support,
so let's select the options to enable it.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: James Hartley <james.hartley@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9913/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BMIPS: dts: Add uart device nodes to bcm7xxx platforms
Jaedon Shin [Fri, 8 May 2015 12:59:18 +0000 (21:59 +0900)]
MIPS: BMIPS: dts: Add uart device nodes to bcm7xxx platforms

Add two uart device nodes known as the uart1 and uart2 for the bcm7xxx
platforms.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9991/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BMIPS: Add support for Broadcom BCM97435SVMB
Florian Fainelli [Tue, 5 May 2015 01:10:57 +0000 (18:10 -0700)]
MIPS: BMIPS: Add support for Broadcom BCM97435SVMB

Add a DTS file and Kconfig entry for the BCM97435SVMB evaluation board
using bcm7435.dtsi as an example.

The current code needs some tweaking to allow us to use the
dual-threaded dual BMIPS5200 CPUs, so for now we limit ourselves to
allowing just a single CPU to be booted.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: blogic@openwrt.org
Cc: cernekee@chromium.org
Cc: Steven.Hill@imgtec.com
Patchwork: https://patchwork.linux-mips.org/patch/9972/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BMIPS: Add BCM7435 dtsi
Florian Fainelli [Tue, 5 May 2015 01:10:56 +0000 (18:10 -0700)]
MIPS: BMIPS: Add BCM7435 dtsi

Add the bare minimum required to boot a BCM7435-based system:

- BMIPS5200 CPU nodes
- Level 1 and 2 interrupt controllers
- UARTs
- EHCI/OHCI controllers

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: blogic@openwrt.org
Cc: cernekee@chromium.org
Cc: Steven.Hill@imgtec.com
Patchwork: https://patchwork.linux-mips.org/patch/9971/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BCM63xx: Utilize asm/bmips-spaces.h
Florian Fainelli [Mon, 4 May 2015 19:09:44 +0000 (12:09 -0700)]
MIPS: BCM63xx: Utilize asm/bmips-spaces.h

Since BCM63xx runs on BMIPS3300 which requires the use of a FIXADDR_TOP
to avoid collisions with the SBR, utilize asm/bmips-spaces.h which
defines FIXADDR_TOP for us now.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: blogic@openwrt.org
Cc: cernekee@chromium.org
Cc: jogo@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/9969/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BMIPS: Define BMIPS_FIXADDR_TOP in asm/bmips-spaces.h
Florian Fainelli [Mon, 4 May 2015 19:09:43 +0000 (12:09 -0700)]
MIPS: BMIPS: Define BMIPS_FIXADDR_TOP in asm/bmips-spaces.h

The FIXADDR_TOP value used by mach-bmips is in fact required whenever we
run on BMIPS3300 BMIPS CPUs, and is not machine, but CPU-specific, move
this constant to asm/bmips-spaces.h and use it in mach-bmips/spaces.h.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: blogic@openwrt.org
Cc: cernekee@chromium.org
Cc: jogo@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/9968/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMAINTAINERS: Add Broadcom BCM47xx entry
Rafał Miłecki [Fri, 29 May 2015 05:39:26 +0000 (07:39 +0200)]
MAINTAINERS: Add Broadcom BCM47xx entry

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Cc: Arend van Spriel <arend@broadcom.com>
Patchwork: https://patchwork.linux-mips.org/patch/10207/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: ingenic: Initial MIPS Creator CI20 support
Paul Burton [Sun, 24 May 2015 15:11:47 +0000 (16:11 +0100)]
MIPS: ingenic: Initial MIPS Creator CI20 support

Add an initial device tree for the Ingenic JZ4780 based MIPS Creator
CI20 board.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10162/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: ingenic: Initial JZ4780 support
Paul Burton [Sun, 24 May 2015 15:11:46 +0000 (16:11 +0100)]
MIPS: ingenic: Initial JZ4780 support

Support the Ingenic JZ4780 SoC using the existing code under
arch/mips/jz4740 now that it has been generalised sufficiently.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Joshua Kinard <kumba@gentoo.org>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/10164/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: use Ingenic SoC UART driver
Paul Burton [Sun, 24 May 2015 15:11:45 +0000 (16:11 +0100)]
MIPS: JZ4740: use Ingenic SoC UART driver

Remove the serial support from arch/mips/jz4740 & make use of the new
Ingenic SoC UART driver. This is done for both regular & early console
output.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Apelete Seketeli <apelete@seketeli.net>
Cc: Alexandre Courbot <gnurou@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10160/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoserial: 8250_ingenic: support for Ingenic SoC UARTs
Paul Burton [Sun, 24 May 2015 15:11:44 +0000 (16:11 +0100)]
serial: 8250_ingenic: support for Ingenic SoC UARTs

Introduce a driver suitable for use with the UARTs present in
Ingenic SoCs such as the JZ4740 & JZ4780. These are described as being
ns16550 compatible but aren't quite - they require the setting of an
extra bit in the FCR register to enable the UART module. The serial_out
implementation is the same as that in arch/mips/jz4740/serial.c - which
will shortly be removed.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jslaby@suse.cz>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-serial@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Cc: Peter Hurley <peter@hurleysoftware.com>
Cc: Alan Cox <alan@linux.intel.com>
Cc: linux-kernel@vger.kernel.org
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: John Crispin <blogic@openwrt.org>
Patchwork: https://patchwork.linux-mips.org/patch/10159/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agodevicetree: document Ingenic SoC UART binding
Paul Burton [Sun, 24 May 2015 15:11:43 +0000 (16:11 +0100)]
devicetree: document Ingenic SoC UART binding

Add binding documentation for the UARTs found in Ingenic SoCs.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10161/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: only detect RAM size if not specified in DT
Paul Burton [Sun, 24 May 2015 15:11:42 +0000 (16:11 +0100)]
MIPS: JZ4740: only detect RAM size if not specified in DT

Allow a devicetree to specify the memory present in the system rather
than probing it from the memory controller. This both saves the probing
for systems where the amount of memory is fixed, and will simplify the
bringup of later Ingenic SoCs where the memory controller register
layout differs.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10163/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: remove clock.h
Paul Burton [Sun, 24 May 2015 15:11:41 +0000 (16:11 +0100)]
MIPS: JZ4740: remove clock.h

The only thing remaining in arch/mips/jz4740/clock.h is declarations of
the jz4740_clock_{suspend,resume} functions. Move these to
arch/mips/include/asm/mach-jz4740/clock.h for consistency with similar
functions, and remove the redundant arch/mips/jz4740/clock.h header.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10156/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoclk: ingenic: add JZ4780 CGU support
Paul Burton [Sun, 24 May 2015 15:11:40 +0000 (16:11 +0100)]
clk: ingenic: add JZ4780 CGU support

Add support for the clocks provided by the CGU in the Ingenic JZ4780
SoC, making use of the SoC-agnostic CGU code to do the heavy lifting.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Co-authored-by: Paul Cercueil <paul@crapouillou.net>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10157/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS, clk: move jz4740 clock suspend, resume functions to jz4740-cgu
Paul Burton [Sun, 24 May 2015 15:11:39 +0000 (16:11 +0100)]
MIPS, clk: move jz4740 clock suspend, resume functions to jz4740-cgu

The jz4740-cgu driver already has access to the CGU, so it makes sense
to move the few remaining accesses to the CGU from arch/mips/jz4740
there too. Move the jz4740_clock_{suspend,resume} functions there for
such consistency. The arch/mips/jz4740/clock.c file now contains nothing
more of use & so is removed.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10158/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS, clk: move jz4740 UDC auto suspend functions to jz4740-cgu
Paul Burton [Sun, 24 May 2015 15:11:38 +0000 (16:11 +0100)]
MIPS, clk: move jz4740 UDC auto suspend functions to jz4740-cgu

The jz4740-cgu driver already has access to the CGU, so it makes sense
to move the few remaining accesses to the CGU from arch/mips/jz4740
there too. Move the jz4740_clock_udc_{dis,en}able_auto_suspend functions
there for such consistency.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10154/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu
Paul Burton [Sun, 24 May 2015 15:11:37 +0000 (16:11 +0100)]
MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu

The jz4740-cgu driver already has access to the CGU, so it makes sense
to move the few remaining accesses to the CGU from arch/mips/jz4740
there too. Move jz4740_clock_set_wait_mode for such consistency.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10153/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS,clk: migrate JZ4740 to common clock framework
Paul Burton [Sun, 24 May 2015 15:11:36 +0000 (16:11 +0100)]
MIPS,clk: migrate JZ4740 to common clock framework

Migrate the JZ4740 & the qi_lb60 board to use common clock framework
via the new Ingenic SoC CGU driver. Note that the JZ4740-specific
debugfs code is removed since common clock framework provides its own
debug capabilities.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Co-authored-by: Paul Cercueil <paul@crapouillou.net>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Fabian Frederick <fabf@skynet.be>
Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10151/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoclk: ingenic: add driver for Ingenic SoC CGU clocks
Paul Burton [Sun, 24 May 2015 15:11:35 +0000 (16:11 +0100)]
clk: ingenic: add driver for Ingenic SoC CGU clocks

This driver supports the CGU clocks for Ingenic SoCs. It is generic
enough to be usable across at least the JZ4740 to the JZ4780, and will
be made use of on such devices in subsequent commits. This patch by
itself only adds the SoC-agnostic infrastructure that forms the bulk of
the CGU driver for the aforementioned further commits to make use of.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Co-authored-by: Paul Cercueil <paul@crapouillou.net>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10150/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoDEVICETREE: Add Ingenic CGU binding documentation
Paul Burton [Sun, 24 May 2015 15:11:34 +0000 (16:11 +0100)]
DEVICETREE: Add Ingenic CGU binding documentation

Document the devicetree binding for Ingenic SoC CGUs, and add headers
defining the clock specifiers for clocks provided by the JZ4740 & JZ4780
CGU blocks.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10152/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: replace use of jz4740_clock_bdata
Paul Burton [Sun, 24 May 2015 15:11:33 +0000 (16:11 +0100)]
MIPS: JZ4740: replace use of jz4740_clock_bdata

Replace uses of the jz4740_clock_bdata struct with calls to clk_get_rate
for the appropriate clock. This is in preparation for migrating the
clocks towards common clock framework & devicetree.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Cc: Apelete Seketeli <apelete@seketeli.net>
Patchwork: https://patchwork.linux-mips.org/patch/10149/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: Call jz4740_clock_init earlier
Paul Burton [Sun, 24 May 2015 15:11:32 +0000 (16:11 +0100)]
MIPS: JZ4740: Call jz4740_clock_init earlier

Call jz4740_clock_init before any uses of jz4740_clock_bdata occur. This
is in preparation for replacing uses of that struct with calls to
clk_get_rate, which will allow the clocks to be migrated towards common
clock framework & devicetree.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10148/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS/IRQCHIP: Move Ingenic SoC intc driver to drivers/irqchip
Paul Burton [Sun, 24 May 2015 15:11:31 +0000 (16:11 +0100)]
MIPS/IRQCHIP: Move Ingenic SoC intc driver to drivers/irqchip

Move the driver for Ingenic SoC interrupt controllers into
drivers/irqchip where it belongs.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10147/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: support newer SoC interrupt controllers
Paul Burton [Sun, 24 May 2015 15:11:30 +0000 (16:11 +0100)]
MIPS: JZ4740: support newer SoC interrupt controllers

Allow the interrupt controllers of the JZ4770, JZ4775 & JZ4780 SoCs to
be probed via devicetree, supporting the 64 interrupts they provide.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10155/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: Avoid JZ4740-specific naming
Paul Burton [Sun, 24 May 2015 15:11:29 +0000 (16:11 +0100)]
MIPS: JZ4740: Avoid JZ4740-specific naming

Rename the functions including jz4740 in their names to be more generic
in preparation for supporting further SoCs, and for moving this
interrupt controller code to drivers/irqchip.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Patchwork: https://patchwork.linux-mips.org/patch/10146/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: read intc base address from DT
Paul Burton [Sun, 24 May 2015 15:11:28 +0000 (16:11 +0100)]
MIPS: JZ4740: read intc base address from DT

Read the base address of the SoC interrupt controller from the device
tree rather than relying upon the JZ4740_INTC_BASE_ADDR macro, in order
to remove the dependency on the asm/mach-jz4740/base.h header.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10145/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: define IRQ numbers based on number of intc IRQs
Paul Burton [Sun, 24 May 2015 15:11:27 +0000 (16:11 +0100)]
MIPS: JZ4740: define IRQ numbers based on number of intc IRQs

For interrupts numbered after those of the interrupt controller, define
their numbers based upon the number of interrupts provided by the SoC
interrupt controller. This is in preparation for supporting newer
Ingenic SoCs which provide more interrupts.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10143/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: support >32 interrupts
Paul Burton [Sun, 24 May 2015 15:11:26 +0000 (16:11 +0100)]
MIPS: JZ4740: support >32 interrupts

On newer Ingenic SoCs the interrupt controller supports more than 32
interrupts, which it does by duplicating the registers at intervals
of 0x20 bytes within its address space. Add support for an arbitrary
number of interrupts using multiple generic chips, and provide the
number of chips to register from the interrupt controller probe
function.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10141/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: Remove jz_intc_base global
Paul Burton [Sun, 24 May 2015 15:11:25 +0000 (16:11 +0100)]
MIPS: JZ4740: Remove jz_intc_base global

Avoid the need for the global variable jz_intc_base by introducing a
struct ingenic_intc_data and passing it around as the IRQ handler data.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10144/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: drop intc debugfs code
Paul Burton [Sun, 24 May 2015 15:11:24 +0000 (16:11 +0100)]
MIPS: JZ4740: drop intc debugfs code

The debugfs code becomes a nuisance when attempting to avoid globals,
since the interrupt controller probe function run too early for it to be
safe to create the debugfs files. Drop it.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10139/
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: register an irq_domain for the interrupt controller
Paul Burton [Sun, 24 May 2015 15:11:23 +0000 (16:11 +0100)]
MIPS: JZ4740: register an irq_domain for the interrupt controller

When probing the interrupt controller, register an IRQ domain such
that the interrupts can be translated by devicetree code & thus used
from devicetree.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10140/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT
Paul Burton [Sun, 24 May 2015 15:11:22 +0000 (16:11 +0100)]
MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT

Rather than hardcoding the IRQ number used to cascade interrupts from
the SoC interrupt controller to the CPU interrupt controller, read that
IRQ number from the DT describing the system.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10137/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: probe interrupt controller via DT
Paul Burton [Sun, 24 May 2015 15:11:21 +0000 (16:11 +0100)]
MIPS: JZ4740: probe interrupt controller via DT

Declare the JZ4740 interrupt controller for probe via DT using the
standard irqchip_init function, and make use of that function to probe
the controller by adding the appropriate node to the JZ4740 dtsi.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10135/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agodevicetree: document Ingenic SoC interrupt controller binding
Paul Burton [Sun, 24 May 2015 15:11:20 +0000 (16:11 +0100)]
devicetree: document Ingenic SoC interrupt controller binding

Add binding documentation for Ingenic SoC interrupt controllers.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10134/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: Move arch_init_irq out of arch/mips/jz4740/irq.c
Paul Burton [Sun, 24 May 2015 15:11:19 +0000 (16:11 +0100)]
MIPS: JZ4740: Move arch_init_irq out of arch/mips/jz4740/irq.c

In preparation for moving the JZ4740 interrupt controller driver to
drivers/irqchip, move arch_init_irq into setup.c such that everything
remaining in irq.c is related to said JZ4740 interrupt controller.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10136/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: use generic plat_irq_dispatch
Paul Burton [Sun, 24 May 2015 15:11:18 +0000 (16:11 +0100)]
MIPS: JZ4740: use generic plat_irq_dispatch

Make use of the generic plat_irq_dispatch function introduced by commit
85f7cdacbb81 "MIPS: Provide a generic plat_irq_dispatch", in order to
reduce unnecessary code duplication.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10138/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: probe CPU interrupt controller via DT
Paul Burton [Sun, 24 May 2015 22:37:42 +0000 (23:37 +0100)]
MIPS: JZ4740: probe CPU interrupt controller via DT

Use the generic irqchip_init function to probe irqchip drivers using DT,
and add the appropriate node to the JZ4740 devicetree in place of the
call to mips_cpu_irq_init.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Patchwork: https://patchwork.linux-mips.org/patch/10166/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoIRQCHIP: irq_cpu: declare irqchip table entry
Paul Burton [Sun, 24 May 2015 15:11:16 +0000 (16:11 +0100)]
IRQCHIP: irq_cpu: declare irqchip table entry

Allow the MIPS CPU interrupt controller to be probed from DT using the
generic __irqchip_of_table for platforms which use irqchip_init. This
will avoid such platforms needing to duplicate the compatible string &
init function pointer.

[ralf@linux-mips.org: Resolved conflict due the preceeding commit that
moves irq-cpu.c.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: linux-kernel@vger.kernel.org
Cc: Felix Fietkau <nbd@openwrt.org>
Patchwork: https://patchwork.linux-mips.org/patch/10131/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS/IRQCHIP: Move irq_chip from arch/mips to drivers/irqchip.
Ralf Baechle [Tue, 26 May 2015 16:20:06 +0000 (18:20 +0200)]
MIPS/IRQCHIP: Move irq_chip from arch/mips to drivers/irqchip.

While at it, rename it because in drivers/irqchip no longer every CPU is
a MIPS.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: require & include DT
Paul Burton [Sun, 24 May 2015 15:11:15 +0000 (16:11 +0100)]
MIPS: JZ4740: require & include DT

Require a DT for JZ4740 based systems, and add a stub one for the
qi_lb60 (Ben NanoNote) board. Devices will be migrated to being probed
via this DT over time.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10132/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: ingenic: Add newer vendor IDs
Paul Burton [Sun, 24 May 2015 15:11:14 +0000 (16:11 +0100)]
MIPS: ingenic: Add newer vendor IDs

Ingenic have actually varied the vendor/company ID of the XBurst cores
across their range of SoCs, whilst keeping the product ID & revision
constant... Add definitions for vendor IDs known to be used in some of
Ingenic's newer SoCs, and handle them in the same way as the existing
Ingenic vendor ID from the JZ4740.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Co-authored-by: Paul Cercueil <paul@crapouillou.net>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Joshua Kinard <kumba@gentoo.org>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-kernel@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/10128/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: JZ4740: introduce CONFIG_MACH_INGENIC
Paul Burton [Sun, 24 May 2015 15:11:13 +0000 (16:11 +0100)]
MIPS: JZ4740: introduce CONFIG_MACH_INGENIC

In preparation for supporting Ingenic SoCs other than the JZ4740,
introduce MACH_INGENIC to Kconfig & move MACH_JZ4740 to a separate
entry selected by the board when appropriate. This allows MACH_INGENIC
to be used to enable things generic across Ingenic SoCs.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Andrew Bresticker <abrestic@chromium.org>
Patchwork: https://patchwork.linux-mips.org/patch/10130/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agodevicetree/bindings: add Qi Hardware vendor prefix
Paul Burton [Sun, 24 May 2015 15:11:12 +0000 (16:11 +0100)]
devicetree/bindings: add Qi Hardware vendor prefix

Define a vendor prefix for Qi Hardware, creators of the Ben Nanonote
(qi_lb60) among other open devices.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Hayato Suzuki <hytszk@gmail.com>
Cc: Thierry Reding <treding@nvidia.com>
Cc: linux-kernel@vger.kernel.org
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Cc: Arnaud Ebalard <arno@natisbad.org>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Antony Pavlov <antonynpavlov@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10142/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agodevicetree/bindings: add Ingenic Semiconductor vendor prefix
Paul Burton [Sun, 24 May 2015 15:11:11 +0000 (16:11 +0100)]
devicetree/bindings: add Ingenic Semiconductor vendor prefix

Define a vendor prefix for Ingenic Semiconductor, a vendor of MIPS-based
SoCs. Simply use 'ingenic'.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Hayato Suzuki <hytszk@gmail.com>
Cc: Thierry Reding <treding@nvidia.com>
Cc: linux-kernel@vger.kernel.org
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Cc: Arnaud Ebalard <arno@natisbad.org>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Antony Pavlov <antonynpavlov@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10129/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: DEC: Update CPU overrides
Maciej W. Rozycki [Wed, 27 May 2015 13:15:31 +0000 (14:15 +0100)]
MIPS: DEC: Update CPU overrides

Update CPU overrides for the DEC port with the recent additions, shaving
off some effectively dead code:

   text    data      bss      dec     hex filename
5586952  233132  5990368 11810452  b43694 vmlinux.32-old
5581248  233140  5990368 11804756  b42054 vmlinux.32-new

   text    data      bss      dec     hex filename
6036936  356648 10756544 17150128 105b0b0 vmlinux.64-old
6029896  360752 10756544 17147192 105a538 vmlinux.64-new

The data size increase is due to the special alignment requirement of
`init_thread_union' aka `.data..init_task' moving it up to the nearest
page boundary and making the amount of padding at its front rely on how
far within a page text ends.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10197/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: netlogic: remove unnecessary MTD partition probe specification
Brian Norris [Mon, 18 May 2015 23:21:12 +0000 (16:21 -0700)]
MIPS: netlogic: remove unnecessary MTD partition probe specification

The cmdlinepart parser is already supported in the default probe.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: linux-mtd@lists.infradead.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10071/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation
Maciej W. Rozycki [Wed, 27 May 2015 13:15:20 +0000 (14:15 +0100)]
MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation

Replace an explicit barrier with a useful processor instruction in TLB
invalidation, following several other such cases elsewhere in
`tlb-r3k.c'.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10196/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: tlb-r3k: Move CP0.Wired register initialisation to `tlb_init'
Maciej W. Rozycki [Wed, 27 May 2015 13:15:15 +0000 (14:15 +0100)]
MIPS: tlb-r3k: Move CP0.Wired register initialisation to `tlb_init'

Move the initialisation of the CP0.Wired register implemented by Toshiba
TX3922 and TX3927 processors from `tx39_cache_init' to `tlb_init' where
it belongs, correcting code structure and making sure initialisation
does not rely on `tx39_cache_init' being called before `tlb_init' to
work correctly.

Make `r3k_have_wired_reg' static as it's no longer externally referred
to; remove a stale declaration too.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10195/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: tlb-r3k: Also invalidate wired TLB entries on boot
Maciej W. Rozycki [Wed, 27 May 2015 13:15:08 +0000 (14:15 +0100)]
MIPS: tlb-r3k: Also invalidate wired TLB entries on boot

Most R3k processor implementations have their 8 first TLB entries fixed
as wired, so we always skip them in TLB invalidation.  That however
means any leftover entries present there at boot will stay throughout
the life of the kernel, unless replaced with new ones.

So rename `local_flush_tlb_all' to `local_flush_tlb_from' and make it
accept the TLB entry to start from.  Then use 0 initially at bootstrap,
and the first regular entry later on, bypassing any wired entries.
Wrap the latter arrangement into a new `local_flush_tlb_all' entry
point.

There is no need to disable interrupts in the call made from `tlb_init'
because it's made before the interrupt subsystem has been initialised;
this is also true for secondary processors, should we ever support R3k
SMP.  So move this piece of code to new `local_flush_tlb_all'.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10194/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: dump_tlb: Take XPA into account
James Hogan [Tue, 19 May 2015 08:50:38 +0000 (09:50 +0100)]
MIPS: dump_tlb: Take XPA into account

XPA extends the physical addresses on MIPS32, including the EntryLo
registers. Update dump_tlb() to concatenate the PFNX field from the high
end of the EntryLo registers (as read by mfhc0).

The width of physical and virtual addresses are also separated to show
only 8 nibbles of virtual but 11 nibbles of physical with XPA.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10077/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: dump_tlb: Take RI/XI bits into account
James Hogan [Tue, 19 May 2015 08:50:37 +0000 (09:50 +0100)]
MIPS: dump_tlb: Take RI/XI bits into account

The RI/XI bits when present are above the PFN field in the EntryLo
registers, at bits 63,62 when read with dmfc0, and bits 31,30 when read
with mfc0. This makes them appear as part of the physical address, since
the other bits are masked with PAGE_MASK, for example:

Index: 253 pgmask=16kb va=77b18000 asid=75
        [pa=1000744000 c=5 d=1 v=1 g=0] [pa=100134c000 c=5 d=1 v=1 g=0]

The physical addresses have bit 36 set, which corresponds to bit 30 of
EntryLo1, the XI bit.

Explicitly mask off the RI and XI bits from the printed physical
address, and print the RI and XI bits separately if they exist, giving
output more like this:

Index: 226 pgmask=16kb va=77be0000 asid=79
        [ri=0 xi=1 pa=01288000 c=5 d=1 v=1 g=0] [ri=0 xi=0 pa=010e4000 c=5 d=0 v=1 g=0]

Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: David Daney <ddaney@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/10080/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: dump_tlb: Take EHINV bit into account
James Hogan [Tue, 19 May 2015 08:50:36 +0000 (09:50 +0100)]
MIPS: dump_tlb: Take EHINV bit into account

The EHINV bit in EntryHi allows a TLB entry to be properly marked
invalid so that EntryHi doesn't have to be set to a unique value to
avoid machine check exceptions due to multiple matching entries.

Unfortunately dump_tlb() doesn't take this into account so it will print
all the uninteresting invalid TLB entries if the current ASID happens to
be 00. Therefore add a condition to skip entries which are marked
invalid with the EHINV bit.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10076/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: dump_tlb: Take global bit into account
James Hogan [Tue, 19 May 2015 08:50:35 +0000 (09:50 +0100)]
MIPS: dump_tlb: Take global bit into account

The TLB only matches the ASID when the global bit isn't set, so
dump_tlb() shouldn't really be skipping global entries just because the
ASID doesn't match. Fix the condition to read the TLB entry's global bit
from EntryLo0. Note that after a TLB read the global bits in both
EntryLo registers reflect the same global bit in the TLB entry.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10079/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: dump_tlb: Make use of EntryLo bit definitions
James Hogan [Tue, 19 May 2015 08:50:34 +0000 (09:50 +0100)]
MIPS: dump_tlb: Make use of EntryLo bit definitions

Make use of recently added EntryLo bit definitions in mipsregs.h when
dumping TLB contents.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10075/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: dump_tlb: Refactor TLB matching
James Hogan [Tue, 19 May 2015 08:50:33 +0000 (09:50 +0100)]
MIPS: dump_tlb: Refactor TLB matching

Refactor the TLB matching code in dump_tlb() slightly so that the
conditions which can cause a TLB entry to be skipped can be more easily
extended. This should prevent the match condition getting unwieldy once
it is updated to take further conditions into account.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10081/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: dump_tlb: Use tlbr hazard macros
James Hogan [Tue, 19 May 2015 08:50:32 +0000 (09:50 +0100)]
MIPS: dump_tlb: Use tlbr hazard macros

Use the new tlb read hazard macros from <asm/hazards.h> rather than the
local BARRIER() macro which uses 7 ops regardless of the kernel
configuration.

We use mtc0_tlbr_hazard for the hazard between mtc0 to the index
register and the tlbr, and tlb_read_hazard for the hazard between the
tlbr and the mfc0 of the TLB registers written by tlbr.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10074/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: mipsregs.h: Add EntryLo bit definitions
James Hogan [Tue, 19 May 2015 08:50:31 +0000 (09:50 +0100)]
MIPS: mipsregs.h: Add EntryLo bit definitions

Add definitions for EntryLo register bits in mipsregs.h. The R4000
compatible ones are prefixed MIPS_ENTRYLO_ and the R3000 compatible ones
are prefixed R3K_ENTRYLO_.

These will be used in later patches.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/10073/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: hazards: Add hazard macros for tlb read
James Hogan [Tue, 19 May 2015 08:50:30 +0000 (09:50 +0100)]
MIPS: hazards: Add hazard macros for tlb read

Add hazard macros to <asm/hazards.h> for the following hazards around
tlbr (TLB read) instructions, which are used in TLB dumping code and
some KVM TLB management code:

- mtc0_tlbr_hazard
  Between mtc0 (Index) and tlbr. This is copied from mtc0_tlbw_hazard in
  all cases on the assumption that tlbr always has similar data user
  timings to tlbw.

- tlb_read_hazard
  Between tlbr and mfc0 (various TLB registers). This is copied from
  tlbw_use_hazard in all cases on the assumption that tlbr has similar
  data writer characteristics to tlbw, and mfc0 has similar data user
  characteristics to loads and stores.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10078/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Add SysRq operation to dump TLBs on all CPUs
James Hogan [Tue, 19 May 2015 08:50:29 +0000 (09:50 +0100)]
MIPS: Add SysRq operation to dump TLBs on all CPUs

Add a MIPS specific SysRq operation to dump the TLB entries on all CPUs,
using the 'x' trigger key.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10072/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: traps: print Exception Code in __show_regs()
Petri Gynther [Fri, 8 May 2015 22:10:10 +0000 (15:10 -0700)]
MIPS: traps: print Exception Code in __show_regs()

Print Exception Code when printing the Cause register.

Signed-off-by: Petri Gynther <pgynther@google.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9998/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BCM47xx: Read board info for all bcma buses
Rafał Miłecki [Tue, 12 May 2015 11:05:18 +0000 (13:05 +0200)]
MIPS: BCM47xx: Read board info for all bcma buses

Extra bcma buses may be totally different models, see following dump:
boardtype=0x0646
pci/1/1/boardtype=0x0545
pci/2/1/boardtype=0x62b
We need to detect them properly to allow drivers apply some board
specific hacks.

[ralf@linux-mips.org: folded in Rafal's fix.]

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: https://patchwork.linux-mips.org/patch/10028/
Patchwork: https://patchwork.linux-mips.org/patch/10048/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BCM47xx: Extract info about et2 interface
Rafał Miłecki [Tue, 12 May 2015 09:54:48 +0000 (11:54 +0200)]
MIPS: BCM47xx: Extract info about et2 interface

New devices may have more than 1 Ethernet core (device). We should
extract info about them to make it available to Ethernet drivers.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Hante Meuleman <meuleman@broadcom.com>
Cc: Ian Kent <raven@themaw.net>
Patchwork: https://patchwork.linux-mips.org/patch/10027/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BCM47xx: Extract all boardflags to new u32 fields
Rafał Miłecki [Tue, 12 May 2015 09:31:02 +0000 (11:31 +0200)]
MIPS: BCM47xx: Extract all boardflags to new u32 fields

For years we planned to get rid of old u16 fields, let's start doing it
with MIPS code. This process will take some time, it requires doing the
same in ssb/bcma and then switching all drivers to new fields. This will
be handled in separated patches submitted to appropriate trees.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: https://patchwork.linux-mips.org/patch/10026/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BCM47XX: Simplify function looking for NVRAM entry
Rafał Miłecki [Tue, 12 May 2015 16:46:12 +0000 (18:46 +0200)]
MIPS: BCM47XX: Simplify function looking for NVRAM entry

First of all it shouldn't modify copied NVRAM just to make sure it can
loop over all entries. It's enough to just compare current position
pointer with the end of buffer address.
Secondly buffer is guaranteed to be \0 ended, so we don't need strnchr.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Hante Meuleman <meuleman@broadcom.com>
Cc: Ian Kent <raven@themaw.net>
Patchwork: https://patchwork.linux-mips.org/patch/10032/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: BCM47XX: Make sure NVRAM buffer ends with \0
Rafał Miłecki [Tue, 12 May 2015 16:46:11 +0000 (18:46 +0200)]
MIPS: BCM47XX: Make sure NVRAM buffer ends with \0

This will simplify reading its contents.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Hante Meuleman <meuleman@broadcom.com>
Cc: Ian Kent <raven@themaw.net>
Patchwork: https://patchwork.linux-mips.org/patch/10031/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: Malta: Make maltasmvp_defconfig useful again.
Ralf Baechle [Wed, 6 May 2015 11:09:54 +0000 (12:09 +0100)]
MIPS: Malta: Make maltasmvp_defconfig useful again.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMIPS: ftrace: Enable support for syscall tracepoints.
Ralf Baechle [Fri, 6 Sep 2013 18:24:48 +0000 (20:24 +0200)]
MIPS: ftrace: Enable support for syscall tracepoints.

All the necessary support code is already there so all that's left is
to enable the feature in kconfig.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoLinux 4.1-rc8
Linus Torvalds [Mon, 15 Jun 2015 01:51:10 +0000 (15:51 -1000)]
Linux 4.1-rc8

9 years agoMerge branch 'fixes' of git://git.infradead.org/users/vkoul/slave-dma
Linus Torvalds [Mon, 15 Jun 2015 01:48:26 +0000 (15:48 -1000)]
Merge branch 'fixes' of git://git.infradead.org/users/vkoul/slave-dma

Pull dmaengine fixes from Vinod Koul:
 "Here are hopefully last set of fixes for 4.1. This time we have:

   - fixing pause capability reporting on both dmaengine pause & resume
     support by Krzysztof

   - locking fix fir at_xdmac by Ludovic

   - slave configuration fix for at_xdmac by Ludovic"

* 'fixes' of git://git.infradead.org/users/vkoul/slave-dma:
  dmaengine: Fix choppy sound because of unimplemented resume
  dmaengine: at_xdmac: rework slave configuration part
  dmaengine: at_xdmac: lock fixes

9 years agoMerge tag 'ntb-4.1' of git://github.com/jonmason/ntb
Linus Torvalds [Mon, 15 Jun 2015 01:46:43 +0000 (15:46 -1000)]
Merge tag 'ntb-4.1' of git://github.com/jonmason/ntb

Pull NTB fixes from Jon Mason:
 "I apologize for the tardiness of this request.  Here are a couple of
  last minute NTB bug fixes for v4.1:

  NTB bug fixes to address issues in unmapping the MW reg base and
  vbase, and an uninitialized variable on Atom platforms"

* tag 'ntb-4.1' of git://github.com/jonmason/ntb:
  ntb: initialize max_mw for Atom before using it
  ntb: iounmap MW reg and vbase in error path

9 years agoMerge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Linus Torvalds [Mon, 15 Jun 2015 01:38:57 +0000 (15:38 -1000)]
Merge branch 'upstream' of git://git.linux-mips.org/ralf/upstream-linus

Pull more MIPS fixes from Ralf Baechle:
 "Another round of 4.1 MIPS fixes, one fix to a MIPS-specific #if
  condition in lib/mpi, one fix to the MIPS GIC irqchip driver and one
  SSB fix.

  Details:
   - fix handling of clock in chipco SSB driver.
   - fix two MIPS-specific #if conditions to correctly work for GCC 5.1.
   - fix damage to R6 pgtable bits done by XPA support.
   - fix possible crash due to unloading modules that contain statically
     defined platform devices.
   - fix disabling of the MSA ASE on context switch to also work
     correctly when a new thread/process has the CPU for the very first
     time.

  This is part of linux-next and has been beaten to death on
  Imagination's test farm.

  While things are not looking too grim this pull request also means the
  rate of fixes for 4.1 remains nearly constant so I'd not be unhappy if
  you'd delay the release"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MPI: MIPS: Fix compilation error with GCC 5.1
  IRQCHIP: mips-gic: Don't nest calls to do_IRQ()
  MIPS: MSA: bugfix - disable MSA correctly for new threads/processes.
  MIPS: Loongson: Do not register 8250 platform device from module.
  MIPS: Cobalt: Do not build MTD platform device registration code as module.
  SSB: Fix handling of ssb_pmu_get_alp_clock()
  MIPS: pgtable-bits: Fix XPA damage to R6 definitions.

9 years agoMerge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Mon, 15 Jun 2015 00:53:02 +0000 (14:53 -1000)]
Merge branch 'irq-urgent-for-linus' of git://git./linux/kernel/git/tip/tip

Pull irqchip fix from Thomas Gleixner:
 "A single fix for an off by one bug in the sunxi irqchip driver"

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip: sunxi-nmi: Fix off-by-one error in irq iterator

9 years agoMerge branch 'locking-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Mon, 15 Jun 2015 00:03:11 +0000 (14:03 -1000)]
Merge branch 'locking-urgent-for-linus' of git://git./linux/kernel/git/tip/tip

Pull lockdep fix from Ingo Molnar:
 "A lockdep/modules unload race fix that can oops"

* 'locking-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  lockdep: Fix a race between /proc/lock_stat and module unload

9 years agoMerge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Mon, 15 Jun 2015 00:00:13 +0000 (14:00 -1000)]
Merge branch 'perf-urgent-for-linus' of git://git./linux/kernel/git/tip/tip

Pull perf fixes from Ingo Molnar:
 "A regression fix for a crash, and a Intel HSW uncore PMU driver fix"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  Revert "perf/x86/intel/uncore: Move uncore_box_init() out of driver initialization"
  perf/x86/intel/uncore: Fix CBOX bit wide and UBOX reg on Haswell-EP

9 years agoMerge tag 'sound-4.1-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai...
Linus Torvalds [Sun, 14 Jun 2015 23:55:24 +0000 (13:55 -1000)]
Merge tag 'sound-4.1-rc8' of git://git./linux/kernel/git/tiwai/sound

Pull sound fixes from Takashi Iwai:
 "Most of commits are regression fixes for HD-audio: a few corner case
  fixes for regmap transition, and i915 binding issues.

  In addition, a quirk for another USB-audio device supporting DSD"

* tag 'sound-4.1-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound:
  ALSA: hda - Abort the probe without i915 binding for HSW/BDW
  ALSA: hda - Re-add the lost fake mute support
  ALSA: hda - Continue probing even if i915 binding fails
  ALSA: hda - Don't actually write registers for caps overwrites
  ALSA: hda - fix number of devices query on hotplug
  ALSA: usb-audio: add native DSD support for JLsounds I2SoverUSB

9 years agoMPI: MIPS: Fix compilation error with GCC 5.1
Jaedon Shin [Fri, 12 Jun 2015 09:04:14 +0000 (18:04 +0900)]
MPI: MIPS: Fix compilation error with GCC 5.1

This patch fixes mips compilation error:

lib/mpi/generic_mpih-mul1.c: In function 'mpihelp_mul_1':
lib/mpi/longlong.h:651:2: error: impossible constraint in 'asm'

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/10546/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoIRQCHIP: mips-gic: Don't nest calls to do_IRQ()
Rabin Vincent [Fri, 12 Jun 2015 08:01:56 +0000 (10:01 +0200)]
IRQCHIP: mips-gic: Don't nest calls to do_IRQ()

The GIC chained handlers use do_IRQ() to call the subhandlers.  This
means that irq_enter() calls get nested, which leads to preempt count
looking like we're in nested interrupts, which in turn leads to all
system time being accounted as IRQ time in account_system_time().

Fix it by using generic_handle_irq().  Since these same functions are
used in some systems (if cpu_has_veic) from a low-level vectored
interrupt handler which does not go throught do_IRQ(), we need to do it
conditionally.

Signed-off-by: Rabin Vincent <rabin.vincent@axis.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Patchwork: https://patchwork.linux-mips.org/patch/10545/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
9 years agoMerge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Linus Torvalds [Sat, 13 Jun 2015 06:54:16 +0000 (20:54 -1000)]
Merge git://git./linux/kernel/git/davem/net

Pull networking fixes from David Miller:

 1) Fix uninitialized struct station_info in cfg80211_wireless_stats(),
    from Johannes Berg.

 2) Revert commit attempt to fix ipv6 protocol resubmission, it adds
    regressions.

 3) Endless loops can be created in bridge port lists, fix from Nikolay
    Aleksandrov.

 4) Don't WARN_ON() if sk->sk_forward_alloc is non-zero in
    sk_clear_memalloc, it is a legal situation during swap deactivation.
    Fix from Mel Gorman.

 5) Fix order of disabling interrupts and unlocking NAPI in enic driver
    to avoid a race.  From Govindarajulu Varadarajan.

 6) High and low register writes are swapped when programming the start
    of periodic output in igb driver.  From Richard Cochran.

 7) Fix device rename handling in mpls stack, from Robert Shearman.

 8) Do not trigger compaction synchronously when optimistically trying
    to allocate an order 3 page in alloc_skb_with_frags() and
    skb_page_frag_refill().  From Shaohua Li.

 9) Authentication with COOKIE_ECHO is not handled properly in SCTP, fix
    from Marcelo Ricardo Leitner.

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net:
  Doc: networking: Fix URL for wiki.wireshark.org in udplite.txt
  sctp: allow authenticating DATA chunks that are bundled with COOKIE_ECHO
  net: don't wait for order-3 page allocation
  mpls: handle device renames for per-device sysctls
  net: igb: fix the start time for periodic output signals
  enic: fix memory leak in rq_clean
  enic: check return value for stat dump
  enic: unlock napi busy poll before unmasking intr
  net, swap: Remove a warning and clarify why sk_mem_reclaim is required when deactivating swap
  bridge: fix multicast router rlist endless loop
  tipc: disconnect socket directly after probe failure
  Revert "ipv6: Fix protocol resubmission"
  cfg80211: wext: clear sinfo struct before calling driver

9 years agoDoc: networking: Fix URL for wiki.wireshark.org in udplite.txt
Masanari Iida [Fri, 12 Jun 2015 15:23:21 +0000 (00:23 +0900)]
Doc: networking: Fix URL for wiki.wireshark.org in udplite.txt

This patch fix URL (http to https) for wiki.wireshark.org.

Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
9 years agosctp: allow authenticating DATA chunks that are bundled with COOKIE_ECHO
Marcelo Ricardo Leitner [Thu, 11 Jun 2015 17:49:46 +0000 (14:49 -0300)]
sctp: allow authenticating DATA chunks that are bundled with COOKIE_ECHO

Currently, we can ask to authenticate DATA chunks and we can send DATA
chunks on the same packet as COOKIE_ECHO, but if you try to combine
both, the DATA chunk will be sent unauthenticated and peer won't accept
it, leading to a communication failure.

This happens because even though the data was queued after it was
requested to authenticate DATA chunks, it was also queued before we
could know that remote peer can handle authenticating, so
sctp_auth_send_cid() returns false.

The fix is whenever we set up an active key, re-check send queue for
chunks that now should be authenticated. As a result, such packet will
now contain COOKIE_ECHO + AUTH + DATA chunks, in that order.

Reported-by: Liu Wei <weliu@redhat.com>
Signed-off-by: Marcelo Ricardo Leitner <marcelo.leitner@gmail.com>
Acked-by: Neil Horman <nhorman@tuxdriver.com>
Acked-by: Vlad Yasevich <vyasevich@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
9 years agoMerge branch 'for-linus' of git://git.kernel.dk/linux-block
Linus Torvalds [Fri, 12 Jun 2015 18:35:19 +0000 (11:35 -0700)]
Merge branch 'for-linus' of git://git.kernel.dk/linux-block

Pull block layer fixes from Jens Axboe:
 "Remember about a week ago when I sent the last pull request for 4.1?
  Well, I lied.  Now, I don't want to shift the blame, but Dan, Ming,
  and Richard made a liar out of me.

  Here are three small patches that should go into 4.1.  More
  specifically, this pull request contains:

   - A Kconfig dependency for the pmem block driver, so it can't be
     selected if HAS_IOMEM isn't availble.  From Richard Weinberger.

   - A fix for genhd, making the ext_devt_lock softirq safe.  This makes
     lockdep happier, since we also end up grabbing this lock on release
     off the softirq path.  From Dan Williams.

   - A blk-mq software queue release fix from Ming Lei.

  Last two are headed to stable, first fixes an issue introduced in this
  cycle"

* 'for-linus' of git://git.kernel.dk/linux-block:
  block: pmem: Add dependency on HAS_IOMEM
  block: fix ext_dev_lock lockdep report
  blk-mq: free hctx->ctxs in queue's release handler

9 years agoMerge tag 'md/4.1-rc7-fixes' of git://neil.brown.name/md
Linus Torvalds [Fri, 12 Jun 2015 18:33:03 +0000 (11:33 -0700)]
Merge tag 'md/4.1-rc7-fixes' of git://neil.brown.name/md

Pull three more md fixes from Neil Brown:
 "Hasn't been a good cycle for md has it :-(

  The main issue fixed here is a rare race which can result in two
  reshape threads running at once, which doesn't end well.

  Also a minor issue with a write to a sysfs file returning the wrong
  value.  Backports to 4.0-stable are indicated"

* tag 'md/4.1-rc7-fixes' of git://neil.brown.name/md:
  md: make sure MD_RECOVERY_DONE is clear before starting recovery/resync
  md: Close race when setting 'action' to 'idle'.
  md: don't return 0 from array_state_store

9 years agoMerge git://git.infradead.org/intel-iommu
Linus Torvalds [Fri, 12 Jun 2015 18:28:57 +0000 (11:28 -0700)]
Merge git://git.infradead.org/intel-iommu

Pull VT-d hardware workarounds from David Woodhouse:
 "This contains a workaround for hardware issues which I *thought* were
  never going to be seen on production hardware.  I'm glad I checked
  that before the 4.1 release...

  Firstly, PASID support is so broken on existing chips that we're just
  going to declare the old capability bit 28 as 'reserved' and change
  the VT-d spec to move PASID support to another bit.  So any existing
  hardware doesn't support SVM; it only sets that (now) meaningless bit
  28.

  That patch *wasn't* imperative for 4.1 because we don't have PASID
  support yet.  But *even* the extended context tables are broken — if
  you just enable the wider tables and use none of the new bits in them,
  which is precisely what 4.1 does, you find that translations don't
  work.  It's this problem which I thought was caught in time to be
  fixed before production, but wasn't.

  To avoid triggering this issue, we now *only* enable the extended
  context tables on hardware which also advertises "we have PASID
  support and we actually tested it this time" with the new PASID
  feature bit.

  In addition, I've added an 'intel_iommu=ecs_off' command line
  parameter to allow us to disable it manually if we need to"

* git://git.infradead.org/intel-iommu:
  iommu/vt-d: Only enable extended context tables if PASID is supported
  iommu/vt-d: Change PASID support to bit 40 of Extended Capability Register

9 years agoiommu/vt-d: Only enable extended context tables if PASID is supported
David Woodhouse [Fri, 12 Jun 2015 09:15:49 +0000 (10:15 +0100)]
iommu/vt-d: Only enable extended context tables if PASID is supported

Although the extended tables are theoretically a completely orthogonal
feature to PASID and anything else that *uses* the newly-available bits,
some of the early hardware has problems even when all we do is enable
them and use only the same bits that were in the old context tables.

For now, there's no motivation to support extended tables unless we're
going to use PASID support to do SVM. So just don't use them unless
PASID support is advertised too. Also add a command-line bailout just in
case later chips also have issues.

The equivalent problem for PASID support has already been fixed with the
upcoming VT-d spec update and commit bd00c606a ("iommu/vt-d: Change
PASID support to bit 40 of Extended Capability Register"), because the
problematic platforms use the old definition of the PASID-capable bit,
which is now marked as reserved and meaningless.

So with this change, we'll magically start using ECS again only when we
see the new hardware advertising "hey, we have PASID support and we
actually tested it this time" on bit 40.

The VT-d hardware architect has promised that we are not going to have
any reason to support ECS *without* PASID any time soon, and he'll make
sure he checks with us before changing that.

In the future, if hypothetical new features also use new bits in the
context tables and can be seen on implementations *without* PASID support,
we might need to add their feature bits to the ecs_enabled() macro.

Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
9 years agomd: make sure MD_RECOVERY_DONE is clear before starting recovery/resync
NeilBrown [Fri, 12 Jun 2015 10:05:04 +0000 (20:05 +1000)]
md: make sure MD_RECOVERY_DONE is clear before starting recovery/resync

MD_RECOVERY_DONE is normally cleared by md_check_recovery after a
resync etc finished.  However it is possible for raid5_start_reshape
to race and start a reshape before MD_RECOVERY_DONE is cleared.  This
can lean to multiple reshapes running at the same time, which isn't
good.

To make sure it is cleared before starting a reshape, and also clear
it when reaping a thread, just to be safe.

Signed-off-by: NeilBrown <neilb@suse.de>
9 years agomd: Close race when setting 'action' to 'idle'.
NeilBrown [Fri, 12 Jun 2015 09:51:27 +0000 (19:51 +1000)]
md: Close race when setting 'action' to 'idle'.

Checking ->sync_thread without holding the mddev_lock()
isn't really safe, even after flushing the workqueue which
ensures md_start_sync() has been run.

While this code is waiting for the lock, md_check_recovery could reap
the thread itself, and then start another thread (e.g. recovery might
finish, then reshape starts).  When this thread gets the lock
md_start_sync() hasn't run so it doesn't get reaped, but
MD_RECOVERY_RUNNING gets cleared.  This allows two threads to start
which leads to confusion.

So don't both if MD_RECOVERY_RUNNING isn't set, but if it is do
the flush and the test and the reap all under the mddev_lock to
avoid any race with md_check_recovery.

Signed-off-by: NeilBrown <neilb@suse.de>
Fixes: 6791875e2e53 ("md: make reconfig_mutex optional for writes to md sysfs files.")
Cc: stable@vger.kernel.org (v4.0+)