remove the read/write port/io intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26479 91177308-0d34-0410-b5e6-96231b3b80d8

Remove these testcases.  These intrinsics are going away

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26478 91177308-0d34-0410-b5e6-96231b3b80d8

Update the llvm.memset/memcpy/memmove intrinsics to reflect the recent split
into types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26477 91177308-0d34-0410-b5e6-96231b3b80d8

Split memcpy/memset/memmove intrinsics into i32/i64 versions, resolving
PR709, and paving the way for future progress.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26476 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify the autoupgrade interface

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26475 91177308-0d34-0410-b5e6-96231b3b80d8

Split memcpy/memset/memmove intrinsics into i32/i64 versions, resolving
PR709, and paving the way for future progress.

Significantly refactor autoupgrading code, to handle the more complex case
(where we upgrade one argument in a function), and fix some bugs in it.

Testcase here: llvm/test/Regression/Bytecode/memcpy.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26474 91177308-0d34-0410-b5e6-96231b3b80d8

new testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26473 91177308-0d34-0410-b5e6-96231b3b80d8

add a note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26472 91177308-0d34-0410-b5e6-96231b3b80d8

Add a regression test for bug 478.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26471 91177308-0d34-0410-b5e6-96231b3b80d8

- Fixed some priority calculation bugs that were causing bug 478. Among them:
  a predecessor appearing more than once in the operand list was counted as
  multiple predecessor; priority1 should be updated during scheduling;
  CycleBound was updated after the node is inserted into priority queue; one
  of the tie breaking condition was flipped.
- Take into consideration of two address opcodes. If a predecessor is a def&use
  operand, it should have a higher priority.
- Scheduler should also favor floaters, i.e. nodes that do not have real
  predecessors such as MOV32ri.
- The scheduling fixes / tweaks fixed bug 478:
        .text
        .align  4
        .globl  _f
_f:
        movl 4(%esp), %eax
        movl 8(%esp), %ecx
        movl %eax, %edx
        imull %ecx, %edx
        imull %eax, %eax
        imull %ecx, %ecx
        addl %eax, %ecx
        leal (%ecx,%edx,2), %eax
        ret

  It is also a slight performance win (1% - 3%) for most tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26470 91177308-0d34-0410-b5e6-96231b3b80d8

Generalize the REM folding code to handle another case Nick Lewycky
pointed out: realize the AND can provide factors and look through Casts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26469 91177308-0d34-0410-b5e6-96231b3b80d8

add a couple more cases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26468 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a compilation error with GCC 4.1.  Thanks to Vladimir Merzliakov for
pointing this out.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26467 91177308-0d34-0410-b5e6-96231b3b80d8

Support for enumerations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26466 91177308-0d34-0410-b5e6-96231b3b80d8

testcase that crashed the new CFE

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26465 91177308-0d34-0410-b5e6-96231b3b80d8

Don't print llvm constant in assmebly file. Assembler won't like comments that
span multiple lines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26463 91177308-0d34-0410-b5e6-96231b3b80d8

Back out my last check-in. Wrong place to fix it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26462 91177308-0d34-0410-b5e6-96231b3b80d8

AsmWriter should not print LLVM constant in comment. Assembler won't like
multi-line comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26461 91177308-0d34-0410-b5e6-96231b3b80d8

Fix CodeGen/Generic/2006-03-01-dagcombineinfloop.ll, an infinite loop
in the dag combiner on 176.gcc on x86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26459 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26458 91177308-0d34-0410-b5e6-96231b3b80d8

Remove extra comma from enum list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26457 91177308-0d34-0410-b5e6-96231b3b80d8

Remove comma from enum list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26456 91177308-0d34-0410-b5e6-96231b3b80d8

Switch back to using actual dwarf tags.  Simplifies code without loss to other
debug forms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26455 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a typo evan noticed

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26454 91177308-0d34-0410-b5e6-96231b3b80d8

Use context and not compile unit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26453 91177308-0d34-0410-b5e6-96231b3b80d8

I guess I can handle large type sizes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26452 91177308-0d34-0410-b5e6-96231b3b80d8

Basic array support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26451 91177308-0d34-0410-b5e6-96231b3b80d8

Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26450 91177308-0d34-0410-b5e6-96231b3b80d8

load (x|y)  -> load (x+y)  iff x and y have no common bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26449 91177308-0d34-0410-b5e6-96231b3b80d8

add a note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26448 91177308-0d34-0410-b5e6-96231b3b80d8

Compile this:

void foo(float a, int *b) { *b = a; }

to this:

_foo:
        fctiwz f0, f1
        stfiwx f0, 0, r4
        blr

instead of this:

_foo:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        stw r2, 0(r4)
        blr

This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26447 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase.  These functions shouldn't touch the stack if stfiwx use
is enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26446 91177308-0d34-0410-b5e6-96231b3b80d8

Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26445 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase.  There should be no accesses to the stack for these functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26444 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for target-specific dag combines

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26443 91177308-0d34-0410-b5e6-96231b3b80d8

Add interfaces for targets to provide target-specific dag combiner optimizations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26442 91177308-0d34-0410-b5e6-96231b3b80d8

Add a new AddToWorkList method, start using it

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26441 91177308-0d34-0410-b5e6-96231b3b80d8

Pull shifts by a constant through multiplies (a form of reassociation),
implementing Regression/CodeGen/X86/mul-shift-reassoc.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26440 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26439 91177308-0d34-0410-b5e6-96231b3b80d8

Vector op lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26438 91177308-0d34-0410-b5e6-96231b3b80d8

New vector type v2f32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26437 91177308-0d34-0410-b5e6-96231b3b80d8

Vector ops lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26436 91177308-0d34-0410-b5e6-96231b3b80d8

New type v2f32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26435 91177308-0d34-0410-b5e6-96231b3b80d8

Missing a cast previously.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26434 91177308-0d34-0410-b5e6-96231b3b80d8

- Added v2f32, not used by any target currently. Only for testing purpose.
- Minor bug fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26433 91177308-0d34-0410-b5e6-96231b3b80d8

- Added VConstant as an abstract version of ConstantVec.
- All abstrct vector nodes must have # of elements and element type as their
first two operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26432 91177308-0d34-0410-b5e6-96231b3b80d8

Add a test case for left shift by 1. We should not be using lea for this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26431 91177308-0d34-0410-b5e6-96231b3b80d8

Another entry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26430 91177308-0d34-0410-b5e6-96231b3b80d8

Don't match x << 1 to LEAL. It's better to emit x + x.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26429 91177308-0d34-0410-b5e6-96231b3b80d8

Add const, volatile, restrict support.
Add array of debug descriptor support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26428 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a regression in a patch from a couple of days ago.  This fixes
Transforms/InstCombine/2006-02-28-Crash.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26427 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26426 91177308-0d34-0410-b5e6-96231b3b80d8

8 spaces -> tab.  Reported by Wink Saville

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26425 91177308-0d34-0410-b5e6-96231b3b80d8

evan's recent x86 isel improvements have fixed this, though not in the way
originally envisioned :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26422 91177308-0d34-0410-b5e6-96231b3b80d8

Add a subtarget feature for the stfiwx instruction.  I know the G5 has it,
but I don't know what other PPC impls do.  If someone could update the proc
table, I would appreciate it :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26421 91177308-0d34-0410-b5e6-96231b3b80d8

new testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26420 91177308-0d34-0410-b5e6-96231b3b80d8

Compile:
unsigned foo4(unsigned short *P) { return *P & 255; }
unsigned foo5(short *P) { return *P & 255; }

to:

_foo4:
        lbz r3,1(r3)
        blr
_foo5:
        lbz r3,1(r3)
        blr

not:

_foo4:
        lhz r2, 0(r3)
        rlwinm r3, r2, 0, 24, 31
        blr
_foo5:
        lhz r2, 0(r3)
        rlwinm r3, r2, 0, 24, 31
        blr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26419 91177308-0d34-0410-b5e6-96231b3b80d8

remove implemented item

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26418 91177308-0d34-0410-b5e6-96231b3b80d8

Fold "and (LOAD P), 255" -> zextload.  This allows us to compile:

unsigned foo3(unsigned *P) { return *P & 255; }
as:
_foo3:
        lbz r3, 3(r3)
        blr

instead of:

_foo3:
        lwz r2, 0(r3)
        rlwinm r3, r2, 0, 24, 31
        blr

and:

unsigned short foo2(float a) { return a; }

as:
_foo2:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lhz r3, -2(r1)
        blr

instead of:

_foo2:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        rlwinm r3, r2, 0, 16, 31
        blr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26417 91177308-0d34-0410-b5e6-96231b3b80d8

fold (sra (sra x, c1), c2) -> (sra x, c1+c2)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26416 91177308-0d34-0410-b5e6-96231b3b80d8

Implement rem.ll:test[7-9] and PR712

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26415 91177308-0d34-0410-b5e6-96231b3b80d8

new testcases for PR712

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26414 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify some code now that the RHS of a rem can't be 0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26413 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26412 91177308-0d34-0410-b5e6-96231b3b80d8

Rearrange some code, fold "rem X, 0", implementing rem.ll:test6

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26411 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for output memory constraints.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26410 91177308-0d34-0410-b5e6-96231b3b80d8

Qualify dwarf namespace inside llvm namespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26409 91177308-0d34-0410-b5e6-96231b3b80d8

readme updates

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26405 91177308-0d34-0410-b5e6-96231b3b80d8

Partial enabling of functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26404 91177308-0d34-0410-b5e6-96231b3b80d8

Don't print constant initializers, they may span lines now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26403 91177308-0d34-0410-b5e6-96231b3b80d8

Supporting multiple compile units.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26402 91177308-0d34-0410-b5e6-96231b3b80d8

Re-orging file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26401 91177308-0d34-0410-b5e6-96231b3b80d8

Pretty print large struct constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26400 91177308-0d34-0410-b5e6-96231b3b80d8

Removed dependency on how operands are printed (want multi-line.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26399 91177308-0d34-0410-b5e6-96231b3b80d8

Use -emit-llvm -S to get .ll file output from llvm-gcc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26397 91177308-0d34-0410-b5e6-96231b3b80d8

Merge two almost-identical pieces of code.

Make this code more powerful by using ComputeMaskedBits instead of looking
for an AND operand.  This lets us fold this:

int %test23(int %a) {
        %tmp.1 = and int %a, 1
        %tmp.2 = seteq int %tmp.1, 0
        %tmp.3 = cast bool %tmp.2 to int  ;; xor tmp1, 1
        ret int %tmp.3
}

into: xor (and a, 1), 1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26396 91177308-0d34-0410-b5e6-96231b3b80d8

new testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26395 91177308-0d34-0410-b5e6-96231b3b80d8

Fold (A^B) == A  ->  B == 0
and  (A-B) == A  ->  B == 0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26394 91177308-0d34-0410-b5e6-96231b3b80d8

New testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26393 91177308-0d34-0410-b5e6-96231b3b80d8

Implement bit propagation through sub nodes, this (re)implements
PowerPC/div-2.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26392 91177308-0d34-0410-b5e6-96231b3b80d8

Reenable this

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26391 91177308-0d34-0410-b5e6-96231b3b80d8

remove some completed notes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26390 91177308-0d34-0410-b5e6-96231b3b80d8

Check RHS simplification before LHS simplification to avoid infinitely looping
on PowerPC/small-arguments.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26389 91177308-0d34-0410-b5e6-96231b3b80d8

Just like we use the RHS of an AND to simplify the LHS, use the LHS to
simplify the RHS.  This allows for the elimination of many thousands of
ands from multisource, and compiles CodeGen/PowerPC/and-elim.ll:test2
into this:

_test2:
        srwi r2, r3, 1
        xori r3, r2, 40961
        blr

instead of this:

_test2:
        rlwinm r2, r3, 31, 17, 31
        xori r2, r2, 40961
        rlwinm r3, r2, 0, 16, 31
        blr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26388 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26387 91177308-0d34-0410-b5e6-96231b3b80d8

Add a bunch of missed cases.  Perhaps the most significant of which is that
assertzext produces zero bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26386 91177308-0d34-0410-b5e6-96231b3b80d8

Fold (X|C1)^C2 -> X^(C1|C2) when possible.  This implements
InstCombine/or.ll:test23.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26385 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26384 91177308-0d34-0410-b5e6-96231b3b80d8

Reverting. Didn't realize some developers were embedding constants in their
target assembler code gen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26383 91177308-0d34-0410-b5e6-96231b3b80d8

ConstantPoolIndex is now the displacement portion of the address (rather
than base).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26382 91177308-0d34-0410-b5e6-96231b3b80d8

Print ConstantPoolSDNode offset field.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26381 91177308-0d34-0410-b5e6-96231b3b80d8

Fixed ConstantPoolIndex operand asm print bug. This fixed 2005-07-17-INT-To-FP
and 2005-05-12-Int64ToFP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26380 91177308-0d34-0410-b5e6-96231b3b80d8

Format large struct constants for readability.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26379 91177308-0d34-0410-b5e6-96231b3b80d8

New test case: use lea for imul by some constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26378 91177308-0d34-0410-b5e6-96231b3b80d8

lea.ll is XFAIL until we implement convertToThreeAddress.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26377 91177308-0d34-0410-b5e6-96231b3b80d8

* Cleaned up addressing mode matching code.
* Cleaned up and tweaked LEA cost analysis code. Removed some hacks.
* Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and
  they need to be matched before LEA.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26376 91177308-0d34-0410-b5e6-96231b3b80d8

Updates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26375 91177308-0d34-0410-b5e6-96231b3b80d8

* Allow mul, shl nodes to be codegen'd as LEA (if appropriate).
* Add patterns to handle GlobalAddress, ConstantPool, etc.
  MOV32ri to materialize these nodes in registers.
  ADD32ri to handle %reg + GA, etc.
  MOV32mi to handle store GA, etc. to memory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26374 91177308-0d34-0410-b5e6-96231b3b80d8

ConstantPoolIndex is now the displacement field of addressing mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26373 91177308-0d34-0410-b5e6-96231b3b80d8

Added a common about the need for X86ISD::Wrapper.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26372 91177308-0d34-0410-b5e6-96231b3b80d8