ARM64: dts: rk3399-android: add HDMI device node support

Change-Id: I29b46d097351c55df66782d55c004c356049fb37
Signed-off-by: xuhuicong <xhc@rock-chips.com>

ARM64: dts: rk3399: add HDMI DDC/CEC pinctrl

Change-Id: Ic3417a5153ceabad3f9c69ffe5b6fa542e7a84c1
Signed-off-by: xuhuicong <xhc@rock-chips.com>

video: rockchip: hdmi: misc clean up to hdmi driver

remove unused dts properties parsed code and print an error message
when enable hdmi clk error

Change-Id: I92f37f5c1dc2cd8dbf18744f4fd17a52bc25080f
Signed-off-by: xuhuicong <xhc@rock-chips.com>

video: rockchip: hdmi: support rk3399 hdmi

RK3399 hdmi register layout is similar with rk3288 and rk3368, so most
code can reuse. but hdmi resign is upgrade from 20 to 21 so it has a
little diffrence. and the hdmi phy clk is Independent from dclk too.

Change-Id: I83b30c92d9572fc9ceaf52777d224e5cec1823be
Signed-off-by: xuhuicong <xhc@rock-chips.com>

regulator: rockchip: lp8752: fix up the compile warning

fix up the warning:
drivers/regulator/lp8752.c: In function 'lp8752_buck_set_mode':
drivers/regulator/lp8752.c:93:2: warning: 'ret' may be used uninitialized in this function [-Wmaybe-uninitialized]

Change-Id: Iee9f69791bbcea2e6b3a16713b76e93cfc0a2b67
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

video: rockchip: fix compile warning: may be used uninitialized

Change-Id: Ia162b79443e8361d93575963c6603999ffc3e405
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

drivers: video: rockchip: rga2: Fix compile warning

Change-Id: I3622b70a5b15014ccb5fb9fc09bced97db194dc8
Signed-off-by: Zhiqin Wei <wzq@rock-chips.com>

iommu: rk-iommu: fix build warning when enable CONFIG_CC_OPTIMIZE_FOR_SIZE

Change-Id: Iff20759a625df9f6c6138eaa8d963d67a483c01d
Signed-off-by: Simon <xxm@rock-chips.com>

ASoC: es8316: fix warning: 'val' may be used uninitialized

Change-Id: If7bdba3cd7a23879a2cf41202d21fadaef614f23
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

rockchip/vcodec: seperate power-on timer for independent hw

Seperate power-on timer for rkvdec and vpu when they are not
in combo mode (definitly independence).

Before this patch, h/w power off schedule will be interrupted
by the other h/w, and power off will be triggered when h/w
still running a task.

Change-Id: I29124e90afccc727d2e7a04098727aa4a2c3e8bb
Signed-off-by: Alpha Lin <alpha.lin@rock-chips.com>

ARM64: rockchip_cros_defconfig: enable the GOV_POWER_ALLOCATOR

Enable the GOV_POWER_ALLOCATOR for rk3399.

Change-Id: I8f7e457a09543d730e30c1ce74a9b5dffba57e10
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: config: enable the devfreq_thermal for rockchip

It will enable the devfreq thermal that's generic devfreq cooling
mechanism through frequency reduction for devices using devfreq.
This will throttle the device by limiting the maximum allowed DVFS
frequency corresponding to the cooling level.

Change-Id: Ia017ecf46599700382b9604e375193135f7d1d24
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

MALI: rockchip: add "platform specific code" of rk platform

Change-Id: Ia58cba15b43f875ac572a3b35807b5ec48e3df01
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

ARM64: dts: rk3399-android: set usbdrd_dwc3_0 in peripheral mode

Change-Id: I775283d3b3c8180e352281568d1b77ab5c5a544c
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

mmc: sdhci-of-arasan: fix using sleep function whthin spinlock

Let's use unlock/lock around phy APIs as them will call
mutex which is sleepable casuing failure of kernel debug
check.

Change-Id: Ic7670bfc9ed763cc9bdec53f85f553bc0be1416c
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

drm/rockchip: vop: fix pin_pol config

rgb/edp/hdmi/mipi pin_pol is removed after (e5683dd FROMLIST:
drm/rockchip: get rid of rockchip_drm_crtc_mode_config), that
is wrong.

This patch re-add those pin_pol config.

Change-Id: I46f3e32ad405f4b6e2f76110757248e8516693c4
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

regulator: mp8865: update mp8865 enable_time

enable_time is controlled by capacitance connected to Pin SS,
it described more detailedly in mp8865 datasheet Page 15.
Capacitance is 12nF now.

Change-Id: Ib604a4e109db7ab125104e5cf3067864fefb6fe0
Signed-off-by: Zain Wang <wzz@rock-chips.com>

ARM64: dts: rk3399: support bluetooth for rk3399-evb

Change-Id: Id1eb05cc4cc39d026b6c26f1635760eed38c8968
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

drm/rockchip: vop: Initialize vskiplines to zero

There is a path that use vskiplines with non-initialize.
That would cause vop abnormal behavior.

Change-Id: I53c6c575d6acc16aeae761dbb4867f3bc8bfe5ce
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: vop: fix iommu crash with async atomic

On Async atomic_commit callback, drm_atomic_clean_old_fb will
clean all old fb, but because async, the old fb may be also on
the vop hardware, dma will access the old fb buffer, clean old
fb will cause iommu page fault.

Reference the fb and unreference it when the fb actuall swap out
from vop hardware.

Change-Id: I585786884295060efdaef0a00c3cbd75244399d7
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: vop: support plane zpos property

Change-Id: Idd0265020a591ce5b34d117442104f625e331119
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: vop: rk3399: add area plane

Change-Id: Ia6f77353363e25423ac29129372bc510565682f8
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: vop: rk3288: add area plane

Change-Id: Iac8fde019020d8f1a671d52c1a4d91ad2d050d43
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: vop: support multi area plane

The series vop of VOP_FULL framework support area plane, such as
RK3288 and RK3399, one group of area planes share same hardware,
reuse the hardware on different scanout time, this design is
useful to support mulit planes with low hardware consume.

Change-Id: Ie53211ce9ed22d03f7668637efbb7c95d9a8eb5b
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm: introduce share plane

The plane hardware is used when the display scanout run into plane active
scanout, that means we can reuse the plane hardware resources on plane
non-active scanout.

Because resource share, There are some limit on share plane: one group
of share planes need use same zpos, can't not overlap, etc.

We assume share plane is a universal plane with some limit flags.
people who use the share plane need know the limit, should call the ioctl
DRM_CLIENT_CAP_SHARE_PLANES, and judge the planes limit before use it.

Change-Id: Iecc3d8e7f1ce29d567cdbad689ba4dbad3d594e1
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

FROMLIST: drm/rockchip: get rid of rockchip_drm_crtc_mode_config

We need to take care of the vop status when use
rockchip_drm_crtc_mode_config, if vop is disabled,
the function would failed, that is terrible.

Save output_type and output_mode into rockchip_crtc_state,
it's nice to make them into atomic.

Conflicts:

drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
drivers/gpu/drm/rockchip/dw-mipi-dsi.c
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
drivers/gpu/drm/rockchip/inno_hdmi.c
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
drivers/gpu/drm/rockchip/rockchip_drm_vop.c

Change-Id: I43c49a92b2b9df02ce8a055bd16948b400ab0f47
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
(am from https://patchwork.kernel.org/patch/8844321/)

UPSTREAM: arm64: Enable the timer on Rockchip architecture

On the RK3368 SoC, support the APB timers for rockchip platform.

Change-Id: I2bee09c4140994d3d2e23f1820663230d82547de
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit c840f28bbf643c361c463bcb8fb815d0b2dad4e8)

UPSTREAM: clocksource/drivers/rockchip: Add err handle for rk_timer_init

Currently rockchip_timer doesn't do some basic cleanup work when
failing to init the timer. Let's add err handle routine to deal
with all the err cases.

Change-Id: I73bbd32592e6fe157a8d166743db3fc130d0004c
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
(cherry picked from commit 522ed95c26cd03b768018e441bbc0ff656e30fe4)

UPSTREAM: clocksource/drivers/rockchip: Add COMPILE_TEST option

Increase the compilation test coverage by adding the COMPILE_TEST option.

Due to the dsb() usage in the driver, this driver is only compilable on
ARM and ARM64.

Change-Id: I5f2c1a5353a7b20c80dcfc3cd3900510f56a0729
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 40ada2aac5e3a3c38f295d4e37b182fc4feff723)

UPSTREAM: clocksource/drivers/rockchip: Remove dsb() usage

The dsb() instruction is pointless in this code.

Remove it.

That also fixes the ARM64 compilation issue.

Change-Id: I0c8e33abe0d976714f4df288fe5ac52ffb8ded5b
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 23b8f81f3890edd06bcabdaac33ff5c087114c59)

UPSTREAM: clocksource/drivers/rockchip: Make the driver more readable

Let's checkstyle to clean up the macros with such trivial details.

Change-Id: I6cf0c7cf5e48bcb4d52a483fdba7c4ce26677f06
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
(cherry picked from commit a0d2216ec0d04ec6bf2a7282774338d5ffb3ff0b)

arm64: dts: rk3399: fix the incorrect crit temperture

Fix the incorrect critial temperture for gpu thermal.

Change-Id: I9ecfc107afcdbb421ae40cc796c40a39d6d68677
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rk3399: support for evb rev1 and evb rev2

For evb1
- rk3399-evb-rev1-android.dts
- rk3399-evb-rev1-cros.dts

For evb2
- rk3399-evb-rev2-android.dts
- rk3399-evb-rev2-cros.dts

Change-Id: I95a2d4229c0a7581ca5ae777340f4d26e86503ba
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

ARM64: rockchip_defconfig: enable THERMAL_DEFAULT_GOV_FAIR_SHARE

Change-Id: Ide2ca2361cb13454d0e3269a929a57463da53985
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM64: dts: rk3399: android: Enable rga device

Change-Id: I7c348158c410b8bd32a574a607a975fe5e8b74a5
Signed-off-by: Zhiqin Wei <wzq@rock-chips.com>

ARM64: dts: rk3399-evb: add mmc-hs400-enhanced-strobe support

This patch enables mmc-hs400-enhanced-strobe for rk3399-evb, so
enhanced strobe function will be used if any eMMC 5.1 is probed.

Change-Id: If5f30e0d759f7a9850bec82c3d53d9bb26ba8c3d
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

mmc: add hs400 enhanced strobe support for mmc subsystem

HS400 enhanced strobe is a new feature introduced by eMMC
spec 5.1, let's implement it and enjoy it!

please note that currently I have no much bandwith to split this
big patch into patchset. So please use, test and applied! Thanks.

Change-Id: I874f18a617a1b69e3ff56f5c134feb817b6985b9
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

Documentation: mmc: add mmc-hs400-enhanced-strobe

Let's add some description of mmc-hs400-enhanced-strobe
which can be used to support hs400 enhanced strobe function
introduced by eMMC spec 5.1

Change-Id: I03b8e803071dc7034bddf655892b12eabcaa852a
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

netfilter: xt_qtaguid: fix crash on non-full sks

If sock is request_sock then kernel will crash. So use
skb_to_full_sk() and sk_fullsock() helper to make sure
we get full sock.

Change-Id: Iefd548e0591055b1a8031f0835c4dca7b9d42b61
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM64: rockchip_cros_defconfig: cleanup and use HZ=1000 for cros

At least for the cros, we have previously kept ARM and ARM64 common
configs on HZ=1000, but at least on ARM64, each individual ARM64 kernel
config.

Also, cleanup for cros config.

Change-Id: I1f4470a01b409e212bd60b6fd885a8f2b53d8850
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

clk: rockchip: rk3399: fix the incorrect parent for c/gpll_aclk_perihp_src

Change-Id: I9cacddcaa637d46a96c7c70c8d0938688561b187
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: rockchip_cros_defconfig: Don't force the command line

There's no reason to force the command line at this point.

Forcing the command like makes it pretty hard to switch between eMMC and
SD card boots because the old command line forced the root filesystem to
/dev/mmcblk0p3 vs. depthcharge automatically inserting the right UUID
based on where it found the kernel.

BUG=None
TEST=I see my command line now.

Change-Id: I5f76b60b9726aee2152c09fbd6460b2b973b0b20
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: rockchip_defconfig: enable lp8752 regulator

Change-Id: Id3281624c80bb56fb8fd939f14edfdd59bc0393a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

regulator: rockchip: lp8752: support lp8752 regulator

updata lp8752 driver.
add devicetree bindings for lp8752.

Change-Id: I21cdbde985d4663862b56c28429c41d9d3c38c36
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: dts: rk3399: add trackpad for gru/kevin boards

The trackpad bits in the DTS needed some love.  This adds some basic
infrastructure support in the main gru dts file and then adds the
specific trackpad used on kevin-r0 and kevin-r1.  For now just duplicate
between kevin-r0 and kevin-r1 and we'll decide if we want to share
later (perhaps we want an "atmel" snippet?).

Note that gpio-keymap here makes the driver appear as a trackpad rather
than a touchscreen (driver assumes that anything with buttons is a
trackpad).  Input entry corresponding to the button on the trackpad was
found by experimentation as suggested in the device tree bindings.

BUG=chrome-os-partner:52637
TEST=With series, trackpad works in browser; button works.

Change-Id: Ia62cff90449625778fd99054b914e22a55c13550
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/256510
Commit-Ready: Doug Anderson <dianders@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Reviewed-by: Brian Norris <briannorris@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: rockchip_cros_defconfig: Turn on atmel touchscreen driver

The touchscreen driver is used for both atmel trackpads (AKA touchpads)
and touchscreens.  Turn it on so we can use it.

BUG=chrome-os-partner:52637
TEST=With series, trackpad works in browser; button works.

Change-Id: I316a8411c35ab7b48182cbe704c9f80114a5afcf
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/256511
Commit-Ready: Doug Anderson <dianders@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Reviewed-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rockchip: kevin: enable HS400 mode on kevin board

enable HS400 mode on kevin, if found it is not stable, just
remove "mmc-hs400-1_8v" property, it will use HS200 mode instead.

Change-Id: I7c5d162de1f15bcc069134ffa228d833be2b8a02
Signed-off-by: Lin Huang <hl@rock-chips.com>

ARM64: dts: rockchip: kevin: add configure for emmc phy

assign freq-sel, dr-sel, opdelay value to meet the hardware
requirement of kevin.

Change-Id: Ibb410c607e69c966a9f2949846ef95ec34e15e79
Signed-off-by: Lin Huang <hl@rock-chips.com>

ARM64: dts: rk3399: support arm64 cpuidle-dt

Change-Id: I5506a6647985f44de352f097cf809b31f1917e6a
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

ARM64: dts: rk3399: change for thermal zone

Let's control the power more be effective.We should make the big clusters
cpu throttle firstly.

Change-Id: I8f055f5856ce0239f9bf8bb5b5f2705b3151ba03
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

thermal: rockchip: fixes the period time for tsadc

we should increase the period cycles to save power since the rk3399 has
the high frequency for tsadc clock.

Change-Id: Ia9481515cac6dd6026d3312ac930329a3e906436
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

thermal: rockchip: add the set_trips function

Whenever the current temperature is updated, the trip points immediately
below and above the current temperature are found. A sensor driver
callback `set_trips' is then called with the temperatures.
Lastly, The sensor will trigger the hardware high temperature interrupts
to increase the sampleing rate and throttle frequency to limit the temperature
rising When performing passive cooling.

Change-Id: I16b2ab4f8fb85425aab5cd3777ca600bd4cace20
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

thermal: bang-bang governor: act on lower trip boundary

With interrupt driven thermal zones we pass the lower and upper temperature
on which shall be acted, so in the governor we have to act on the exact lower
temperature to be consistent. Otherwise an interrupt may be generated on the
exact lower temperature, but the bang bang governor does not react.

Change-Id: Ic9dd855b0767d34b15505c1ff12ea99b76cdcea7
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

thermal: streamline get_trend callbacks

The .get_trend callback in struct thermal_zone_device_ops has the prototype:
        int (*get_trend) (struct thermal_zone_device *, int,
                          enum thermal_trend *);
whereas the .get_trend callback in struct thermal_zone_of_device_ops has:

        int (*get_trend)(void *, long *);

Streamline both prototypes and add the trip argument to the OF callback
aswell and use enum thermal_trend * instead of an integer pointer.

While the OF prototype may be the better one, this should be decided at
framework level and not on OF level.

Change-Id: I39c5a38a22c7a2177a35338bc63c8ba36983a7b0
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

thermal: of: implement .set_trips for device tree thermal zones

Change-Id: I566c468165c35e54a17663888539817246d0f0ed
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

thermal: Add support for hardware-tracked trip points

This adds support for hardware-tracked trip points to the device tree
thermal sensor framework.

The framework supports an arbitrary number of trip points. Whenever
the current temperature is updated, the trip points immediately
below and above the current temperature are found. A .set_trips
callback is then called with the temperatures. If there is no trip
point above or below the current temperature, the passed trip
temperature will be -INT_MAX or INT_MAX respectively. In this callback,
the driver should program the hardware such that it is notified
when either of these trip points are triggered. When a trip point
is triggered, the driver should call `thermal_zone_device_update'
for the respective thermal zone. This will cause the trip points
to be updated again.

If .set_trips is not implemented, the framework behaves as before.

This patch is based on an earlier version from Mikko Perttunen
<mikko.perttunen@kapsi.fi>

Change-Id: I8c33f9859909704583ba8b6632b91ffd58a9628e
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

Revert "CHROMIUM: thermal: of: Add support for hardware-tracked trip points"

This reverts commit 2f8e5324ef44d0842f3db3af5fc4da761440abfb.
Since there are the perfect patches in fromlist to instead of it.

Change-Id: I9f15478d0b0b94805d1bb9539a1cbea42a7af6a1
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

Revert "thermal: rockchip: add the set_trips function"

This reverts commit ec24f1ae50a370c9ef7b7166156b79b4d4feee5f.

Change-Id: I1fa579309691ac20d22bebf9f9cea1cd2243440f
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

clk: rockchip: rk3399: keep the pclk_vio is CLK_IGNORE_UNUSED and critical

When we use the MIPI screen, the driver will unprepare and disable
the phy_cfg, it will diable its parent pclk_vio:
dw_mipi_dsi_phy_init
  --> clk_disable_unprepare
    --> clk_disable
      --> clk_core_disable(core->parent)

The pclk_vio supply power for pclk_vio_grf, hence, disable pclk_vio_grf will
cause other drivers failed to operate GRF.

Change-Id: I6d5bd27b9478da09209130f1fd5a62c0d4bb1785
Reported-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: dts: rk3399-evb: enable HS400 mode for emmc

We now enable HS400 mode for rk3399-evb for rk folks
to do more test for hs400. If any problem, please remove
mmc-hs400-1_8v from rk3399-evb.dtsi and any reports are
welcomed.

Change-Id: If7d9d291351a075fbb258bd04fce2a2f9cb81be3
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM64: dts: rk3399-evb: add some configure for emmc phy

This patch assign freq-sel, dr-sel, opdelay to meet the
hw requirement of rk3399-evb.

Change-Id: I1ef98645b5414bcffa0b5711bc9eb63f077a5dc3
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM64: dts: rk3399-evb: remove freq limit for sdhci

Change-Id: Ib5916869b79016f6dd4f99389bf723d82355bca3
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM64: dts: rk3399: assign clk parent and rate for SCLK_EMMC

Let's assign clk parent and rate for SCLK_EMMC to meet the
requiremen.

Change-Id: I3730a2124494da51717b1756f488f9df5bcd6423
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

mmc: sdhci-of-arasan: refactor set_clock callback

commit 61b914eb81f8 ("mmc: sdhci-of-arasan: add phy support for
sdhci-of-arasan") introduce phy support for arasan. According to
the vendor's databook, we should make sure the phy is in poweroff
stat before we configure the clk stuff. Otherwise it may cause
some IO sample timing issue from the test. But we don't need this
extra operation while running in non HS200/HS400 mode since phy
doesn't trigger sampling block.

Change-Id: I5506f99e5a3b4d9a4356ad485ceac900c6d754aa
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

phy: rockchip-emmc: fix dllrdy timeout issue

According to the databook, 10.2us is the max time for
dll to be ready to work. However from the test, some chips
need 20us for dll to ready. So this patch add some extra
margin for dllrdy to be ready to meet the reality.

Change-Id: Ie5362b4403309d260ac621b8b20a0f5b579d3153
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

Documentation: bindings: add more configuration for rockchip emmc phy

This patch add some optional configuration for dt. freq-sel can be used
to decide the phy sample clk in order to match the real freq of emmc
controller. dr-sel can be configured to match the requirement of different
drive strength of phy IO. opdelay should be used to adjust the output
delay for clk IO and data IO, which is useful for sloving timing issue.

Change-Id: I0b4da111581c76fbb96b15cd6be653aaa4843c33
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

phy: rockchip-emmc: add some setup configuration

Let's expose the freq-sel, dr-sel, opdalay to dt for user
to decide how to configure their phy.

Change-Id: Ib9ef40b263d3fd669c7bbda666d28c0c55ff6d8e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM64: dts: rockchip: Tiny comment cleanups for kevin-r0

I was having a hard time figuring out where to put new things in
kevin-r0.  Add some comments to explain the sort order.

BUG=None
TEST=Build and boot

Change-Id: I9fb8c200f934542ebed984566bab039d4ec3fd13
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/256509
Commit-Ready: Doug Anderson <dianders@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Reviewed-by: Brian Norris <briannorris@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rockchip: Remove 'veyron' in kevin/gru compatible

Veyron was an rk3288 board.  Having it in the compatible doesn't make a
ton of sense.  We'll stick 'gru' in the kevin name, though, since that
sorta makes sense.  Not that we ever really fall back to this stuff.

BUG=None
TEST=Build and boot

Change-Id: Ia4b6e02bd9b160c0b20e5459ca441047add2c0bd
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/256508
Commit-Ready: Doug Anderson <dianders@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Reviewed-by: Brian Norris <briannorris@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rockchip: Fixup revisions for kevin

Turns out that we got mixed up.  Old stuff should just be rev 0.  New
stuff should be rev 1+.  Fix all that.

BUG=None
TEST=Boot rev 0.

Change-Id: I41b38893f1e4224df4e3646cd268179307b3476b
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/256507
Commit-Ready: Doug Anderson <dianders@google.com>
Tested-by: Doug Anderson <dianders@google.com>
Reviewed-by: Brian Norris <briannorris@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

arm64: dts: add kevin r1 and r2

Some pinctrl stuff has moved around and will be identical between gru
and kevin going forward, so kevin r1-specific things will be stored
in the kevin-r1 dts file.

BUG=none
TEST=kernel still boots on kevin-r1

Change-Id: If3e88a57acc40367afca34b5310a59efd70287f6
Signed-off-by: Stephen Barber <smbarber@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/256345
Commit-Ready: Stephen Barber <smbarber@google.com>
Tested-by: Stephen Barber <smbarber@google.com>
Reviewed-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

FROMLIST: mfd: cros_ec: Allow building for ARM64

There are platforms using the ChromeOS embeded controller on ARM64 now,
so let's allow using this driver (without having to use COMPILE_TEST).

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
BUG=none
TEST=make sure we can enable cros_ec for ARM64

Change-Id: I828fec4a2022ea50f10c269ee88ae92c30f48337
Reviewed-on: https://chromium-review.googlesource.com/339540
Commit-Ready: Dan Shi <dshi@google.com>
Tested-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Guenter Roeck <groeck@google.com>
Reviewed-on: https://chrome-internal-review.googlesource.com/256311
Commit-Ready: Brian Norris <briannorris@google.com>
Tested-by: Brian Norris <briannorris@google.com>
Reviewed-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

FROMLIST: platform/chrome: cros_ec_dev - Populate compat_ioctl

compat_ioctl has to be populated for 32 bit userspace applications to work
with 64 bit kernels.

BUG=chrome-os-partner:52276
TEST=Build and test with ectool on kevin

Change-Id: I3955d4cf869e4ad4b9f48cdc3b5901cf49dbbe83
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
(am from https://patchwork.kernel.org/patch/8844321/)
Signed-off-by: Guenter Roeck <groeck@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/256310
Commit-Ready: Brian Norris <briannorris@google.com>
Tested-by: Brian Norris <briannorris@google.com>
Reviewed-by: Doug Anderson <dianders@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: gru: fix pwm regulator supplies

The vin-supply binding is valid only for fixed regulators. pwm-supply
should be used for PWM regulators.

Change-Id: I6b65eac6ddc424bb97ba9133b0d67286252b8568
Signed-off-by: Stephen Barber <smbarber@chromium.org>
Reviewed-on: https://chrome-internal-review.googlesource.com/255731
Tested-by: Stephen Barber <smbarber@google.com>
Reviewed-by: Doug Anderson <dianders@google.com>

Revert "ARM64: dts: rk3399: gru: Let VOP Big first to select connector device"

We must not to adjust the port order, cause the port id is mapping
to VOP type. Current driver just hardcode that VOP Lit is ID 0, and
VOP Big is ID 1.

        ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
        if (ret)
                val = dp->data->lcdsel_lit | dp->data->lcdsel_mask;
        else
                val = dp->data->lcdsel_big | dp->data->lcdsel_mask;

Besides eDP could work well with VOP Lit, so we need to revert this
hack. Just revert commit 602f4f79c8f2a833069cd32cb0cc80984e6febb6.

Change-Id: I69badf2860c83c8211ea23b9f490fd4837dcf22e
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM64: dts: rk3399: gpu: add subnode for mali-simple-power-model

Change-Id: I0bd03634631ed30556cc45455582b075692cceba
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

drm/rockchip: analogix_dp: Hack the vop out mode for RK3399 chip

For RK3999 chip, VOP Big/Lit must configure different display out
mode for eDP controller.
  - VOP Lit should output RGB888
  - Vop Big should output RGB10

Change-Id: I85bac6c25a990404682483c62a731681d19eca29
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm/rockchip: analogix_dp: distinguish chip type for each chips

Driver could check the chip type to do some special things.

Change-Id: I2a33da466db0aa5133868c200a122df675f4c925
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm/rockchip: analogix_dp: rename analogix_dp_data to rockchip_dp_chip_data

Make the data structure name more exactly.

Change-Id: I3d7826ef86d2059cd1557bf4d31b7281377e9fae
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm/rockchip: analogix_dp: remove the devtype check in .mode_valid function

The device type would always be ROCKCHIP_DP, so no need to add the
unused devtype check.

Change-Id: I7668a4bdb29700c5397583b9539446f19ae49c3b
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm: bridge: analogix_dp: rename RK3288_DP to ROCKCHIP_DP

Change-Id: I05adaad81ea1beabee1fa674bc00f4e044a58913
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

MALI: rockchip: update mali-midgard binding doc

Change-Id: Iffb05ab0032bf0be33652803d4931018e06e0631
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

MALI: rockchip: adjust code about thermal for kernel 4.4

Change-Id: Ic5f3947b032deaaa800ee316636a8cc61259ba5d
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

ARM64: rockchip_defconfig: enable pwm regulator

Change-Id: Id46711f5fd2de5b85e380c146ed77682aaae5376
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: ASoC: da7219: Disallow unsupported 32KHz clock setting in set_dai_sysclk()

The PLL function was updated to disallow 32KHz in
commit 501f72e9c520 ("ASoC: da7219: Remove support for 32KHz PLL mode"),
but set_dai_sysclk() was missed and still permits it. This patch resolves
that discrepancy.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org kernel/git/broonie/sound.git
topic/da7219 commit fb137ba64a6415ddf231495f6d1a82de1cd69ed0)

Change-Id: I1cf8242745f39ac5ae3cb1aa30989bf4ab8f7f93
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ASoC: da7219: Update PLL ranges and dividers to improve locking

The expected MCLK frequency ranges and the associated dividers
are updated to improve PLL locking in a corner scenario, with low
MCLK frequency near an input divider change boundary.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org kernel/git/broonie/sound.git
topic/da7219 commit 63a450aa4d08ccf4f53e9fa59144e746e2288319)

Change-Id: I7b830ef2ea1e25600365872802924f617b6e0274
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: dts: rk3399: evb1-cros: disabled eDP device node

There is a pull up resistor connected to eDP HPD pin on EVB1
hardware, and then eDP controller would always reported that
eDP panel is connected, even if no panel connected.

That would cause driver keep failed on eDP AUX communication,
and lots of annoying error messages would be printed out.

Beside actually the primary panel on EVB1 board is MIPI panel,
few people would have the eDP panel. So let's just disabled
the eDP device on EVB1 board.

Change-Id: Ic2f8b94360821f91e3607c2bfde7d8399fd0080f
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

input: touchscreen: fix kernel crash in fb_notifier_callback function

fb_event would only carry the data number in some special notify action,
other actions wouldn't carry an valid data number, and in this case
kernel would crash, logs like:

[    4.129846] Unable to handle kernel paging request at virtual address 200000000000
......
[    4.164618] Hardware name: Rockchip RK3399 Evaluation Board v1 (Chrome OS) (DT)
[    4.184624] PC is at fb_notifier_callback+0x28/0xac
[    4.189497] LR is at notifier_call_chain+0x74/0xb4
[    4.194279] pc : [<ffffffc0005e1468>] lr : [<ffffffc0000b5ba4>] pstate: 20000045
......
[    5.703780] [<ffffffc0005e1468>] fb_notifier_callback+0x28/0xac
[    5.709690] [<ffffffc0000b5ba4>] notifier_call_chain+0x74/0xb4
[    5.715504] [<ffffffc0000b5e70>] __blocking_notifier_call_chain+0x48/0x64
[    5.722280] [<ffffffc0000b5ea0>] blocking_notifier_call_chain+0x14/0x1c
[    5.728885] [<ffffffc00036fd98>] fb_notifier_call_chain+0x20/0x28
[    5.734969] [<ffffffc0003726c0>] register_framebuffer+0x218/0x250
[    5.741054] [<ffffffc0003b7598>] drm_fb_helper_initial_config+0x2f8/0x374
[    5.747832] [<ffffffc0003e056c>] rockchip_drm_fbdev_init+0xa8/0xe8
[    5.754002] [<ffffffc0003dba24>] rockchip_drm_load+0x1e4/0x25c

Change-Id: I3314315a31bbab43489fca85dabc4c6511fc9dee
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

UPSTREAM: soc: rockchip: power-domain: support qos save and restore

support qos save and restore when power domain on/off.

Change-Id: I5cecf9755467290bc153eeeb75dfd009e7736820
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-armsoc/drivers
 commit 074c6a422d86fff76e05cf31be25e0eb752e1bd4)

UPSTREAM: dt-bindings: modify document of Rockchip power domains

Rockchip Socs contain quality of service (qos) blocks managing priority,
bandwidth, etc of the connection of each domain to the interconnect.
These blocks loose state when their domain gets disabled and therefore
need to be saved when disabling and restored when enabling a power-domain.

These qos blocks also are similar over all currently available Rockchip
SoCs.

Change-Id: I03c80e01ae0fd1a66a67db15f24869047862f13f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-armsoc/drivers
 commit 71daabca344b503f98c59e4bdd53a818cd01f2af)

UPSTREAM: soc: rockchip: power-domain: check the existing of regmap

Check return value of syscon_node_to_regmap for
rockchip_pm_domain_probe. If err value is returned, probe
procedure should abort.

Change-Id: I8b6f2a62d383c5cae5b69e030a8a8e2ad9cc18c1
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-armsoc/drivers
 commit 4506697d9f8537a8d33e9e002f8efceb32d10757)

ARM64: dts: rockchip: rk3366: assign parent for gpu and wifi.

Gpu's 480MHz need to select usbphy_480m as parent.
The jitter will be lower, if sclk_wifidsp is supplied by pll_wifi.

Change-Id: I13e5077d55ab80e5224bac36b469e39d556bd347
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rk3366: modify the parent's name of usbphy480m

Change-Id: I6a628a96acba4e73405ffc58fbd9a8f6e4544e4f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

UPSTREAM: clk: Add clk_composite_set_rate_and_parent

When changing the clock-rate, currently a new parent is set first and a
divider adapted thereafter. This may result in the clock-rate overflowing
its target rate for a short time if the new parent has a higher rate than
the old parent.

While this often doesn't produce negative effects, it can affect components
in a voltage-scaling environment, like the GPU on the rk3399 socs, where
the voltage than simply is to low for the temporarily to high clock rate.

For general clock hirarchies this may need more extensive adaptions to
the common clock-framework, but at least for composite clocks having
both parent and rate settings it is easy to create a short-term solution to
make sure the clock-rate does not overflow the target.

Change-Id: Iceb40b24ef13db6947be3d797ea90b3e1055b9df
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from git.kernel.org clk/linux.git clk-next
 commit 9e52cec04fd3b9b686f9256151b47fe61f7c28ef)

UPSTREAM: clk: rockchip: reign in some overly long lines in the rk3399 controller

We allow overlong lines in the array portitions describing the clock
trees to ease readability by having each element always at the same
position. But the rest of the code should honor the 80 char limit.

Fix the newly added rk3399 clock code to respect that.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org kernel/git/mmind/linux-rockchip.git
v4.7-clk/next commit 995d3fdeb2f2d362b1b6bf26656c417452939a1a)

Conflicts:

drivers/clk/rockchip/clk-rk3399.c
[
zx: this patch is based on the old version by Heiko on the upstream:
commit de4939f7fc0a282a4a630e7fcc517ba241340ea0
Author: Xing Zheng <zhengxing@rock-chips.com>
Date:   Fri Mar 25 19:33:48 2016 +0800

    clk: rockchip: rk3399: add some aclk/dclk IDs for vop0/vop1
]

Change-Id: I6aeda93a54ab96ab885f9bf04a5f21b07d1c9a89
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: dts: rk3399-fb: include mipi_dsi.h for mipi command mode of timing file

Change-Id: I4426ff9f47abfa7de99b79078370740226871f44
Signed-off-by: Xubilv <xbl@rock-chips.com>

ARM64: dts: rk3368: include mipi_dsi.h for mipi command mode of timing file

Change-Id: Id80b519c7c45678d6163828f4d500f1fc5742343
Signed-off-by: Xubilv <xbl@rock-chips.com>

ARM64: dts: rk3366: include mipi_dsi.h for mipi command mode of timing file

Change-Id: Ib1e43d4df5735c2364138423d9622fd906ff5349
Signed-off-by: Xubilv <xbl@rock-chips.com>

ARM64: configs: rockchip_defconfig: enable DRM RGA support

Change-Id: I8516f9ad6c4c539839135449b36d74649443adf9
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM64: configs: rockchip_cros_defconfig: enable DRM RGA driver support

Change-Id: I4da9799d9e7fc824893b9b19b0e62cc03156ab54
Signed-off-by: Yakir Yang <ykk@rock-chips.com>