Matt Arsenault [Tue, 6 Jan 2015 23:00:41 +0000 (23:00 +0000)]
R600/SI: Pattern match isinf to v_cmp_class instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225307
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Tue, 6 Jan 2015 23:00:39 +0000 (23:00 +0000)]
R600/SI: Add basic DAG combines for fp_class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225306
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Tue, 6 Jan 2015 23:00:37 +0000 (23:00 +0000)]
R600/SI: Add class intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225305
91177308-0d34-0410-b5e6-
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Matt Arsenault [Tue, 6 Jan 2015 23:00:33 +0000 (23:00 +0000)]
Fix using wrong intrinsic in test
This is a leftover from renaming the intrinsic.
It's surprising the unknown llvm. intrinsic wasn't rejected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225304
91177308-0d34-0410-b5e6-
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Rafael Espindola [Tue, 6 Jan 2015 22:55:16 +0000 (22:55 +0000)]
Change the .ll syntax for comdats and add a syntactic sugar.
In order to make comdats always explicit in the IR, we decided to make
the syntax a bit more compact for the case of a GlobalObject in a
comdat with the same name.
Just dropping the $name causes problems for
@foo = globabl i32 0, comdat
$bar = comdat ...
and
declare void @foo() comdat
$bar = comdat ...
So the syntax is changed to
@g1 = globabl i32 0, comdat($c1)
@g2 = globabl i32 0, comdat
and
declare void @foo() comdat($c1)
declare void @foo() comdat
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225302
91177308-0d34-0410-b5e6-
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Hal Finkel [Tue, 6 Jan 2015 22:31:02 +0000 (22:31 +0000)]
[PowerPC] Reuse a load operand in int->fp conversions
int->fp conversions on PPC must be done through memory loads and stores. On a
modern core, this process begins by storing the int value to memory, then
loading it using a (sometimes special) FP load instruction. Unfortunately, we
would do this even when the value to be converted was itself a load, and we can
just use that same memory location instead of copying it to another first.
There is a slight complication when handling int_to_fp(fp_to_int(x)) pairs,
because the fp_to_int operand has not been lowered when the int_to_fp is being
lowered. We handle this specially by invoking fp_to_int's lowering logic
(partially) and getting the necessary memory location (some trivial refactoring
was done to make this possible).
This is all somewhat ugly, and it would be nice if some later CodeGen stage
could just clean this stuff up, but because doing so would involve modifying
target-specific nodes (or instructions), it is not immediately clear how that
would work.
Also, remove a related entry from the README.txt for which we now generate
reasonable code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225301
91177308-0d34-0410-b5e6-
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Mehdi Amini [Tue, 6 Jan 2015 20:05:02 +0000 (20:05 +0000)]
Use a Factory Method for MachineFunctionInfo Creation
The goal is to allows MachineFunctionInfo to override this create
function to customize the creation.
No change intended in existing backend in this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225292
91177308-0d34-0410-b5e6-
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Colin LeMahieu [Tue, 6 Jan 2015 20:03:31 +0000 (20:03 +0000)]
[Hexagon] Adding compound jump encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225291
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Tue, 6 Jan 2015 19:52:07 +0000 (19:52 +0000)]
R600/SI: Insert s_waitcnt before s_barrier instructions.
This ensures that all memory operations are complete when all threads
reach the barrier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225290
91177308-0d34-0410-b5e6-
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Tom Stellard [Tue, 6 Jan 2015 19:52:04 +0000 (19:52 +0000)]
R600/SI: Fix dependency calculation for DS writes instructions in SIInsertWaits
In DS write instructions, the address operand comes before the value
operand(s) which is reversed from every other instruction type.
The SIInsertWait assumed that the first use for each instruction
was the value, so for DS write it was protecting the address
operand with s_waitcnt instructions when it should have been
protecting the value operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225289
91177308-0d34-0410-b5e6-
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Adrian Prantl [Tue, 6 Jan 2015 19:47:27 +0000 (19:47 +0000)]
Revert "Reapply: Teach SROA how to update debug info for fragmented variables."
because of a tsan buildbot failure.
This reverts commit 225272.
Fix should be coming soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225288
91177308-0d34-0410-b5e6-
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Colin LeMahieu [Tue, 6 Jan 2015 19:03:20 +0000 (19:03 +0000)]
[Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dcfetch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225283
91177308-0d34-0410-b5e6-
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Sanjoy Das [Tue, 6 Jan 2015 19:02:56 +0000 (19:02 +0000)]
This patch teaches IndVarSimplify to add nuw and nsw to certain kinds
of operations that provably don't overflow. For example, we can prove
%civ.inc below does not sign-overflow. With this change,
IndVarSimplify changes %civ.inc to an add nsw.
define i32 @foo(i32* %array, i32* %length_ptr, i32 %init) {
entry:
%length = load i32* %length_ptr, !range !0
%len.sub.1 = sub i32 %length, 1
%upper = icmp slt i32 %init, %len.sub.1
br i1 %upper, label %loop, label %exit
loop:
%civ = phi i32 [ %init, %entry ], [ %civ.inc, %latch ]
%civ.inc = add i32 %civ, 1
%cmp = icmp slt i32 %civ.inc, %length
br i1 %cmp, label %latch, label %break
latch:
store i32 0, i32* %array
%check = icmp slt i32 %civ.inc, %len.sub.1
br i1 %check, label %loop, label %break
break:
ret i32 %civ.inc
exit:
ret i32 42
}
Differential Revision: http://reviews.llvm.org/D6748
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225282
91177308-0d34-0410-b5e6-
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Colin LeMahieu [Tue, 6 Jan 2015 18:38:26 +0000 (18:38 +0000)]
[Hexagon] Adding encoding information for absolute address loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225279
91177308-0d34-0410-b5e6-
96231b3b80d8
Mehdi Amini [Tue, 6 Jan 2015 18:20:04 +0000 (18:20 +0000)]
SelectionDAGBuilder: move constant initialization out of loop
No semantic change intended.
Reviewers: resistor
Differential Revision: http://reviews.llvm.org/D6834
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225278
91177308-0d34-0410-b5e6-
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Tom Stellard [Tue, 6 Jan 2015 18:00:21 +0000 (18:00 +0000)]
R600/SI: Add a stub GCNTargetMachine
This is equivalent to the AMDGPUTargetMachine now, but it is the
starting point for separating R600 and GCN functionality into separate
targets.
It is recommened that users start using the gcn triple for GCN-based
GPUs, because using the r600 triple for these GPUs will be deprecated in
the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277
91177308-0d34-0410-b5e6-
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Tom Stellard [Tue, 6 Jan 2015 18:00:00 +0000 (18:00 +0000)]
Triple: Add amdgcn triple
This will be used for AMD GPUs with the Graphics Core Next architecture,
which are currently using by the r600 triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225276
91177308-0d34-0410-b5e6-
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Tom Stellard [Tue, 6 Jan 2015 17:59:56 +0000 (17:59 +0000)]
R600/SI: Remove MachineFunction dump from AsmPrinter
The dump was dependent on a feature string, which meant that it couldn't
be disabled or enable on a per compile basis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225275
91177308-0d34-0410-b5e6-
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Andrea Di Biagio [Tue, 6 Jan 2015 17:41:18 +0000 (17:41 +0000)]
[CodeGenPrepare] Improved logic to speculate calls to cttz/ctlz.
This patch improves the logic added at revision 224899 (see review D6728) that
teaches the backend when it is profitable to speculate calls to cttz/ctlz.
The original algorithm conservatively avoided speculating more than one
instruction from a basic block in a control flow grap modelling an if-statement.
In particular, the only allowed instruction (excluding the terminator) was a
call to cttz/ctlz. However, there are cases where we could be less conservative
and still be able to speculate a call to cttz/ctlz.
With this patch, CodeGenPrepare now tries to speculate a cttz/ctlz if the
result is zero extended/truncated in the same basic block, and the zext/trunc
instruction is "free" for the target.
Added new test cases to CodeGen/X86/cttz-ctlz.ll
Differential Revision: http://reviews.llvm.org/D6853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225274
91177308-0d34-0410-b5e6-
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Adrian Prantl [Tue, 6 Jan 2015 17:14:10 +0000 (17:14 +0000)]
Reapply: Teach SROA how to update debug info for fragmented variables.
This also rolls in the changes discussed in http://reviews.llvm.org/D6766.
Defers migrating the debug info for new allocas until after all partitions
are created.
Thanks to Chandler for reviewing!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225272
91177308-0d34-0410-b5e6-
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Filipe Cabecinhas [Tue, 6 Jan 2015 17:08:26 +0000 (17:08 +0000)]
Don't loop endlessly for MachO files with 0 ncmds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225271
91177308-0d34-0410-b5e6-
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Colin LeMahieu [Tue, 6 Jan 2015 16:52:38 +0000 (16:52 +0000)]
[Hexagon] Fix 225267. GP register is not yet fully implemented. Removing Uses [GP] maintains existing behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225270
91177308-0d34-0410-b5e6-
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Adrian Prantl [Tue, 6 Jan 2015 16:50:25 +0000 (16:50 +0000)]
Implement a very basic colored syntax highlighting for llvm-dwarfdump.
The color scheme is the same as the one used by the colorize dwarfdump
script on Darwin.
A new --color option can be used to forcibly turn color on or off.
http://reviews.llvm.org/D6852
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225269
91177308-0d34-0410-b5e6-
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Hal Finkel [Tue, 6 Jan 2015 16:46:37 +0000 (16:46 +0000)]
[PowerPC] Add a regression test for r225251
In r225251, I removed an old entry from the README.txt file. While there are
several contributing factors (including pieces in Clang's ABI code), upon
further reflection, the backend part deserves a regression test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225268
91177308-0d34-0410-b5e6-
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Colin LeMahieu [Tue, 6 Jan 2015 16:15:15 +0000 (16:15 +0000)]
[Hexagon] Adding dealloc_return encoding and absolute address stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225267
91177308-0d34-0410-b5e6-
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Asiri Rathnayake [Tue, 6 Jan 2015 15:55:09 +0000 (15:55 +0000)]
[ARM] Cleanup so_imm* tblgen defintions
No functional changes. Support for ARM's modified immediate syntax was added
in r223113 and r223115 (review: D6408). That patch introduced the mod_imm*
tblegen definitions which renders the existing so_imm* definitions redundant.
This patch gets rid of them completely.
Reviewed as: D6722
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225266
91177308-0d34-0410-b5e6-
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Matt Arsenault [Tue, 6 Jan 2015 15:50:59 +0000 (15:50 +0000)]
Convert fcmp with 0.0 from casted integers to icmp
This is already handled in general when it is known the
conversion can't lose bits with smaller integer types
casted into wider floating point types.
This pattern happens somewhat often in GPU programs that cast
workitem intrinsics to float, which are often compared with 0.
Specifically handle the special case of compares with zero which
should also be known to not lose information. I had a more general
version of this which allows equality compares if the casted float is
exactly representable in the integer, but I'm not 100% confident that
is always correct.
Also fold cases that aren't integers to true / false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225265
91177308-0d34-0410-b5e6-
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NAKAMURA Takumi [Tue, 6 Jan 2015 09:44:44 +0000 (09:44 +0000)]
[CMake] Silence stderr on "COMMAND ${CMAKE_C_COMPILER} -Wl,--version". It was noisy during configuraion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225260
91177308-0d34-0410-b5e6-
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NAKAMURA Takumi [Tue, 6 Jan 2015 09:44:29 +0000 (09:44 +0000)]
Reformat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225259
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Tue, 6 Jan 2015 09:10:47 +0000 (09:10 +0000)]
[PM] Hide a function we only use in an assert behind NDEBUG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225258
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Tue, 6 Jan 2015 09:06:35 +0000 (09:06 +0000)]
[PM] Introduce a utility pass that preserves no analyses.
Use this to test that path of invalidation. This test actually shows
redundant invalidation here that is really bad. I'm going to work on
fixing that next, but wanted to commit the test harness now that its all
working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225257
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 6 Jan 2015 08:59:30 +0000 (08:59 +0000)]
[X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16.
Requires new AsmParserOperand types that detect 16-bit and 32/64-bit mode so that we choose the right instruction based on default sizing without predicates. This is necessary since predicates mess up the disassembler table building.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225256
91177308-0d34-0410-b5e6-
96231b3b80d8
David Majnemer [Tue, 6 Jan 2015 08:41:31 +0000 (08:41 +0000)]
InstCombine: Bitcast call arguments from/to pointer/integer type
Try harder to get rid of bitcast'd calls by ptrtoint/inttoptr'ing
arguments and return values when DataLayout says it is safe to do so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225254
91177308-0d34-0410-b5e6-
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Chandler Carruth [Tue, 6 Jan 2015 08:37:58 +0000 (08:37 +0000)]
[PM] Simplify how we parse the outer layer of the pass pipeline text and
remove an extra, redundant pass manager wrapping every run.
I had kept seeing these when manually testing, but it was getting really
annoying and was going to cause problems with overly eager invalidation.
The root cause was an overly complex and unnecessary pile of code for
parsing the outer layer of the pass pipeline. We can instead delegate
most of this to the recursive pipeline parsing.
I've added some somewhat more basic and precise tests to catch this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225253
91177308-0d34-0410-b5e6-
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Craig Topper [Tue, 6 Jan 2015 07:35:50 +0000 (07:35 +0000)]
[X86] Make isel select the 2-byte register form of INC/DEC even in non-64-bit mode. Convert to the 1-byte form in non-64-bit mode as part of MCInst lowering.
Overall this seems simpler. It reduces duplication of patterns between both modes and it simplifies the memory folding/unfolding tables as they don't need to create fake instructions just to keep track of 64-bitness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225252
91177308-0d34-0410-b5e6-
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Hal Finkel [Tue, 6 Jan 2015 07:23:13 +0000 (07:23 +0000)]
[PowerPC] Remove old README.txt entry regarding struct passing
Because of how Clang represents structs as arrays (at least on non-Darwin
platforms), and what SROA does, etc. this is no longer a problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225251
91177308-0d34-0410-b5e6-
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David Majnemer [Tue, 6 Jan 2015 07:12:52 +0000 (07:12 +0000)]
X86: Don't make illegal GOTTPOFF relocations
"ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
relocation target a movq or addq instruction.
Prohibit the truncation of such loads to movl or addl.
This fixes PR22083.
Differential Revision: http://reviews.llvm.org/D6839
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225250
91177308-0d34-0410-b5e6-
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Hal Finkel [Tue, 6 Jan 2015 07:02:15 +0000 (07:02 +0000)]
[PowerPC] Add some missing names in getTargetNodeName
These are used for debugging output; NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225249
91177308-0d34-0410-b5e6-
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Hal Finkel [Tue, 6 Jan 2015 06:01:57 +0000 (06:01 +0000)]
[PowerPC] Improve int_to_fp(fp_to_int(x)) combining
The old target DAG combine that allowed for performing int_to_fp(fp_to_int(x))
without a load/store pair is updated here with support for unsigned integers,
and to support single-precision values without a third rounding step, on newer
cores with the appropriate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225248
91177308-0d34-0410-b5e6-
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Chandler Carruth [Tue, 6 Jan 2015 04:49:44 +0000 (04:49 +0000)]
[PM] Add a utility pass template that synthesizes the invalidation of
a specific analysis result.
This is quite handy to test things, and will also likely be very useful
for debugging issues. You could narrow down pass validation failures by
walking these invalidate pass runs up and down the pass pipeline, etc.
I've added support to the pass pipeline parsing to be able to create one
of these for any analysis pass desired.
Just adding this class uncovered one latent bug where the
AnalysisManager CRTP base class had a hard-coded Module type rather than
using IRUnitT.
I've also added tests for invalidation and caching of analyses in
a basic way across all the pass managers. These in turn uncovered two
more bugs where we failed to correctly invalidate an analysis -- its
results were invalidated but the key for re-running the pass was never
cleared and so it was never re-run. Quite nasty. I'm very glad to debug
this here rather than with a full system.
Also, yes, the naming here is horrid. I'm going to update some of the
names to be slightly less awful shortly. But really, I've no "good"
ideas for naming. I'll be satisfied if I can get it to "not bad".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225246
91177308-0d34-0410-b5e6-
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Chandler Carruth [Tue, 6 Jan 2015 04:49:38 +0000 (04:49 +0000)]
[PM] Simplify how we use the registry by including it only once. Still
more verbose than I'd like, but the code really isn't that interesting,
and this still seems vastly simpler than any other solutions I've come
up with. =] Maybe if we get to the 10th IR unit, this will be a problem
in practice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225245
91177308-0d34-0410-b5e6-
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Craig Topper [Tue, 6 Jan 2015 04:23:57 +0000 (04:23 +0000)]
[X86] Remove 16-bit and 32-bit offset jump instructions from the AsmParser. We always select the 8-bit size and let the assembler backend relax to the larger size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225243
91177308-0d34-0410-b5e6-
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Craig Topper [Tue, 6 Jan 2015 04:23:53 +0000 (04:23 +0000)]
[X86] Make isel select the shorter form of jump instructions instead of the long form.
The assembler backend will relax to the long form if necessary. This removes a swap from long form to short form in the MCInstLowering code. Selecting the long form used to be required by the old JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225242
91177308-0d34-0410-b5e6-
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Chandler Carruth [Tue, 6 Jan 2015 02:50:06 +0000 (02:50 +0000)]
[PM] Add a collection of no-op analysis passes and switch the new pass
manager tests to use them and be significantly more comprehensive.
This, naturally, uncovered a bug where the CGSCC pass manager wasn't
printing analyses when they were run.
The only remaining core manipulator is I think an invalidate pass
similar to the require pass. That'll be next. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225240
91177308-0d34-0410-b5e6-
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Chandler Carruth [Tue, 6 Jan 2015 02:37:55 +0000 (02:37 +0000)]
[PM] Sink the no-op pass parsing logic into the .def-based registry to
simplify things. This will become more important as I add no-op analyses
that want to re-use the logic we already have for analyses in the
registry. For now, no functionality changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225238
91177308-0d34-0410-b5e6-
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Chandler Carruth [Tue, 6 Jan 2015 02:21:37 +0000 (02:21 +0000)]
[PM] Move the analysis registry into the Passes.cpp file and provide
a normal interface for it in Passes.h.
This gives us essentially a single interface for running pass managers
which are provided from the bottom of the LLVM stack through interfaces
at the top of the LLVM stack that populate them with all of the
different analyses available throughout. It also means there is a single
blob of code that needs to include all of the pass headers and needs to
deal with the registry of passes and parsing names.
No functionality changed intended, should just be cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225237
91177308-0d34-0410-b5e6-
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Chandler Carruth [Tue, 6 Jan 2015 02:10:51 +0000 (02:10 +0000)]
[PM] Add a utility to the new pass manager for generating a pass which
is a no-op other than requiring some analysis results be available.
This can be used in real pass pipelines to force the usually lazy
analysis running to eagerly compute something at a specific point, and
it can be used to test the pass manager infrastructure (my primary use
at the moment).
I've also added bit of pipeline parsing magic to support generating
these directly from the opt command so that you can directly use these
when debugging your analysis. The syntax is:
require<analysis-name>
This can be used at any level of the pass manager. For example:
cgscc(function(require<my-analysis>,no-op-function))
This would produce a no-op function pass requiring my-analysis, followed
by a fully no-op function pass, both of these in a function pass manager
which is nested inside of a bottom-up CGSCC pass manager which is in the
top-level (implicit) module pass manager.
I have zero attachment to the particular syntax I'm using here. Consider
it a straw man for use while I'm testing and fleshing things out.
Suggestions for better syntax welcome, and I'll update everything based
on any consensus that develops.
I've used this new functionality to more directly test the analysis
printing rather than relying on the cgscc pass manager running an
analysis for me. This is still minimally tested because I need to have
analyses to run first! ;] That patch is next, but wanted to keep this
one separate for easier review and discussion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225236
91177308-0d34-0410-b5e6-
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Rafael Espindola [Tue, 6 Jan 2015 01:41:24 +0000 (01:41 +0000)]
Add a testcase that would have found the problem in r225048.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225235
91177308-0d34-0410-b5e6-
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Eric Christopher [Tue, 6 Jan 2015 01:12:42 +0000 (01:12 +0000)]
Remove dead variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225233
91177308-0d34-0410-b5e6-
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Eric Christopher [Tue, 6 Jan 2015 01:12:40 +0000 (01:12 +0000)]
Use the same call off of the TargetMachine rather than the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225232
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Eric Christopher [Tue, 6 Jan 2015 01:12:30 +0000 (01:12 +0000)]
Rewrite the Mips16HardFloat pass to avoid using the Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225231
91177308-0d34-0410-b5e6-
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Lang Hames [Tue, 6 Jan 2015 00:54:32 +0000 (00:54 +0000)]
Revert r225048: It broke ObjC on AArch64.
I've filed http://llvm.org/PR22100 to track this issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225228
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Brad Smith [Tue, 6 Jan 2015 00:53:52 +0000 (00:53 +0000)]
Remove X86 .quad workaround for buggy GNU assembler on OpenBSD / Bitrig.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225227
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Duncan P. N. Exon Smith [Mon, 5 Jan 2015 23:31:54 +0000 (23:31 +0000)]
IR: Don't drop MDNode uniquing on null operands
Now that `LLVMContextImpl` can call `MDNode::dropAllReferences()` to
prevent teardown madness, stop dropping uniquing just because an operand
drops to null.
Part of PR21532.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225223
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Duncan P. N. Exon Smith [Mon, 5 Jan 2015 23:31:51 +0000 (23:31 +0000)]
Revert "Use the integrated assembler by default on 32-bit PowerPC and SPARC"
This reverts commit r225213. It's failing on multiple buildbots [1][2].
[1]: http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/22032
[2]: http://lab.llvm.org:8080/green/view/Clang/job/clang-stage1-cmake-RA-incremental_check/2357/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225222
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Hal Finkel [Mon, 5 Jan 2015 23:17:43 +0000 (23:17 +0000)]
[PowerPC] Fix test to pass on Darwin hosts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225220
91177308-0d34-0410-b5e6-
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Hal Finkel [Mon, 5 Jan 2015 22:20:22 +0000 (22:20 +0000)]
[PowerPC] Remove old README.txt entry
We no longer generate horrible code for the stated function:
void f(signed char *a, _Bool b, _Bool c) {
signed char t = 0;
if (b) t = *a;
if (c) *a = t;
}
for which we now generate:
.L.f:
andi. 5, 5, 1
cmpldi 1, 4, 0
li 5, 0
beq 1, .LBB0_2
lbz 5, 0(3)
.LBB0_2: # %if.end
bclr 4, 1, 0
stb 5, 0(3)
blr
so we don't need the README.txt entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225217
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Mon, 5 Jan 2015 22:08:48 +0000 (22:08 +0000)]
[X86][SSE] lowerVectorShuffleAsByteShift tidyup
Removed local isSequential predicate and use standard helper isSequentialOrUndefInRange instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225216
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Hal Finkel [Mon, 5 Jan 2015 21:53:52 +0000 (21:53 +0000)]
[PowerPC] Convert a README.txt entry into a better test
We now produce the desired code as noted in the README.txt file (no spurious
or). Remove the README entry and improve the regression test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225214
91177308-0d34-0410-b5e6-
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Brad Smith [Mon, 5 Jan 2015 21:48:16 +0000 (21:48 +0000)]
Use the integrated assembler by default on 32-bit PowerPC and SPARC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225213
91177308-0d34-0410-b5e6-
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Hal Finkel [Mon, 5 Jan 2015 21:41:26 +0000 (21:41 +0000)]
[PowerPC] Remove README.txt entry
This entry has been rendered irrelevant now that we have proper CR bit
tracking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225211
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Colin LeMahieu [Mon, 5 Jan 2015 21:36:38 +0000 (21:36 +0000)]
[Hexagon] Adding add/sub with carry, logical shift left by immediate and memop instructions. Removing old defs without bits and updating references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225210
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Hal Finkel [Mon, 5 Jan 2015 21:33:14 +0000 (21:33 +0000)]
[PowerPC] Add a test for truncating a shifted load
We now produce the desired code as noted in the README.txt file. Remove the
README entry and add a regression test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225209
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Frederic Riss [Mon, 5 Jan 2015 21:29:41 +0000 (21:29 +0000)]
Make DIE.h a public CodeGen header.
dsymutil would like to use all the AsmPrinter/MCStreamer infrastructure
to stream out the DWARF. In order to do so, it will reuse the DIE object
and so this header needs to be public.
The interface exposed here has some corners that cannot be used without a
DwarfDebug object, but clients that want to stream Dwarf can just avoid
these.
Differential Revision: http://reviews.llvm.org/D6695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225208
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Frederic Riss [Mon, 5 Jan 2015 21:29:28 +0000 (21:29 +0000)]
[dsymutil] Implement the BinaryHolder object and gain archive support.
This object is meant to own the ObjectFiles and their underlying
MemoryBuffer. It is basically the equivalent of an OwningBinary
except that it efficiently handles Archives. It is optimized for
efficiently providing mappings of members of the same archive when
they are opened successively (which is standard in Darwin debug
maps, objects from the same archive will be contiguous).
Of course, the BinaryHolder will also be used by the DWARF linker
once it is commited, but for now only the debug map parser uses it.
With this change, you can run llvm-dsymutil on your Darwin debug build
of clang and get a complete debug map for it.
Differential Revision: http://reviews.llvm.org/D6690
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225207
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NAKAMURA Takumi [Mon, 5 Jan 2015 21:24:36 +0000 (21:24 +0000)]
[autoconf] llvm/cmake/modules/Makefile: Make sure to regenerate LLVMConfig.cmake whenever Makefile is updated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225206
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Hal Finkel [Mon, 5 Jan 2015 21:22:42 +0000 (21:22 +0000)]
[PowerPC] Add another test for load/store with update
We now produce the desired code as noted in the README.txt file. Remove the
README entry and add a regression test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225205
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NAKAMURA Takumi [Mon, 5 Jan 2015 21:14:14 +0000 (21:14 +0000)]
[autoconf] Export LLVM_LIBDIR_SUFFIX with empty string in LLVMConfig.cmake. tools/llvm-config is also doing so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225204
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Hal Finkel [Mon, 5 Jan 2015 21:10:24 +0000 (21:10 +0000)]
[PowerPC] Fold i1 extensions with other ops
Consider this function from our README.txt file:
int foo(int a, int b) { return (a < b) << 4; }
We now explicitly track CR bits by default, so the comment in the README.txt
about not really having a SETCC is no longer accurate, but we did generate this
somewhat silly code:
cmpw 0, 3, 4
li 3, 0
li 12, 1
isel 3, 12, 3, 0
sldi 3, 3, 4
blr
which generates the zext as a select between 0 and 1, and then shifts the
result by a constant amount. Here we preprocess the DAG in order to fold the
results of operations on an extension of an i1 value into the SELECT_I[48]
pseudo instruction when the resulting constant can be materialized using one
instruction (just like the 0 and 1). This was not implemented as a DAGCombine
because the resulting code would have been anti-canonical and depends on
replacing chained user nodes, which does not fit well into the lowering
paradigm. Now we generate:
cmpw 0, 3, 4
li 3, 0
li 12, 16
isel 3, 12, 3, 0
blr
which is less silly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225203
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Simon Pilgrim [Mon, 5 Jan 2015 21:09:48 +0000 (21:09 +0000)]
[X86][SSE] Fixed description for isSequentialOrUndefInRange. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225202
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Colin LeMahieu [Mon, 5 Jan 2015 20:56:41 +0000 (20:56 +0000)]
[Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and accumulating shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225201
91177308-0d34-0410-b5e6-
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Duncan P. N. Exon Smith [Mon, 5 Jan 2015 20:41:25 +0000 (20:41 +0000)]
IR: Prune arguments to ValueAsMetadata::ValueAsMetadata()
`LLVMContext` isn't actually used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225200
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Colin LeMahieu [Mon, 5 Jan 2015 20:35:54 +0000 (20:35 +0000)]
[Hexagon] Adding V4 bit manipulating instructions, removing ALU defs without encoding bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225199
91177308-0d34-0410-b5e6-
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Colin LeMahieu [Mon, 5 Jan 2015 20:14:58 +0000 (20:14 +0000)]
[Hexagon] Adding V4 logic-logic instructions and tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225198
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Colin LeMahieu [Mon, 5 Jan 2015 20:04:40 +0000 (20:04 +0000)]
[Hexagon] Adding orand, bitsplit reg/reg, and modwrap instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225197
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Hal Finkel [Mon, 5 Jan 2015 18:52:29 +0000 (18:52 +0000)]
[PowerPC] Remove zexts after i32 ctlz
The 64-bit semantics of cntlzw are not special, the 32-bit population count is
stored as a 64-bit value in the range [0,32]. As a result, it is always zero
extended, and it can be added to the PPCISelDAGToDAG peephole optimization as a
frontier instruction for the removal of unnecessary zero extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225192
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Hal Finkel [Mon, 5 Jan 2015 18:09:06 +0000 (18:09 +0000)]
[PowerPC] Remove zexts after byte-swapping loads
lhbrx and lwbrx not only load their data with byte swapping, but also clear the
upper 32 bits (at least). As a result, they can be added to the PPCISelDAGToDAG
peephole optimization as frontier instructions for the removal of unnecessary
zero extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225189
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Colin LeMahieu [Mon, 5 Jan 2015 18:08:21 +0000 (18:08 +0000)]
[Hexagon] Adding round reg/imm and bitsplit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225188
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Saleem Abdulrasool [Mon, 5 Jan 2015 17:56:32 +0000 (17:56 +0000)]
SymbolRewriter: use iplist::splice
The swap implementation for iplist is currently unsupported. Simply splice the
old list into place, which achieves the same purpose. This is needed in order
to thread the -frewrite-map-file frontend option correctly. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225186
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Saleem Abdulrasool [Mon, 5 Jan 2015 17:56:29 +0000 (17:56 +0000)]
SymbolRewriter: 80-column
Wrap a couple of lines. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225185
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Ahmed Bougacha [Mon, 5 Jan 2015 17:10:26 +0000 (17:10 +0000)]
[AArch64] Improve codegen of store lane instructions by avoiding GPR usage.
We used to generate code similar to:
umov.b w8, v0[2]
strb w8, [x0, x1]
because the STR*ro* patterns were preferred to ST1*.
Instead, we can avoid going through GPRs, and generate:
add x8, x0, x1
st1.b { v0 }[2], [x8]
This patch increases the ST1* AddedComplexity to achieve that.
rdar://
16372710
Differential Revision: http://reviews.llvm.org/D6202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225183
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Ahmed Bougacha [Mon, 5 Jan 2015 17:02:28 +0000 (17:02 +0000)]
[AArch64] Improve codegen of store lane 0 instructions by directly storing the subregister.
For 0-lane stores, we used to generate code similar to:
fmov w8, s0
str w8, [x0, x1, lsl #2]
instead of:
str s0, [x0, x1, lsl #2]
To correct that: for store lane 0 patterns, directly match to STR <subreg>0.
Byte-sized instructions don't have the special case for a 0 index,
because FPR8s are defined to have untyped content.
rdar://
16372710
Differential Revision: http://reviews.llvm.org/D6772
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225181
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NAKAMURA Takumi [Mon, 5 Jan 2015 14:18:04 +0000 (14:18 +0000)]
llvm/test/lit.cfg: have_ld_plugin_support(): Use decode() for stdout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225171
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Karthik Bhat [Mon, 5 Jan 2015 13:57:59 +0000 (13:57 +0000)]
Select lower fsub,fabs pattern to fabd on AArch64
This patch lowers patterns such as-
fsub v0.4s, v0.4s, v1.4s
fabs v0.4s, v0.4s
to
fabd v0.4s, v0.4s, v1.4s
on AArch64.
Review: http://reviews.llvm.org/D6791
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225169
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Charlie Turner [Mon, 5 Jan 2015 13:26:37 +0000 (13:26 +0000)]
Parse Tag_compatibility correctly.
Tag_compatibility takes two arguments, but before this patch it would
erroneously accept just one, it now produces an error in that case.
Change-Id: I530f918587620d0d5dfebf639944d6083871ef7d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225167
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Charlie Turner [Mon, 5 Jan 2015 13:12:17 +0000 (13:12 +0000)]
Emit the build attribute Tag_conformance.
Claim conformance to version 2.09 of the ARM ABI.
This build attribute must be emitted first amongst the build attributes when
written to an object file. This is to simplify conformance detection by
consumers.
Change-Id: If9eddcfc416bc9ad6e5cc8cdcb05d0031af7657e
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225166
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Karthik Bhat [Mon, 5 Jan 2015 13:11:07 +0000 (13:11 +0000)]
Select lower sub,abs pattern to sabd on AArch64
This patch lowers patterns such as-
sub v0.4s, v0.4s, v1.4s
abs v0.4s, v0.4s
to
sabd v0.4s, v0.4s, v1.4s
on AArch64.
Review: http://reviews.llvm.org/D6781
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225165
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Michael Kuperstein [Mon, 5 Jan 2015 12:34:01 +0000 (12:34 +0000)]
Fix broken test from r225159.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225164
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Chandler Carruth [Mon, 5 Jan 2015 12:32:11 +0000 (12:32 +0000)]
[PM] Don't run the machinery of invalidating all the analysis passes
when all are being preserved.
We want to short-circuit this for a couple of reasons. One, I don't
really want passes to grow a dependency on actually receiving their
invalidate call when they've been preserved. I'm thinking about removing
this entirely. But more importantly, preserving everything is likely to
be the common case in a lot of scenarios, and it would be really good to
bypass all of the invalidation and preservation machinery there.
Avoiding calling N opaque functions to try to invalidate things that are
by definition still valid seems important. =]
This wasn't really inpsired by much other than seeing the spam in the
logging for analyses, but it seems better ot get it checked in rather
than forgetting about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225163
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Chandler Carruth [Mon, 5 Jan 2015 12:21:44 +0000 (12:21 +0000)]
[PM] Add names and debug logging for analysis passes to the new pass
manager.
This starts to allow us to test analyses more easily, but it's really
only the beginning. Some of the code here is still untestable without
manual changes to create analysis passes, but I wanted to factor it into
a small of chunks as possible.
Next up in order to be able to test things are, in no particular order:
- No-op analyses passes so we don't have to use real ones to exercise
the pass maneger itself.
- Automatic way of generating dummy passes that require an analysis be
run, including a variant that calls a 'print' method on a pass to make
it even easier to print out the results of an analysis.
- Dummy passes that invalidate all analyses for their IR unit so we can
test invalidation and re-runs.
- Automatic way to print each analysis pass as it is re-run.
- Automatic but optional verification of analysis passes everywhere
possible.
I'm not claiming I'll get to all of these immediately, but that's what
is in the pipeline at some stage. I'm fleshing out exactly what I need
and what to prioritize by working on converting analyses and then trying
to test the conversion. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225162
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Craig Topper [Mon, 5 Jan 2015 10:15:49 +0000 (10:15 +0000)]
Replace several 'assert(false' with 'llvm_unreachable' or fold a condition into the assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225160
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Jiangning Liu [Mon, 5 Jan 2015 10:08:58 +0000 (10:08 +0000)]
Fixed a bug in memory dependence checking module of loop vectorization. The following loop should not be vectorized with current algorithm.
{code}
// loop body
... = a[i] (1)
... = a[i+1] (2)
.......
a[i+1] = .... (3)
a[i] = ... (4)
{code}
The algorithm tries to collect memory access candidates from AliasSetTracker, and then check memory dependences one another. The memory accesses are unique in AliasSetTracker, and a single memory access in AliasSetTracker may map to multiple entries in AccessAnalysis, which could cover both 'read' and 'write'. Originally the algorithm only checked 'write' entry in Accesses if only 'write' exists. This is incorrect and the consequence is it ignored all read access, and finally some RAW and WAR dependence are missed.
For the case given above, if we ignore two reads, the dependence between (1) and (3) would not be able to be captured, and finally this loop will be incorrectly vectorized.
The fix simply inserts a new loop to find all entries in Accesses. Since it will skip most of all other memory accesses by checking the Value pointer at the very beginning of the loop, it should not increase compile-time visibly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225159
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Michael Gottesman [Mon, 5 Jan 2015 08:55:19 +0000 (08:55 +0000)]
Convert SmallMapVector from a class to a struct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225158
91177308-0d34-0410-b5e6-
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Craig Topper [Mon, 5 Jan 2015 08:19:12 +0000 (08:19 +0000)]
[X86] Remove the predicates from the register forms of the 2-byte inc and dec instructions. Remove the 32-bit mode only versions that existed for the disassembler. Move the patterns out of the instructions so they can still be qualified with predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225157
91177308-0d34-0410-b5e6-
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Craig Topper [Mon, 5 Jan 2015 08:19:10 +0000 (08:19 +0000)]
[X86] Simplify code a little by just summing flags instead of conditionally incrementing. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225156
91177308-0d34-0410-b5e6-
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Craig Topper [Mon, 5 Jan 2015 08:19:07 +0000 (08:19 +0000)]
[X86] Remove unnecessary redeclaration of a variable with the same assignment as the beginning of the function. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225155
91177308-0d34-0410-b5e6-
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Craig Topper [Mon, 5 Jan 2015 08:19:05 +0000 (08:19 +0000)]
[X86] Remove a strange fixme referring to a hack that doesn't seem to exist since the code is in a comment. Can't figure out what the body of the 'if' was supposed to be anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225154
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Craig Topper [Mon, 5 Jan 2015 08:19:03 +0000 (08:19 +0000)]
[x86] Reduce text duplication for similar operand class declarations in tablegen instruction info. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225153
91177308-0d34-0410-b5e6-
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Craig Topper [Mon, 5 Jan 2015 08:18:59 +0000 (08:18 +0000)]
[X86] Fix the immediate size to match the address size in the operand types for the move to/from absolute memory instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225152
91177308-0d34-0410-b5e6-
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Craig Topper [Mon, 5 Jan 2015 08:18:52 +0000 (08:18 +0000)]
[X86] Remove unused operand type from disassembler handling. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225151
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