Typos

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75991 91177308-0d34-0410-b5e6-96231b3b80d8

Consolidate reg-imm / reg-reg-imm address mode selection logic in one place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75990 91177308-0d34-0410-b5e6-96231b3b80d8

Fix fallout from 12-bit stuff landing: decide whether 20 bit displacements are needed during elimination of frame indexes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75989 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for 12 bit displacements

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75988 91177308-0d34-0410-b5e6-96231b3b80d8

We already have reserved call frame regardless whether variable sized frame objects were present or not

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75987 91177308-0d34-0410-b5e6-96231b3b80d8

Emit proper lowering of load from arg stack slot

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75986 91177308-0d34-0410-b5e6-96231b3b80d8

Implement dynamic allocas

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75985 91177308-0d34-0410-b5e6-96231b3b80d8

Add jump tables

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75984 91177308-0d34-0410-b5e6-96231b3b80d8

Exapnd br_jt into indirect branch. Provide pattern for indirect branches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75983 91177308-0d34-0410-b5e6-96231b3b80d8

Implement 64 bit immediates

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75982 91177308-0d34-0410-b5e6-96231b3b80d8

Add rotates

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75981 91177308-0d34-0410-b5e6-96231b3b80d8

Add patterns for integer negate

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75980 91177308-0d34-0410-b5e6-96231b3b80d8

Provide proper patterns for and with imm instructions. Tune the tests accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75979 91177308-0d34-0410-b5e6-96231b3b80d8

Add 32 bit and reg-imm and disable invalid patterns for now

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75978 91177308-0d34-0410-b5e6-96231b3b80d8

Add z9 and z10 target processors. Mark z10-only instructions as such.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75977 91177308-0d34-0410-b5e6-96231b3b80d8

Fix MUL64rm instruction asmprinting

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75976 91177308-0d34-0410-b5e6-96231b3b80d8

Preliminary asmprinting of globals

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75975 91177308-0d34-0410-b5e6-96231b3b80d8

Implement asmprinting for odd-even regpairs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75974 91177308-0d34-0410-b5e6-96231b3b80d8

32-bit ri addressing mode has only 12-bit displacement

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75973 91177308-0d34-0410-b5e6-96231b3b80d8

Forgot to add

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75972 91177308-0d34-0410-b5e6-96231b3b80d8

Do not put bunch of target-specific stuff into common namespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75971 91177308-0d34-0410-b5e6-96231b3b80d8

Print signed imms properly

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75970 91177308-0d34-0410-b5e6-96231b3b80d8

Provide hooks for spilling / restoring stuff

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75969 91177308-0d34-0410-b5e6-96231b3b80d8

Revert thinko

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75968 91177308-0d34-0410-b5e6-96231b3b80d8

Temporary workaround problem with signed 32-bit imm's

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75967 91177308-0d34-0410-b5e6-96231b3b80d8

Implement InsertBranch() hook

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75966 91177308-0d34-0410-b5e6-96231b3b80d8

Pipehole pattern for i32 imm's

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75965 91177308-0d34-0410-b5e6-96231b3b80d8

Bunch of sext_inreg patterns

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75964 91177308-0d34-0410-b5e6-96231b3b80d8

Provide normal 32 bit load and store

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75963 91177308-0d34-0410-b5e6-96231b3b80d8

Proper lower 'small' results

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75962 91177308-0d34-0410-b5e6-96231b3b80d8

Completel forgot about unconditional branches

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75961 91177308-0d34-0410-b5e6-96231b3b80d8

Lower addresses of globals

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75960 91177308-0d34-0410-b5e6-96231b3b80d8

Test (incomplete) for easy muls

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75959 91177308-0d34-0410-b5e6-96231b3b80d8

Provide "wide" muls and divs/rems

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75958 91177308-0d34-0410-b5e6-96231b3b80d8

Fix thinko

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75957 91177308-0d34-0410-b5e6-96231b3b80d8

Fix epic bug with invalid regclass for R0D

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75956 91177308-0d34-0410-b5e6-96231b3b80d8

Let RegisterInfo decide whether it can emit cross-class copy or not

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75955 91177308-0d34-0410-b5e6-96231b3b80d8

More register pairs (now 32 bit ones)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75954 91177308-0d34-0410-b5e6-96231b3b80d8

Add even-odd register pairs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75953 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak due to mainline api change

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75952 91177308-0d34-0410-b5e6-96231b3b80d8

Preliminary mul lowering

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75951 91177308-0d34-0410-b5e6-96231b3b80d8

More extloads

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75950 91177308-0d34-0410-b5e6-96231b3b80d8

Tests for cmp / br_cc / select_cc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75949 91177308-0d34-0410-b5e6-96231b3b80d8

SELECT_CC lowering

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75948 91177308-0d34-0410-b5e6-96231b3b80d8

Conditional branches and comparisons

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75947 91177308-0d34-0410-b5e6-96231b3b80d8

Emit correct offset for PseudoSourceValue

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75946 91177308-0d34-0410-b5e6-96231b3b80d8

Provide proper stack offsets for outgoing arguments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75945 91177308-0d34-0410-b5e6-96231b3b80d8

Change register allocation order to reduce amount of callee-saved regs to be spilled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75944 91177308-0d34-0410-b5e6-96231b3b80d8

Emit callee-saved regs spills / restores

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75943 91177308-0d34-0410-b5e6-96231b3b80d8

Scan for presence of calls and determine max callframe size early. To allow ProcessFunctionBeforeCalleeSaveScan() use this information

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75942 91177308-0d34-0410-b5e6-96231b3b80d8

Some preliminary call lowering

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75941 91177308-0d34-0410-b5e6-96231b3b80d8

Prologue / epilogue emission

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75940 91177308-0d34-0410-b5e6-96231b3b80d8

Add simple frame index elimination

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75939 91177308-0d34-0410-b5e6-96231b3b80d8

Provide proper test :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75938 91177308-0d34-0410-b5e6-96231b3b80d8

Swap the order of imm and idx field for rri addrmode in order to make handling of rri and ri addrmodes common

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75937 91177308-0d34-0410-b5e6-96231b3b80d8

Do not truncate sign bits for negative imms

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75936 91177308-0d34-0410-b5e6-96231b3b80d8

Add address computation stuff

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75935 91177308-0d34-0410-b5e6-96231b3b80d8

Cleanup

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75934 91177308-0d34-0410-b5e6-96231b3b80d8

Add mem-imm stores

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75933 91177308-0d34-0410-b5e6-96231b3b80d8

[PATCH 023/155] Typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75932 91177308-0d34-0410-b5e6-96231b3b80d8

Add stores and truncstores

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75931 91177308-0d34-0410-b5e6-96231b3b80d8

Add patterns for various extloads

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75930 91177308-0d34-0410-b5e6-96231b3b80d8

Do some heroic rri address matching (shamelessly stolen from x86 backend). Not tested though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75929 91177308-0d34-0410-b5e6-96231b3b80d8

Change register allocation order, so R0 will be allocated the last among scratch. This will make address-calculation code much more happy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75928 91177308-0d34-0410-b5e6-96231b3b80d8

Add shifts and reg-imm address matching

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75927 91177308-0d34-0410-b5e6-96231b3b80d8

Add bunch of 32-bit patterns... Uffff :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75926 91177308-0d34-0410-b5e6-96231b3b80d8

Propagate return result extension type

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75925 91177308-0d34-0410-b5e6-96231b3b80d8

Add tests for fixes I committed earlier to the C++ FE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75924 91177308-0d34-0410-b5e6-96231b3b80d8

Add 32 bit subregs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75923 91177308-0d34-0410-b5e6-96231b3b80d8

Add another bunch of reg-imm patterns for add/or/and/xor

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75922 91177308-0d34-0410-b5e6-96231b3b80d8

Add bunch of reg-imm movs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75921 91177308-0d34-0410-b5e6-96231b3b80d8

Proper match halfword-imm operands for mov and add

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75920 91177308-0d34-0410-b5e6-96231b3b80d8

Provide masked reg-imm 'or' and 'and'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75919 91177308-0d34-0410-b5e6-96231b3b80d8

Fix test running lines

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75918 91177308-0d34-0410-b5e6-96231b3b80d8

Add reg-reg and pattern

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75917 91177308-0d34-0410-b5e6-96231b3b80d8

Add sub reg-reg pattern

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75916 91177308-0d34-0410-b5e6-96231b3b80d8

Add xor reg-reg pattern

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75915 91177308-0d34-0410-b5e6-96231b3b80d8

Add or reg-reg pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75914 91177308-0d34-0410-b5e6-96231b3b80d8

Add add reg-reg and reg-imm patterns

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75913 91177308-0d34-0410-b5e6-96231b3b80d8

Add simple reg-reg and reg-imm moves

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75912 91177308-0d34-0410-b5e6-96231b3b80d8

Minimal lowering for formal_arguments / ret

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75911 91177308-0d34-0410-b5e6-96231b3b80d8

Add testsuite dir for systemz stuff

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75910 91177308-0d34-0410-b5e6-96231b3b80d8

Let's start another backend :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75909 91177308-0d34-0410-b5e6-96231b3b80d8

Combine an unaligned store of unaligned load into a memmove.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75908 91177308-0d34-0410-b5e6-96231b3b80d8

Lower the threshold at which memcpy / memmove / memset stop being expanded
inline in the XCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75906 91177308-0d34-0410-b5e6-96231b3b80d8

Fix typo in last commit on expansion of unaligned loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75903 91177308-0d34-0410-b5e6-96231b3b80d8

Expand unaligned 32 bit loads from an address which is a constant
offset from a 32 bit aligned base as follows:

  ldw low, base[offset >> 2]
  ldw high, base[(offset >> 2) + 1]
  shr low_shifted, low, (offset & 0x3) * 8
  shl high_shifted, high, 32 - (offset & 0x3) * 8
  or result, low_shifted, high_shifted

Expand 32 bit loads / stores with 16 bit alignment into two 16 bit
loads / stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75902 91177308-0d34-0410-b5e6-96231b3b80d8

Custom lower unaligned 32 bit stores and loads into libcalls. This is
a big code size win since before they were expanding to upto 16
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75901 91177308-0d34-0410-b5e6-96231b3b80d8

Let callers decide the sub-register index on the def operand of rematerialized instructions.
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8

use SUBREG_TO_REG instead of INSERT_SUBREG, this way the code
generator can know the top bits are zero, not undefined.
Thanks to Dan for pointing this out.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75899 91177308-0d34-0410-b5e6-96231b3b80d8

Fix coding style issues pointed by Bill.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75898 91177308-0d34-0410-b5e6-96231b3b80d8

add a knob to turn off PrettyStackTrace globally.  Patch by Zoltan
Varga!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75897 91177308-0d34-0410-b5e6-96231b3b80d8

implement .include in the lexer/parser instead of passing it into the streamer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75896 91177308-0d34-0410-b5e6-96231b3b80d8

fix some casts that I improperly refactored, patch by Artur Pietrek!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75894 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unused header.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75893 91177308-0d34-0410-b5e6-96231b3b80d8

Kill off last uses of TargetMachineRegistry class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75892 91177308-0d34-0410-b5e6-96231b3b80d8

Fix gcc 4.0 build failure, can't rely on access inside nested friended class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75891 91177308-0d34-0410-b5e6-96231b3b80d8

Switch llc and createJIT to use simpler command line parsing for -march.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75890 91177308-0d34-0410-b5e6-96231b3b80d8

Add registered target list to --version output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75889 91177308-0d34-0410-b5e6-96231b3b80d8

Make sure targets are initialized before we do anything, even command line
processing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75888 91177308-0d34-0410-b5e6-96231b3b80d8