Simplify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135127 91177308-0d34-0410-b5e6-96231b3b80d8

Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135126 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify and delay extracting DebugLoc elements, scope and InlinedAt, as much as possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135124 91177308-0d34-0410-b5e6-96231b3b80d8

Add a dag combine pattern for folding C2-(A+C1) -> (C2-C1)-A

Fixes rdar://9761830

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135123 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r135121 which broke a gcc-4.2 builder.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135122 91177308-0d34-0410-b5e6-96231b3b80d8

Count references to interference cache entries.

Each InterferenceCache::Cursor instance references a cache entry. A
non-zero reference count guarantees that the entry won't be reused for a
new register.

This makes it possible to have multiple live cursors examining
interference for different physregs.

The total number of live cursors into a cache must be kept below
InterferenceCache::getMaxCursors().

Code generation should be unaffected by this change, and it doesn't seem
to affect the cache replacement strategy either.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135121 91177308-0d34-0410-b5e6-96231b3b80d8

Fix up assertion in r135018 so it doesn't trigger on 32-bit; when we're in 32-bit, it doesn't matter whether the operation overflows because the computed address is not wider than the immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135120 91177308-0d34-0410-b5e6-96231b3b80d8

ARM tests for EOR instruction parsing and encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135119 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify. Compile unit check inside hasValidLocation() did not add any value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135118 91177308-0d34-0410-b5e6-96231b3b80d8

Remove duplicate tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135117 91177308-0d34-0410-b5e6-96231b3b80d8

ARM Assembler support for DSB instruction.

Add instalias for default 'sy' option. Add tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135116 91177308-0d34-0410-b5e6-96231b3b80d8

Reapply r135074 and r135080 with a fix.

The cache entry referenced by the best split candidate could become
clobbered by an unsuccessful candidate.

The correct fix here is to use reference counts on the cache entries.
Coming up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135113 91177308-0d34-0410-b5e6-96231b3b80d8

DMB instalias needs the same predicate as the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135112 91177308-0d34-0410-b5e6-96231b3b80d8

Fix typo in DEBUG message.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135111 91177308-0d34-0410-b5e6-96231b3b80d8

Add DEBUG messages.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135110 91177308-0d34-0410-b5e6-96231b3b80d8

ARM Assembler support for DMB instruction.

Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135109 91177308-0d34-0410-b5e6-96231b3b80d8

Update comments. These are for assembler, too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135107 91177308-0d34-0410-b5e6-96231b3b80d8

Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode.  Switch ARM over to using that rather than its own special MCInstrDesc bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135106 91177308-0d34-0410-b5e6-96231b3b80d8

Add code to handle a "frameless" unwind stack.

The frameless unwind stack has a special encoding, the algorithm for which is in
"permuteEncode".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135103 91177308-0d34-0410-b5e6-96231b3b80d8

ARM Assembler support for DBG instruction.

Add range checking and testing for parsing and encoding of DBG instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135102 91177308-0d34-0410-b5e6-96231b3b80d8

We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135099 91177308-0d34-0410-b5e6-96231b3b80d8

ARM parsing and encoding tests for CMN/CMP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135098 91177308-0d34-0410-b5e6-96231b3b80d8

struct Init -> class Init

Rename struct Init to class Init for consistency and in preparation
for making Init a FoldingSetNode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135097 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r135074 and r135080. They broke clamscan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135096 91177308-0d34-0410-b5e6-96231b3b80d8

Shuffle ARM assembly tests a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135095 91177308-0d34-0410-b5e6-96231b3b80d8

Revert 135093. Think-o.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135094 91177308-0d34-0410-b5e6-96231b3b80d8

Correct range for thumb co-processor immediate

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135093 91177308-0d34-0410-b5e6-96231b3b80d8

Range checking for CDP[2] immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8

Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more
general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135088 91177308-0d34-0410-b5e6-96231b3b80d8

The target specific node PANDN name is misleading. That happens because
it's later selected to a ANDNPD/ANDNPS instruction instead of the PANDN
instruction. Rename it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135087 91177308-0d34-0410-b5e6-96231b3b80d8

Cleanup Thumb co-processor instructions a bit.

Combine redundant base classes and such. No indended functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135085 91177308-0d34-0410-b5e6-96231b3b80d8

Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64.  It can overflow, leading to a crash/miscompile.

<rdar://problem/9763308>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135084 91177308-0d34-0410-b5e6-96231b3b80d8

Parameterize away the ARM T1Cop class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135082 91177308-0d34-0410-b5e6-96231b3b80d8

Fix predicates for Thumb co-processor instructions.

They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135081 91177308-0d34-0410-b5e6-96231b3b80d8

Only keep the global split candidates that work out.

Some pysical registers create split solutions that would spill anywhere.
They should not even be considered in future multi-way global splits.

This does not affect code generation (yet).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135080 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor out checking for displacements on x86-64 addressing modes.  No functionality change.  Refactoring in preparation for an additional safety check in FoldOffsetIntoAddress.

Part of <rdar://problem/9763308>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135079 91177308-0d34-0410-b5e6-96231b3b80d8

Testcases for ARM assembly BX/BXJ instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135078 91177308-0d34-0410-b5e6-96231b3b80d8

Fix encoding for ARM BXJ instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135077 91177308-0d34-0410-b5e6-96231b3b80d8

Fix encoding of predicate bits on ARM BX_pred.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135076 91177308-0d34-0410-b5e6-96231b3b80d8

Move the InterferenceCache cursor into the GlobalSplitCand struct.

This is in preparation of supporting multiple global split candidates in
a single live range split operation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135074 91177308-0d34-0410-b5e6-96231b3b80d8

Testcases for ARM assembly BLX/BL instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135072 91177308-0d34-0410-b5e6-96231b3b80d8

Range checking for 16-bit immediates in ARM assembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135071 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r135042. As Chris pointed out, it had no effect, and was based on
a complete misunderstanding of the code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135070 91177308-0d34-0410-b5e6-96231b3b80d8

Fix up TargetLoweringObjectFile ctors to properly initialize fields.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135068 91177308-0d34-0410-b5e6-96231b3b80d8

Give the ARM BKPT instruction the right operand type.

The immediate is of limited range and the operand type should reflect that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135066 91177308-0d34-0410-b5e6-96231b3b80d8

Change test case, one that actually failed before my commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135064 91177308-0d34-0410-b5e6-96231b3b80d8

Add tests for ARM parsing of 'BKPT' instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135063 91177308-0d34-0410-b5e6-96231b3b80d8

Fix copy-pasto.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135062 91177308-0d34-0410-b5e6-96231b3b80d8

Add tests for ARM parsing of 'BIC' instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135061 91177308-0d34-0410-b5e6-96231b3b80d8

Add some FIXMEs.

Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135060 91177308-0d34-0410-b5e6-96231b3b80d8

Revert accidental commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135059 91177308-0d34-0410-b5e6-96231b3b80d8

It's not safe to fold (fptrunc (sqrt (fpext x))) to (sqrtf x) if there is another use of sqrt. rdar://9763193

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135058 91177308-0d34-0410-b5e6-96231b3b80d8

Add tests for ARM parsing of 'AND' instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135056 91177308-0d34-0410-b5e6-96231b3b80d8

Improve ARM assembly parsing diagnostics a bit.

Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.

Add some tests for the diagnostics we do want.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135055 91177308-0d34-0410-b5e6-96231b3b80d8

Add tests for ARM parsing of 'ADD' instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135053 91177308-0d34-0410-b5e6-96231b3b80d8

Destination register operand is optional for ADC and SBC ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135052 91177308-0d34-0410-b5e6-96231b3b80d8

Flesh out ARM Parser support for shifted-register operands.

Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135049 91177308-0d34-0410-b5e6-96231b3b80d8

80 columns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135047 91177308-0d34-0410-b5e6-96231b3b80d8

Update MCParsedAsmOperand debug methods.

Update the debug output interface for MCParsedAsmOperand to have a print()
method which takes an output stream argument, an << operator which invokes
the print method using the given stream, and a dump() method which prints
the operand to the dbgs() stream. This makes the interface more consistent
with the rest of LLVM, and more convenient to use at the debugger command
line.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135043 91177308-0d34-0410-b5e6-96231b3b80d8

Really cache function types and anonymous struct types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135042 91177308-0d34-0410-b5e6-96231b3b80d8

Convert InsertValueInst and ExtractValueInst APIs to use ArrayRef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135040 91177308-0d34-0410-b5e6-96231b3b80d8

Add some bits that I found useful when converting InsertValueInst and
ExtractValueInst APIs to use ArrayRef: a new constructor taking a
(begin, end) range, and operators == and != for element-wise comparison.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135039 91177308-0d34-0410-b5e6-96231b3b80d8

Add to RuntimeDyld support different object formats

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135037 91177308-0d34-0410-b5e6-96231b3b80d8

stop leaking all named struct types with an empty name.  Thanks
to Benjamin Kramer for steering me in the right direction here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135031 91177308-0d34-0410-b5e6-96231b3b80d8

Add an entry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135024 91177308-0d34-0410-b5e6-96231b3b80d8

AVX Codegen support for 256-bit versions of vandps, vandpd, vorps, vorpd, vxorps, vxorpd

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135023 91177308-0d34-0410-b5e6-96231b3b80d8

Don't emit the FDE end label if the last thing emitted was a compact unwind and
not the FDE

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135020 91177308-0d34-0410-b5e6-96231b3b80d8

Add an assert (which should never trigger) that triggers on a testcase I'm looking at.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135018 91177308-0d34-0410-b5e6-96231b3b80d8

Improve codegen for select's:
if (x != 0) x = 1
if (x == 1) x = 1

Previous codegen looks like this:
        mov     r1, r0
        cmp     r1, #1
        mov     r0, #0
        moveq   r0, #1

The naive lowering select between two different values. It should recognize the
test is equality test so it's more a conditional move rather than a select:
        cmp     r0, #1
        movne   r0, #0

rdar://9758317

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135017 91177308-0d34-0410-b5e6-96231b3b80d8

Assign variable before we test it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135015 91177308-0d34-0410-b5e6-96231b3b80d8

Fix obvious think-o.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135014 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up the handling of an EBP/RBP unwind frame pointer. In particular, don't
assert when the frame pointer is -1 (i.e., the function is "frameless").

Still to do: "frameless" unwind information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135013 91177308-0d34-0410-b5e6-96231b3b80d8

There is a cyclic dependency between MC and Target if this method is out-of-line.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135006 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the const from Type after of Jay deconstify work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135000 91177308-0d34-0410-b5e6-96231b3b80d8

Delete StructType bodies when destroying a StructType.

Leak found by valgrind.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134994 91177308-0d34-0410-b5e6-96231b3b80d8

Add check for predicate w/o S bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134987 91177308-0d34-0410-b5e6-96231b3b80d8

Improve test cases from r134746.

Use memory barriers to force if-conversion off for these tests instead of
the internal llc command line option ifcvt-limit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134986 91177308-0d34-0410-b5e6-96231b3b80d8

Reverted 134901 because of 134959. Did not use svn merge -r but rather:

1,$s/llvm::Type::getInt\(..\)Ty(builder.getContext())/builder.getInt\1Ty()/g
1,$s/builder.getInt\(..*\)Ty()->getPointerTo()/builder.getInt\1PtrTy()/g

vi sub commands (second one was not a reversion but requested by
Tobias Grosser.

Mod was tested, but other examples have failed to build as they are currently
being thrashed with the const qualifier removal change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134985 91177308-0d34-0410-b5e6-96231b3b80d8

Second attempt at de-constifying LLVM Types in FunctionType::get(),
StructType::get() and TargetData::getIntPtrType().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134982 91177308-0d34-0410-b5e6-96231b3b80d8

VectorType is also a SequentialType

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134979 91177308-0d34-0410-b5e6-96231b3b80d8

Remove IntegerType constness from TargetData

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134978 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the BrainF build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134975 91177308-0d34-0410-b5e6-96231b3b80d8

simplify assertions to not be completely redundant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134968 91177308-0d34-0410-b5e6-96231b3b80d8

make the IRBuilder type methods return non-const types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134959 91177308-0d34-0410-b5e6-96231b3b80d8

Comment correction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134958 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r134893 and r134888 (and related patches in other trees). It was causing
an assert on Darwin llvm-gcc builds.

Assertion failed: (castIsValid(op, S, Ty) && "Invalid cast!"), function Create, file /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.llvm-gcc-i386-darwin9-RA/llvm.src/lib/VMCore/Instructions.cpp, li\
ne 2067.
etc.

http://smooshlab.apple.com:8013/builders/llvm-gcc-i386-darwin9-RA/builds/2354

--- Reverse-merging r134893 into '.':
U    include/llvm/Target/TargetData.h
U    include/llvm/DerivedTypes.h
U    tools/bugpoint/ExtractFunction.cpp
U    unittests/Support/TypeBuilderTest.cpp
U    lib/Target/ARM/ARMGlobalMerge.cpp
U    lib/Target/TargetData.cpp
U    lib/VMCore/Constants.cpp
U    lib/VMCore/Type.cpp
U    lib/VMCore/Core.cpp
U    lib/Transforms/Utils/CodeExtractor.cpp
U    lib/Transforms/Instrumentation/ProfilingUtils.cpp
U    lib/Transforms/IPO/DeadArgumentElimination.cpp
U    lib/CodeGen/SjLjEHPrepare.cpp
--- Reverse-merging r134888 into '.':
G    include/llvm/DerivedTypes.h
U    include/llvm/Support/TypeBuilder.h
U    include/llvm/Intrinsics.h
U    unittests/Analysis/ScalarEvolutionTest.cpp
U    unittests/ExecutionEngine/JIT/JITTest.cpp
U    unittests/ExecutionEngine/JIT/JITMemoryManagerTest.cpp
U    unittests/VMCore/PassManagerTest.cpp
G    unittests/Support/TypeBuilderTest.cpp
U    lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp
U    lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp
U    lib/VMCore/IRBuilder.cpp
G    lib/VMCore/Type.cpp
U    lib/VMCore/Function.cpp
G    lib/VMCore/Core.cpp
U    lib/VMCore/Module.cpp
U    lib/AsmParser/LLParser.cpp
U    lib/Transforms/Utils/CloneFunction.cpp
G    lib/Transforms/Utils/CodeExtractor.cpp
U    lib/Transforms/Utils/InlineFunction.cpp
U    lib/Transforms/Instrumentation/GCOVProfiling.cpp
U    lib/Transforms/Scalar/ObjCARC.cpp
U    lib/Transforms/Scalar/SimplifyLibCalls.cpp
U    lib/Transforms/Scalar/MemCpyOptimizer.cpp
G    lib/Transforms/IPO/DeadArgumentElimination.cpp
U    lib/Transforms/IPO/ArgumentPromotion.cpp
U    lib/Transforms/InstCombine/InstCombineCompares.cpp
U    lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
U    lib/Transforms/InstCombine/InstCombineCalls.cpp
U    lib/CodeGen/DwarfEHPrepare.cpp
U    lib/CodeGen/IntrinsicLowering.cpp
U    lib/Bitcode/Reader/BitcodeReader.cpp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134949 91177308-0d34-0410-b5e6-96231b3b80d8

TypeMap had a destructor that destroyed the types it held. DenseMap did not, so
destroy those types in ~LLVMContext.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134945 91177308-0d34-0410-b5e6-96231b3b80d8

indvars: Code reorganization in preparation for
LinearFunctionTestReplace rewrite. No functionality.

I've been wanting to group the indvar subphases into sections and
order them by their logical sequence. My next checkin adds functions
related to LFTR, and doing the reorg now should help reviewers. Since,
most of the code in IndVarSimplify.cpp has recently been replaced or
will be replaced soon, obscuring blame should not be an issue. This
seems like an ideal time to shuffle the code around.

I'm happy to take more suggestions for cleaning up the code. Or if
you've been wanting to cleanup anything in this file yourself, now is
a good time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134941 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r134921, 134917, 134908 and 134907. They're causing failures
in multiple buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134936 91177308-0d34-0410-b5e6-96231b3b80d8

fix some examples

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134933 91177308-0d34-0410-b5e6-96231b3b80d8

Fix LTO after the recent MC subtarget refactoring.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134930 91177308-0d34-0410-b5e6-96231b3b80d8

Most MCCodeEmitter's don't meed MCContext.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134922 91177308-0d34-0410-b5e6-96231b3b80d8

Use get(0 Instead of Create()

Respond to some feedback asking for a name change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134921 91177308-0d34-0410-b5e6-96231b3b80d8

Disassembler doesn't need TargetMachine anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134920 91177308-0d34-0410-b5e6-96231b3b80d8

struct Init -> class Init.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134917 91177308-0d34-0410-b5e6-96231b3b80d8

Fix Build

Update the tag for Init to match how it's defined.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134908 91177308-0d34-0410-b5e6-96231b3b80d8

[AVX] Make Inits Foldable

Manage Inits in a FoldingSet.  This provides several benefits:

- Memory for Inits is properly managed

- Duplicate Inits are folded into Flyweights, saving memory

- It enforces const-correctness, protecting against certain classes
  of bugs

The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen.  This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134907 91177308-0d34-0410-b5e6-96231b3b80d8

Resynchronize EDInfo.h and EDEmitter.cpp.
The enum names as well as order (i.e. value)
had skewed, which means that consumers of the
tablegen-ed table would see different values than
intended. Make both files have a superset of enums,
and add classification as needed for numMCOperands.

Reviewed by Owen Anderson

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134905 91177308-0d34-0410-b5e6-96231b3b80d8

Fix recognition of ARM 'adcs' mnemonic.

The 'CS' is not a predication suffix in this case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134903 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify printing of ARM shifted immediates.

Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
 displayed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134902 91177308-0d34-0410-b5e6-96231b3b80d8