Nadav Rotem [Thu, 12 Jul 2012 13:45:15 +0000 (13:45 +0000)]
The LIT tests below do not specify the exact cpu model and fail on AVX2 machines, because we select different instructions such as vbroadcast, new shuffles, etc.
Patch by Michael Liao.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160129
91177308-0d34-0410-b5e6-
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Gabor Greif [Thu, 12 Jul 2012 13:18:13 +0000 (13:18 +0000)]
detabify
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160128
91177308-0d34-0410-b5e6-
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Gabor Greif [Thu, 12 Jul 2012 13:05:12 +0000 (13:05 +0000)]
fix typo in generated comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160127
91177308-0d34-0410-b5e6-
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NAKAMURA Takumi [Thu, 12 Jul 2012 10:22:57 +0000 (10:22 +0000)]
llvm/test/CodeGen/X86/rdrand.ll: Relax expression corresponding to Win64 CC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160124
91177308-0d34-0410-b5e6-
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NAKAMURA Takumi [Thu, 12 Jul 2012 10:15:48 +0000 (10:15 +0000)]
llvm/test/CMakeLists.txt: Add llvm-diff to deps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160123
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Benjamin Kramer [Thu, 12 Jul 2012 09:36:29 +0000 (09:36 +0000)]
Use %s instead of the explicit name, the latter doesn't work in out-of-tree builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160120
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Thu, 12 Jul 2012 09:31:43 +0000 (09:31 +0000)]
Add intrinsics for Ivy Bridge's rdrand instruction.
The rdrand/cmov sequence is the same that is emitted by both
GCC and ICC.
Fixes PR13284.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160117
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Duncan Sands [Thu, 12 Jul 2012 09:01:35 +0000 (09:01 +0000)]
The result type of EXTRACT_VECTOR_ELT doesn't have to match the element type of
the input vector, it can be bigger (this is helpful for powerpc where <2 x i16>
is a legal vector type but i16 isn't a legal type, IIRC). However this wasn't
being taken into account by ExpandRes_EXTRACT_VECTOR_ELT, causing PR13220.
Lightly tweaked version of a patch by Michael Liao.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160116
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Craig Topper [Thu, 12 Jul 2012 06:52:41 +0000 (06:52 +0000)]
Update GATHER instructions to support 2 read-write operands. Patch from myself and Manman Ren.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160110
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Evan Cheng [Thu, 12 Jul 2012 01:45:35 +0000 (01:45 +0000)]
Instcombine was transforming:
%shr = lshr i64 %key, 3
%0 = load i64* %val, align 8
%sub = add i64 %0, -1
%and = and i64 %sub, %shr
ret i64 %and
to:
%shr = lshr i64 %key, 3
%0 = load i64* %val, align 8
%sub = add i64 %0,
2305843009213693951
%and = and i64 %sub, %shr
ret i64 %and
The demanded bit optimization is actually a pessimization because add -1 would
be codegen'ed as a sub 1. Teach the demanded constant shrinking optimization
to check for negated constant to make sure it is actually reducing the width
of the constant.
rdar://
11793464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160101
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Jim Grosbach [Thu, 12 Jul 2012 00:53:31 +0000 (00:53 +0000)]
TableGen: Location information for diagnostic.
def Pat<...>;
Results in 'record name is not a string!' diagnostic. Not the best,
but the lack of location information moves it from not very helpful
into completely useless. We're in the Record class when throwing the
error, so just add the location info directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160098
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Manman Ren [Wed, 11 Jul 2012 23:47:00 +0000 (23:47 +0000)]
ARM: fix typo in comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160093
91177308-0d34-0410-b5e6-
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Manman Ren [Wed, 11 Jul 2012 22:51:44 +0000 (22:51 +0000)]
ARM: Fix optimizeCompare to correctly check safe condition.
It is safe if CPSR is killed or re-defined.
When we are done with the basic block, check whether CPSR is live-out.
Do not optimize away cmp if CPSR is live-out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160090
91177308-0d34-0410-b5e6-
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Jack Carter [Wed, 11 Jul 2012 22:17:39 +0000 (22:17 +0000)]
Patch for Mips direct object generation.
When WriteFragmentData() case FT_align called
Asm.getBackend().writeNopData() is called, nothing
is done since Mips implementation of writeNopData just
returned "true".
For some reason this has not caused problems in 32 bit
mode, but in 64 bit mode it caused an assert when processing
multiple function units.
The test case included will assert without this patch. It
runs twice with different flags to prevent false positives
due to changes in code generation over time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160084
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Chad Rosier [Wed, 11 Jul 2012 21:49:14 +0000 (21:49 +0000)]
Fixup broken doc link. Patch by Sean Silva <silvas@purdue.edu>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160082
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Jack Carter [Wed, 11 Jul 2012 21:41:49 +0000 (21:41 +0000)]
This change removes an "initialization" warning.
Even though variable in question could not
be initialized before use, the code was such that
the compiler had no way of knowing that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160081
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Stepan Dyatkovskiy [Wed, 11 Jul 2012 21:02:57 +0000 (21:02 +0000)]
Fixed diff comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160076
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Argyrios Kyrtzidis [Wed, 11 Jul 2012 20:59:20 +0000 (20:59 +0000)]
In MemoryBuffer::getOpenFile() don't verify that the mmap'ed
file buffer is null-terminated.
If the file is smaller than we thought, mmap will not allow dereferencing
past the pages that are enough to cover the actual file size,
even though we asked for a larger address range.
rdar://
11612916
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160075
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Akira Hatanaka [Wed, 11 Jul 2012 20:51:50 +0000 (20:51 +0000)]
In register classes in MipsRegisterInfo.td, list the registers in ascending
order of binary encoding.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160073
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Chad Rosier [Wed, 11 Jul 2012 19:58:38 +0000 (19:58 +0000)]
[x86 fast-isel] Per discussion with Eric, add all cases to switch with verbose
comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160069
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Akira Hatanaka [Wed, 11 Jul 2012 19:50:46 +0000 (19:50 +0000)]
Test case for r160036.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160067
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Manman Ren [Wed, 11 Jul 2012 19:35:12 +0000 (19:35 +0000)]
X86: Update to peephole optimization to move Movr0 before (Sub, Cmp) pair.
When Movr0 is between sub and cmp, we move Movr0 before sub if it enables
removal of Cmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160066
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Akira Hatanaka [Wed, 11 Jul 2012 19:32:27 +0000 (19:32 +0000)]
Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160064
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Evan Cheng [Wed, 11 Jul 2012 18:55:07 +0000 (18:55 +0000)]
InstrEmitter::EmitSubregNode() optimize extract_subreg in this case:
r1025 = s/zext r1024, 4
r1026 = extract_subreg r1025, 4
to a copy:
r1026 = copy r1024
This is correct. However it uses TII->isCoalescableExtInstr() which can return
true for instructions which essentially does a sext_in_reg so this can end up
with an illegal copy where the source and destination register classes do not
match. Add a check to avoid it. Sorry, no test case possible at this time.
rdar://
11849816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160059
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Wed, 11 Jul 2012 18:31:59 +0000 (18:31 +0000)]
PR13326: Fix a subtle edge case in the udiv -> magic multiply generator.
This caused 6 of 65k possible 8 bit udivs to be wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160058
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Tom Stellard [Wed, 11 Jul 2012 17:34:12 +0000 (17:34 +0000)]
test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160056
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Chad Rosier [Wed, 11 Jul 2012 17:23:17 +0000 (17:23 +0000)]
[x86 fast-isel] Rather then call llvm_unreachable() have fast-isel fall back
to Selection DAG isel. Patch by Andrew Kaylor <andrew.kaylor@intel.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160055
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Nadav Rotem [Wed, 11 Jul 2012 13:27:05 +0000 (13:27 +0000)]
When ext-loading and trunc-storing vectors to memory, on x86 32bit systems, allow loads/stores of 64bit values from xmm registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160044
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Nadav Rotem [Wed, 11 Jul 2012 11:02:16 +0000 (11:02 +0000)]
Rename many of the Tmp1, Tmp2, Tmp3 variables to names such as Chain, Value, Ptr, etc.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160042
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Benjamin Kramer [Wed, 11 Jul 2012 09:39:04 +0000 (09:39 +0000)]
Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160040
91177308-0d34-0410-b5e6-
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Nadav Rotem [Wed, 11 Jul 2012 08:52:09 +0000 (08:52 +0000)]
Refactor the DAG Legalizer by extracting the legalization of
Load and Store nodes into their own functions.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160037
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Owen Anderson [Wed, 11 Jul 2012 06:38:55 +0000 (06:38 +0000)]
Only apply the SETCC+SITOFP -> SELECTCC optimization when the SETCC returns an MVT::i1, i.e. before type legalization.
This is a speculative fix for a problem on Mips reported by Akira Hatanaka.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160036
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Akira Hatanaka [Wed, 11 Jul 2012 00:53:32 +0000 (00:53 +0000)]
Lower RETURNADDR node in Mips backend.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160031
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Jack Carter [Tue, 10 Jul 2012 22:41:20 +0000 (22:41 +0000)]
Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands
are defined by the name of the variable they are marked with in
the inline assembler code. This is a way to specify that the
operand just refers to the low order register for that variable.
It is the opposite of modifier 'D' which specifies the high order
register.
Example:
main()
{
long long ll_input = 0x1111222233334444LL;
long long ll_val = 3;
int i_result = 0;
__asm__ __volatile__(
"or %0, %L1, %2"
: "=r" (i_result)
: "r" (ll_input), "r" (ll_val));
}
Which results in:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -8
addu $2, $2, $25
sw $2, 0($sp)
lui $2, 13107
ori $3, $2, 17476 <-- Low 32 bits of ll_input
lui $2, 4369
ori $4, $2, 8738 <-- High 32 bits of ll_input
addiu $5, $zero, 3 <-- Low 32 bits of ll_val
addiu $2, $zero, 0 <-- High 32 bits of ll_val
#APP
or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val
#NO_APP
addiu $sp, $sp, 8
jr $ra
If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.
There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Tue, 10 Jul 2012 22:39:56 +0000 (22:39 +0000)]
Require and preserve LoopInfo for early if-conversion.
It will surely be needed by heuristics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160027
91177308-0d34-0410-b5e6-
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Chandler Carruth [Tue, 10 Jul 2012 22:25:21 +0000 (22:25 +0000)]
Teach the LiveInterval::join function to use the fast merge algorithm,
generalizing its implementation sufficiently to support this value
number scenario as well.
This cuts out another significant performance hit in large functions
(over 10k basic blocks, etc), especially those with "natural" CFG
structures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160026
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Tue, 10 Jul 2012 22:18:23 +0000 (22:18 +0000)]
Run early if-conversion in domtree post-order.
This ordering allows nested if-conversion without using a work list, and
it makes it possible to update the dominator tree on the fly as well.
Any erased basic blocks will always be dominated by the current
post-order position, so the domtree can be pruned without invalidating
the iterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160025
91177308-0d34-0410-b5e6-
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Chad Rosier [Tue, 10 Jul 2012 18:27:15 +0000 (18:27 +0000)]
Move [get|set]BasePtrStackAdjustment() from MachineFrameInfo to
X86MachineFunctionInfo as this is currently only used by X86. If this ever
becomes an issue on another arch (e.g., ARM) then we can hoist it back out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160009
91177308-0d34-0410-b5e6-
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Chad Rosier [Tue, 10 Jul 2012 17:57:00 +0000 (17:57 +0000)]
Add newline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160006
91177308-0d34-0410-b5e6-
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Chad Rosier [Tue, 10 Jul 2012 17:49:39 +0000 (17:49 +0000)]
Add test case accidentally omitted from r160002.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160004
91177308-0d34-0410-b5e6-
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Chad Rosier [Tue, 10 Jul 2012 17:45:53 +0000 (17:45 +0000)]
Add support for dynamic stack realignment in the presence of dynamic allocas on
X86. Basically, this is a reapplication of r158087 with a few fixes.
Specifically, (1) the stack pointer is restored from the base pointer before
popping callee-saved registers and (2) in obscure cases (see comments in patch)
we must cache the value of the original stack adjustment in the prologue and
apply it in the epilogue.
rdar://
11496434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160002
91177308-0d34-0410-b5e6-
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Chandler Carruth [Tue, 10 Jul 2012 15:41:33 +0000 (15:41 +0000)]
Fix a bug where I didn't test for an empty range before inspecting the
back of it.
I don't have anything even remotely close to a test case for this. It
only broke two build bots, both of them doing bootstrap builds, one of
them a dragonegg bootstrap. It doesn't break for me when I bootstrap
either. It doesn't reproduce every time or on many machines during the
bootstrap. Many thanks to Duncan Sands who got the exact command (and
stage of the bootstrap) which failed on the dragonegg bootstrap and
managed to get it to trigger under valgrind with debug symbols. The fix
was then found by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159993
91177308-0d34-0410-b5e6-
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Nadav Rotem [Tue, 10 Jul 2012 13:25:08 +0000 (13:25 +0000)]
Improve the loading of load-anyext vectors by allowing the codegen to load
multiple scalars and insert them into a vector. Next, we shuffle the elements
into the correct places, as before.
Also fix a small dagcombine bug in SimplifyBinOpWithSameOpcodeHands, when the
migration of bitcasts happened too late in the SelectionDAG process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159991
91177308-0d34-0410-b5e6-
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Richard Barton [Tue, 10 Jul 2012 12:51:09 +0000 (12:51 +0000)]
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989
91177308-0d34-0410-b5e6-
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Craig Topper [Tue, 10 Jul 2012 06:38:33 +0000 (06:38 +0000)]
Reverse assembler/disassembler operand order for gather instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159983
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Tue, 10 Jul 2012 05:16:17 +0000 (05:16 +0000)]
Add an efficient merge operation to LiveInterval and use it to avoid
quadratic behavior when performing pathological merges. Fixes the core
element of PR12652.
There is only one user of addRangeFrom left: join. I'm hoping to
refactor further in a future patch and have join use this merge
operation as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159982
91177308-0d34-0410-b5e6-
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Chandler Carruth [Tue, 10 Jul 2012 05:06:03 +0000 (05:06 +0000)]
Teach LiveIntervals how to verify themselves and start using it in some
of the trick merge routines. This adds a layer of testing that was
necessary when implementing more efficient (and complex) merge logic for
this datastructure.
No functionality changed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159981
91177308-0d34-0410-b5e6-
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Jim Grosbach [Tue, 10 Jul 2012 00:51:13 +0000 (00:51 +0000)]
ARM: Allow more flexible patterns in NEON formats.
Some NEON instructions want to match against normal SDNodes for some
operand types and Intrinsics for others. For example, CTLZ. To enable this,
switch from explicitly requiring Intrinsic on the class templates to using
SDPatternOperator instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159974
91177308-0d34-0410-b5e6-
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Jim Grosbach [Tue, 10 Jul 2012 00:51:11 +0000 (00:51 +0000)]
Allow intrinsics to be used in place of node matchables.
TableGen has support for using an intrinics name directly in a DAG,
but this breaks down when referring to just a node, as that's
handled initializer list stuff entirely via subclassing in the
parser. That is, using an instrinsic like "(int_my_intrinsic ...)"
works fine. Using it standalone for parameterizing the operator
in such a DAG does not.
Fixing this is simple enough, as we simply declare Intrinsic
as deriving from SDPatternOperator, which is the class name
intended for exactly this purpose in TargetSelectionDAG.td.
When the intrinsic is actually used in the DAG pattern, it will
be recognized and expanded to an intrinsic_wo_chain (et. al.)
just like when it's used directly.
Incoming ARM NEON cleanup based on this and a bit of functionality
improvement after that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159973
91177308-0d34-0410-b5e6-
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Akira Hatanaka [Tue, 10 Jul 2012 00:19:06 +0000 (00:19 +0000)]
Make register Mips::RA allocatable if not in mips16 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159971
91177308-0d34-0410-b5e6-
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Dan Gohman [Mon, 9 Jul 2012 23:51:20 +0000 (23:51 +0000)]
Delete code for folding undefs in ScalarEvolution. It's invalid in
obscure ways, and it isn't actually important in the real world.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159969
91177308-0d34-0410-b5e6-
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Chad Rosier [Mon, 9 Jul 2012 20:43:34 +0000 (20:43 +0000)]
Revert r159938 (and r159945) to appease the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960
91177308-0d34-0410-b5e6-
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Andrew Trick [Mon, 9 Jul 2012 20:43:03 +0000 (20:43 +0000)]
Machine model: allow itineraries to be shared by different processor models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159959
91177308-0d34-0410-b5e6-
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Andrew Trick [Mon, 9 Jul 2012 20:43:01 +0000 (20:43 +0000)]
indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159958
91177308-0d34-0410-b5e6-
96231b3b80d8
Owen Anderson [Mon, 9 Jul 2012 20:31:12 +0000 (20:31 +0000)]
Teach the DAG combiner to turn sitofp/uitofp from i1 into a conditional move, since there are only two possible values.
Previously, this would become an integer extension operation, followed by a real integer->float conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159957
91177308-0d34-0410-b5e6-
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Manman Ren [Mon, 9 Jul 2012 18:57:12 +0000 (18:57 +0000)]
X86: implement functions to analyze & synthesize CMOV|SET|Jcc
getCondFromSETOpc, getCondFromCMovOpc, getSETFromCond, getCMovFromCond
No functional change intended.
If we want to update the condition code of CMOV|SET|Jcc, we first analyze the
opcode to get the condition code, then update the condition code, finally
synthesize the new opcode form the new condition code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159955
91177308-0d34-0410-b5e6-
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Akira Hatanaka [Mon, 9 Jul 2012 18:46:47 +0000 (18:46 +0000)]
Reapply r158846.
Access mips register classes via MCRegisterInfo's functions instead of via the
TargetRegisterClasses defined in MipsGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953
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Nuno Lopes [Mon, 9 Jul 2012 18:38:20 +0000 (18:38 +0000)]
instcombine: merge the functions that remove dead allocas and dead mallocs/callocs/...
This patch removes ~70 lines in InstCombineLoadStoreAlloca.cpp and makes both functions a bit more aggressive than before :)
In theory, we can be more aggressive when removing an alloca than a malloc, because an alloca pointer should never escape, but we are not taking advantage of this anyway
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159952
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Richard Barton [Mon, 9 Jul 2012 18:30:56 +0000 (18:30 +0000)]
Some formatting to keep Clang happy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159948
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Richard Barton [Mon, 9 Jul 2012 18:20:02 +0000 (18:20 +0000)]
Oops - correct broken disassembly for VMOV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159945
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Richard Barton [Mon, 9 Jul 2012 16:41:33 +0000 (16:41 +0000)]
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938
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Richard Barton [Mon, 9 Jul 2012 16:31:14 +0000 (16:31 +0000)]
Prevent ARM assembler from losing a right shift by #32 applied to a register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159937
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Richard Barton [Mon, 9 Jul 2012 16:14:28 +0000 (16:14 +0000)]
Spelling!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159936
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Richard Barton [Mon, 9 Jul 2012 16:12:24 +0000 (16:12 +0000)]
Teach the assembler to use the narrow thumb encodings of various three-register dp instructions where permissable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159935
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Benjamin Kramer [Sun, 8 Jul 2012 19:47:51 +0000 (19:47 +0000)]
Remove some trivial copy ctors so the classes become trivially copyable and get the optimized SmallVector implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159916
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Benjamin Kramer [Sun, 8 Jul 2012 12:06:35 +0000 (12:06 +0000)]
SmallVector: Make use of move semantics to speed up moving objects in erase() and insert()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159914
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Andrew Trick [Sat, 7 Jul 2012 04:00:00 +0000 (04:00 +0000)]
I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.
MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.
These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.
This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891
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Andrew Trick [Sat, 7 Jul 2012 03:59:51 +0000 (03:59 +0000)]
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159890
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Andrew Trick [Sat, 7 Jul 2012 03:59:48 +0000 (03:59 +0000)]
Tweak spelling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159889
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Manman Ren [Sat, 7 Jul 2012 03:34:46 +0000 (03:34 +0000)]
X86: Fix optimizeCompare to correctly check safe condition.
It is safe if EFLAGS is killed or re-defined.
When we are done with the basic block, check whether EFLAGS is live-out.
Do not optimize away cmp if EFLAGS is live-out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159888
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NAKAMURA Takumi [Sat, 7 Jul 2012 03:12:28 +0000 (03:12 +0000)]
LLVMConfig.cmake.in: Quote around @LLVM_INSTALL_PREFIX@, or it would not accept whitespace paths.
Thanks to Kai.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159887
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Bill Wendling [Sat, 7 Jul 2012 00:52:35 +0000 (00:52 +0000)]
Use the DebugInfo wrappers instead of mucking about with the MDNode directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159881
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Bill Wendling [Fri, 6 Jul 2012 23:43:12 +0000 (23:43 +0000)]
Print the name last.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159879
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Chad Rosier [Fri, 6 Jul 2012 23:13:38 +0000 (23:13 +0000)]
Fix the naming of ensureAlignment. Per the coding standard function names
should be camel case, and start with a lower case letter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159877
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Nuno Lopes [Fri, 6 Jul 2012 23:09:25 +0000 (23:09 +0000)]
teach instcombine to remove allocated buffers even if there are stores, memcpy/memmove/memset, and objectsize users.
This means we can do cheap DSE for heap memory.
Nothing is done if the pointer excapes or has a load.
The churn in the tests is mostly due to objectsize, since we want to make sure we
don't delete the malloc call before evaluating the objectsize (otherwise it becomes -1/0)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159876
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Dmitri Gribenko [Fri, 6 Jul 2012 23:06:47 +0000 (23:06 +0000)]
Since SmallMap was removed in r158644, remove documentation in ProgrammersManual.html.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159874
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Bill Wendling [Fri, 6 Jul 2012 23:06:16 +0000 (23:06 +0000)]
Check if it's a scope last, because several things are scopes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159873
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Jim Grosbach [Fri, 6 Jul 2012 21:52:04 +0000 (21:52 +0000)]
ARM: Add test cleanup entry to the README.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159864
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Akira Hatanaka [Fri, 6 Jul 2012 20:16:48 +0000 (20:16 +0000)]
revert r159851.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159854
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Akira Hatanaka [Fri, 6 Jul 2012 19:29:11 +0000 (19:29 +0000)]
Reapply r158846.
Include file MipsGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159851
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Bill Wendling [Fri, 6 Jul 2012 19:12:31 +0000 (19:12 +0000)]
Add a print method to the ObjC property object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159848
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Bill Wendling [Fri, 6 Jul 2012 17:49:19 +0000 (17:49 +0000)]
Remove trailing comma in array initialization list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159843
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Bill Wendling [Fri, 6 Jul 2012 17:47:36 +0000 (17:47 +0000)]
Remove unnecessary 'llvm::'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159842
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Bill Wendling [Fri, 6 Jul 2012 17:46:28 +0000 (17:46 +0000)]
Remove unnecessary 'llvm::'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159841
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Chad Rosier [Fri, 6 Jul 2012 17:44:22 +0000 (17:44 +0000)]
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159839
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Manman Ren [Fri, 6 Jul 2012 17:36:20 +0000 (17:36 +0000)]
X86: peephole optimization to remove cmp instruction
For each Cmp, we check whether there is an earlier Sub which make Cmp
redundant. We handle the case where SUB operates on the same source operands as
Cmp, including the case where the two source operands are swapped.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159838
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Chad Rosier [Fri, 6 Jul 2012 17:33:39 +0000 (17:33 +0000)]
[fast-isel] Tell fast-isel to do nothing with the new donothing intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159837
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Chad Rosier [Fri, 6 Jul 2012 17:15:03 +0000 (17:15 +0000)]
Update getFunction parameter documentation. Fixes PR13268.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159835
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Dmitri Gribenko [Fri, 6 Jul 2012 16:42:25 +0000 (16:42 +0000)]
Revert r159789.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159834
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NAKAMURA Takumi [Fri, 6 Jul 2012 15:55:39 +0000 (15:55 +0000)]
llvm/include/llvm/CMakeLists.txt: Cut dependency to intrinsics_gen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159831
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Duncan Sands [Fri, 6 Jul 2012 14:43:16 +0000 (14:43 +0000)]
Attempt to fix windows buildbots. Patch by James Benton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159826
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NAKAMURA Takumi [Fri, 6 Jul 2012 12:12:39 +0000 (12:12 +0000)]
test/CodeGen/X86/sext-setcc-self.ll: Mark it as XFAIL: cygwin,mingw32,win32. Investigating.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159820
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NAKAMURA Takumi [Fri, 6 Jul 2012 11:12:44 +0000 (11:12 +0000)]
Revert r159804, "[arm-fast-isel] Add support for vararg function calls."
It broke LLVM :: CodeGen/Thumb2/large-call.ll on several hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159817
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Alexey Samsonov [Fri, 6 Jul 2012 08:45:08 +0000 (08:45 +0000)]
Fix PR13202 and a regtest.
DwarfDebug class could generate the same (inlined) DIVariable twice:
1) when trying to find abstract debug variable for a concrete inlined instance.
2) when explicitly collecting info for variables that were optimized out.
This change makes sure that this duplication won't happen and makes
Clang pass "gdb.opt/inline-locals" test from gdb testsuite.
Reviewed by Eric Christopher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159811
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Bill Wendling [Fri, 6 Jul 2012 05:51:50 +0000 (05:51 +0000)]
Sphinxify the CMake document.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159806
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Jush Lu [Fri, 6 Jul 2012 03:02:37 +0000 (03:02 +0000)]
[arm-fast-isel] Add support for vararg function calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159804
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Jack Carter [Fri, 6 Jul 2012 02:44:22 +0000 (02:44 +0000)]
Changes per review of commit 159787
Mips specific inline asm operand modifier D.
Comment changes and predicate change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159802
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Eric Christopher [Fri, 6 Jul 2012 02:35:57 +0000 (02:35 +0000)]
Untabify and move a function near similar functions dealing with struct
types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159801
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Jakob Stoklund Olesen [Fri, 6 Jul 2012 02:31:22 +0000 (02:31 +0000)]
Add some comments suggested in code review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159800
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Dmitri Gribenko [Fri, 6 Jul 2012 00:25:39 +0000 (00:25 +0000)]
Enable new[] on llvm::BumpPtrAllocator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159789
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