ARM64: dts: rockchip: add power domain node for RK3399 Soc

add pd node for RK3399 Soc
create power domain tree

Change-Id: I5a455034f56b6d88860c3ed2decd8c6dc94896a3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: dts: rockchip: add emmc, sdio and sdmmc node for rk3399

This patch add emmc, sdio and sdmmc node to support
mmc stuff on rk3399 platform.

Change-Id: I717855dded5f5161127ba29e34b9ff2106009c55
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

phy: rockchip-emmc: fix compile issue on arm64 platform

This patch rename "reg" property to "reg_offset".
We rename it to fix the compile issue on ARM64 platform:
(reg_format): "reg" property in /phy has invalid length (4 bytes)
(#address-cells == 2, #size-cells == 2)

This's because "reg" is very special one which should keep the
*-cells with its parent node and can't be overwrited even if we
do that explicitly. On 32-bit plafform, the default *-cells
fit for what we assign to "reg". But that's not correct for 64-bit
platform. So we can see two possible solutions to fix this problem:
A) make phy-rockchip-emmc as a child phy node and overwrite its
parent's #address-cells and #size-cells.
B) avoid using this special property.

we use it just for passing on a offset for different Socs, and there's
no requirement to change the code to make phy-rockchip-emmc as a child
node. so choose option B) is sane.

Change-Id: Ib6a10cb8c3629ec3983854f1bfb7c2426edf79d2
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM64: rockchip_defconfig: enable sdhci controller

Change-Id: Iec8f07c898ed651f662847d0605954f3c356c55e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

pwm: rockchip: add pwm support for rk3399

Change-Id: I0658d1b69b5799c2ef6604563c41b5a0d87ddce2
Signed-off-by: David Wu <david.wu@rock-chips.com>

ARM64: dts: rockchip: add saradc support for rk3399

Change-Id: I786e6efe31a45568d581baf09093f56409c0151f
Signed-off-by: David Wu <david.wu@rock-chips.com>

ARM64: dts: rockchip: add pwm support for rk3399

Change-Id: I243cbf417cf78f39b97e12f66c916502fe72fe31
Signed-off-by: David Wu <david.wu@rock-chips.com>

ARM64: dts: rockchip: add i2c node for rk3399

Change-Id: I3a662d25927fc9c2c4f756963f1522c24fce70d6
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

iio: adc: rockchip_saradc: add saradc support for rk3399

Change-Id: I1d60583f02cc4b4cac8a8a1c1fb22bfeb5e52647
Signed-off-by: David Wu <david.wu@rock-chips.com>

net: rkwifi: Modify driver loading way to reduce boot time

Change-Id: Ie569aeedb5544cb0131ab48818db6a5b0dde05bb
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

ARM64: dts: rk3366-tb: enable nandc

Change-Id: I2b563214e9ad276524f555a31a408c8995cb63a9
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>

arm64: configs: rockchip_defconfig add nand driver

Change-Id: I3bccfe5710c860841714d6e54aa23ed075d5a584
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>

net: rfkill-bt: auto compatible for uart rts control for all uart bt chip

Change-Id: I9b4d6614160285754ee86c427e8918296b92ddbd
Signed-off-by: huweiguo <hwg@rock-chips.com>

ARM64: nand: update nand drvier for 3366

Change-Id: I96ff59f331591807f8d5b009c933a6c71f62a93b
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>

ARM64: rockchip_defconfig: enable rk808 rtc

add CONFIG_RTC_DRV_RK808=y

Change-Id: I7aae9990c9bbf787a7e42e319116df6b4749c3cd
Signed-off-by: Shengfei xu <xsf@rock-chips.com>

UPSTREAM: clk: rockchip: add new pll-type for rk3399 and similar socs

The rk3399's pll and clock are similar with rk3036's, it different
with base on the rk3066(rk3188, rk3288, rk3368 use it), there are
different adjust foctors and control registers, so these should be
independent and separate from the series of rk3066s.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git
v4.7-clk/next commit 95e0c473a0ac1bdac25f55678dc602eb50dae684)

Change-Id: I77872b5fb33eb92402e9036b97b185ea56eb45c6
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: release io resource when failing to init clk

We should call iounmap to relase reg_base since it's not going
to be used any more if failing to init clk.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git
v4.7-clk/next commit 86609a6613c64ee9272da1fd2f578d4beab2174e)

Conflicts:

drivers/clk/rockchip/clk-rk3228.c
[zx: there is no rk3228 clock controller, and apply this patch for
clk-rk3366 manually.]

Change-Id: I2d73c90eb6f43150725c81417af37a6a562cd329
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: remove redundant checking of device_node

rockchip_clk_of_add_provider is used by sub-clk driver which
already call of_iomap before calling it. If device_node does
not exist, of_iomap returns NULL which will fail to init the
sub-clk driver. So really it's redundant.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git
v4.7-clk/next commit a96edf5a5243e1bdf642492b783221aa498f1e49)

Change-Id: I9a51ed269fe26742da2ae84d99cf9689f49add1b
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: fix warning reported by kernel-doc

./scripts/kernel-doc -man -v drivers/clk/rockchip/clk.h > /dev/null

drivers/clk/rockchip/clk.h:133: warning: missing initial short
description on line:
 * struct rockchip_clk_provider: information about clock provider
drivers/clk/rockchip/clk.h:133: info: Scanning doc for struct
drivers/clk/rockchip/clk.h:164: warning: missing initial short
description on line:
 * struct rockchip_pll_clock: information about pll clock
drivers/clk/rockchip/clk.h:164: info: Scanning doc for struct
drivers/clk/rockchip/clk.h:194: warning: No description found for
parameter 'parent_names'
drivers/clk/rockchip/clk.h:194: warning: No description found for
parameter 'num_parents'
drivers/clk/rockchip/clk.h:194: warning: Excess struct/union/enum/typedef
member 'parent_name' description in 'rockchip_pll_clock'
drivers/clk/rockchip/clk.h:235: warning: missing initial short
description on line:
 * struct rockchip_cpuclk_reg_data: describes register offsets and
masks of the cpuclock

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git
v4.7-clk/next commit 1c908b320055e1ce706e91121dbb2ce7934c788f)

Change-Id: I18dbd45ebd528fe2a871c98a1561dd0c0bf41e13
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: remove mux_core_reg from rockchip_cpuclk_reg_data

mux_core_reg isn't been used anywhere, let's remove it.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git
v4.7-clk/next commit 72478f190fec9f2358b62f32ce5e27e6f323fa53)

Change-Id: Ib6d8ee5bca61d1ada6215660862d2d728927a948
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: Add support for multiple clock providers

There are need to support Multi-CRUs probability in future, but
it is not supported on the current Rockchip Clock Framework.

Therefore, this patch add support a provider as the parameter
handler when we call the clock register functions for per CRU.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git
v4.7-clk/next commit d509ddf2e57c99ae760d1a289b85f1e0d729f864)

Conflicts:

drivers/clk/rockchip/clk-rk3036.c
drivers/clk/rockchip/clk-rk3188.c
drivers/clk/rockchip/clk-rk3228.c
drivers/clk/rockchip/clk-rk3366.c
[zx: keep calling clk_register_fixed_factor previouslly, and there
is no rk3228 clock controller, add support for clk-rk3366 manually,
because it is not in the upstream codes.]

Change-Id: I94976f38fb6edd88f334479d6e44fef5bcdfc16a
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: allow varying mux parameters for cpuclk pll-sources

Thers are only two parent PLLs that APLL and GPLL for core on the
previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
GPLL as alternate parent when core is switching freq.

Since RK3399 big.LITTLE architecture, we need to select and adapt
more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next
 commit 0fda2be634398f4b8d53c0436311f99557e56c4e)

Conflicts:

drivers/clk/rockchip/clk-rk3228.c
[zx: there is no rk3228 clock controller, apply this patch for
clk-rk3366.]

Change-Id: I48fde9facccd41585873c997b0b02a7a73972717

UPSTREAM: clk: rockchip: only enter pll slow-mode directly before reboots on rk3288

As commit 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before
reboot for rk3288") states, switching the PLLs to slow-mode is only
necessary when rebooting using the soft-reset done through the CRU.

The dwc2 controllers used create really big number of interrupts in
special constellations involving usb-hubs and their number is so high,
it can even overwhelm the interrupt handler if the cpu-speed os to low.

Right now the PLLs are put into slow-mode in a shutdown syscore_ops
callback which means it happens on all reboots (not only the soft-reset
ones) and even on poweroff actions.

This can result in the system not powering off and getting stuck instead,
so we should move the slow-mode change nearer to the actual reboot action.

For this we introduce the possiblity to also set a callback that gets
called from the restart-handler directly prior to restarting the system
and move the shutdown-callback to this new option.

With this the slow-mode switch is done only on the necessary reboots
and also has a smaller possibility of causing artifacts.

Fixes: 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288")
Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
(cherry picked from commit dfff24bde7fb8d57482e907d5dfb0be3a9e28119)

Conflicts:

drivers/clk/rockchip/clk-rk3228.c
[zx: there is no rk3228 clock controller, apply for clk-rk3366]

Change-Id: I2e91afd893c87eb3ab8a41db1fe81f5c43409951
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: switch PLLs to slow mode before reboot for rk3288

We've been seeing some crashes at reboot test on rk3288-based systems,
which boards have not reset pin connected to NPOR, they reboot by
setting 0xfdb9 to RK3288_GLB_SRST_FST register. If the APLL works in
a high frequency mode, some IPs might hang during soft reset.
It appears that we can fix the problem by switching to slow mode before
reboot, just like what we did before suspend.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 1d33929e2a2b69ae6d40e09ccfc8c7d705a543ba)

Change-Id: Ic01f80e6f33ae84cc87e954aae35f26b6f1a5434
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: dts: rockchip: rk3366: add usb2.0 phy node

Change-Id: Ib1bc0add32d99de9ed78e70c29526cef926c7cad
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

phy: rockchip-usb: support InnoSilicon usb2.0 phy

For InnoSilicon usb2.0 phy, there is no siddq bit for operating,
what is more, when we control usb phy to suspend, its Plls will
not be affected. So we can operate resume/suspend bits directly
when it is going to power on/off.

Change-Id: I6bfe6b1a90b1bdcb0b0d5b670d579a625b22c0ba
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

Documentation: bindings: add compatible entry for Rockchip USB2.0 PHY

Compatible "rockchip,rk336x-usb-phy" support to RK3368 & RK3366.

Change-Id: I435ecd0a9f1c2a50836f7e3c44b6089ba49d728a
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

UPSTREAM: clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type

Because there are some frac clock mux nodes don't have a gate node on
the RK3399.

Change-Id: I4791b90a08faab286743a5cba30738cfb046594c
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next
 commit ffd9d4d39ef7ff90364d3abd6c39919e6582b605)

clk: rockchip: add clock ids for mpll_src and 32k on RK3366

Set the newly added id for mpll_src and 32k, so that they can be called
in other parts.

Change-Id: Ief82231215a147b62abcfbb5565054470fc9ea37
Signed-off-by: Feng Xiao <xf@rock-chips.com>

ARM64: dts: rockchip: enable the tsadc for rk3399 chrome

This patch enables the tsadc for rk3399 evb board.

The rk3399 evb board uses the gpio to reset the chip since it connects the
PMIC to work, and TSHUT is low active on evb board.

Change-Id: Ibd4fc2c752fe1f34cc231385ee314e4b9a32e970
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

ARM64: dts: rockchip: add the thermal main info found on rk3399

This patch adds the thermal needed main information for rk3399 SoCS.

Basically has the following content:

1) TSADC controller:
    Add the needed attributes for rk3399 TSADC controller.
    Especially for the TSHUT, in some cases if we are unable to shut it down
    in orderly fashion (says: kernel is stuck holding a lock or similar), then
    hardware TSHUT will reset it.
    If the temperature is over 95C over a period of time the thermal shutdown
    of the tsadc is invoked with can either reset the entire chip via the CRU,
    or notify the PMIC via a GPIO. This should be set in the specific board.

2) Thermal zones:
    Add the needed device mode for thermal generic framework.
    Detail in Documentation/devicetree/bindings/thermal/thermal.txt.

Change-Id: I1361beeb85e6d4a134b4640c16440452aa950e16
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

video: rockchip: lcdc: 3366: add support power domain control

Change-Id: Ibb9d15e6e2a84a1847f4cfbbc8e75bca54e1782b
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

dt/bindings: power: add RK3399 SoCs header for power-domain

According to a description from TRM, add all the power domains

Change-Id: Ibbf17fb1edc125358760db8acd99dd681913cd3c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: dts: rk3399: add pinctrl for i2s spdif

Change-Id: I12ae87196180efadb6a8b16787b4815c42223970
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

dtsi: screen-timing: lcd-tv080wum-mipi: update CABC lut

Get the gamma value from screen vendor and use the following
algorithm to get the cabc lut

for(i=0;i<256;i++)
cabc_lut[i] = pow((256.0/(i + 256)), gamma_val) * 65536 + 0.5;

Change-Id: I8500cc84869d2693ce6af4e116b2140b3d3a16fc
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: lcdc: 3366: update for CABC

Change-Id: I75fd4deb02f3f131a7258f5529a8cb68fb55dca6
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

UPSTREAM: spi/rockchip: Make sure spi clk is on in rockchip_spi_set_cs

Rockchip_spi_set_cs could be called by spi_setup, but
spi_setup may be called by device driver after runtime suspend.
Then the spi clock is closed, rockchip_spi_set_cs may access the
spi registers, which causes cpu block in some socs.

Change-Id: I58915aee30cfbd3098eb137e3d9046b59ad9476c
Fixes: 64e36824b32 ("spi/rockchip: add driver for Rockchip RK3xxx")
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org broonie/spi.git for-next
 commit b920cc3191d7612f26f36ee494e05b5ffd9044c0)

UPSTREAM: spi: rockchip: add bindings for rk3399 spi

Add devicetree bindings for Rockchip rk3399 spi which found on
Rockchip rk3399 SoCs.

Change-Id: Ib43ec4ce8970359f660311fce35017843f8998df
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org broonie/spi.git for-next
 commit 9b7a56221590cad777e56ec40afe7a6a68f9ac01)

UPSTREAM: arm64: dts: rockchip: Add the thermal data found on RK3368

This patchset add the thermal for RK3368 dts,
Since the two CPU clusters, with four CPU core for each cluster,
one cluster is optimized for high-performance(big cluster) and the othe
is optimized for low power(little cluster).

This patch adds the second order for thermal throttle, and the critical
temperature for thermal over-tempeature protection on Software.

Change-Id: I9491287695768530c557511097f79ad6188adf1b
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit c68bb56efb25e2d326ae413e399cdb1b4528e173)

ARM64: dts: rk3366: use operating-points-v2 for gpu dvfs

Change-Id: Ia68197273e278f25320a4afe64c35c070f1737cc
Signed-off-by: Feng Xiao <xf@rock-chips.com>

video: rockchip: lcdc: 3366: fix timing reg take effect time

rk3366 timing reg config change to frame effect,
so we need config done after update timing.

Change-Id: I7279fc03a066357cb8a0ed452e9182f92bf90f01
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

ARM64: dts: rockchip: rk3366-tb: add hdmi support

Change-Id: Id278ca8f4ecc2e835d65653d72ae83de74cd9f91
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: fb: update for extend vop fb info

like rk3366 vop0 is different from vop1, so fb[rk_fb->num_fb >> 1]
is not correct for extend vop fb info.

Change-Id: Ie7ed0614a5cb32fcb22707c88aa70be45cb243d7
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

arm64: configs: rockchip_defconfig add DEVFREQ Governors

Change-Id: Iea6985da7a0f080b9949715a55326a9ece8f0ed9
Signed-off-by: Feng Xiao <xf@rock-chips.com>

lowmemorykiller: calculator free pages exclude CMA's free

Change-Id: I51a08cd9c9ef8d37fd0a5f649c5d2843a8b7d9ff
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

clk: rockchip: add clock ids for isp of RK3366 SoCs

Change-Id: Ia1c1ef34eebcaa8f29d537b291c45654252444b8
Signed-off-by: Feng Xiao <xf@rock-chips.com>

ARM64: dts: rk3366-tb: Enable rga device

Change-Id: I935033613e52edce6a479651fe0bc3ed2db5fb9c
Signed-off-by: Zhiqin Wei <wzq@rock-chips.com>

ARM64: dts: rockchip: add dts file for rk3399 chromebook

Change-Id: I17589cef588958601448ff7e3615b84ef95dd506
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>

arm64: configs: update rockchip_defconfig by savedefconfig

Change-Id: I057bdbe89ed484f15295a0184f94f8a5acac8483
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

video: rockchip: reorder config

Change-Id: Ie9e0f2e8a69c456f52003dd3f956ff0a44b981cd
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

video: rockchip: iep: do not default enable

Change-Id: I48747ec133f05ec6b1fa6d70187c4c641fed7ccd
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM64: rockchip_defconfig: enable VCODEC

add CONFIG_RK_VCODEC=y

Change-Id: Ida687dceeb36488c8ddbbf02bd273dec2991993b
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>

ARM64: dts: rk3366: add iep device

add iep device

Change-Id: Ie3c60a79aaddf308847f84b3acd55d529e22f352
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>

ARM64: dts: rk3366: enable iep mmu

enable iep mmu

Change-Id: Ia70422fbdf60d5cea8deaa2695913ccf32b580a3
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>

ARM64: dts: rk3366: add vpu device

add vpu_service and rkvdec device

Change-Id: I53dea4053fa61bd0cd4f6313d9ea7e87673f2ce4
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>

ARM64: dts: rk3366: enable vpu mmu

enable vpu mmu

Change-Id: I07d0c0e251d726b76110ecab0f3276ba4e97ee33
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>

video: rockchip: vcodec: add vpu codec drivers

move vpu codec code to drivers/video/rockchip

Change-Id: Idf4100181200cf28a18990da7088bee495f10fcb
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>

ARM64: dts: rockchip: rk3366: modify the initial rate of wifi pll

There is a div2 behind wifi pll, so the initial rate should be 960MHz.

Change-Id: Ib90457a0b17907c3056adf58edd623ae462b06a3
Signed-off-by: Feng Xiao <xf@rock-chips.com>

mmc: sdio: call mmc_power_cycle before re-init sdio devices

Change-Id: I4ae9bb385c9235eb184de0f3bf06719b056f4842
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

video: screen-timeing: sdk mipi: The frame rate increased from 44 to 55

Change-Id: Id5fec461e1785b8cb713c7bb686deb2bb38973d9
Signed-off-by: xubilv <xbl@rock-chips.com>

Revert "ARM64: dts: rockchip: add emmc, sdio and sdmmc node for rk3399"

This reverts commit d3e94b630981c7aabe0f041e547c78a7bd3d3ec4.

ERROR (reg_format): "reg" property in /phy has invalid length (8 bytes) (#address-cells == 2, #size-cells == 2)

Change-Id: I92c498906248c08aade2e36967f896fdd1094abc

clk: rockchip: add video noc clk to the list of rk3366 critical clocks

The clocks of VPU NOC and RKVEDC NOC interact with each other.
If one of VPU and RKVDEC is working, they all must be opened.

Change-Id: I966df107ae72fbbb99f1e660a79bfd07476e8539
Signed-off-by: Feng Xiao <xf@rock-chips.com>

ARM64: rockchip_defconfig: enable IEP

enable IPE

Change-Id: Id4f8f8a91106269b6d8e4f0e0dc7ec1d499c2ce2
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>

video: rockchip: iep: iep code modify

fix iep code compile fail in kernel-4.4

Change-Id: Iba105baecff5fe474cd0d9c02dc9b7970e9c9990
Signed-off-by: sayon.chen <sayon.chen@rock-chips.com>

MALI: add midgard src dir

Change-Id: I9938fe0377fc57e030c9e5109c216d6c62dbeef0
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

arm64: configs: rockchip_defconfig enable configs for MALI midgard.

Change-Id: Idec65015b7dfd73926e713a74daf15f46ea409eb
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

arm64: dts: rk3366: add node of GPU.

Change-Id: Id545de4b7a2747e6b2c46cbedfdc160c3552c105
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

MALI: rockchip: not to use sg_dma_len.

When CONFIG_NEED_SG_DMA_LENGTH is enabled,
sg_dma_len is defined as follow :
"#define sg_dma_len(sg)             ((sg)->dma_length)"
But, dma_length is not used by the framework indeed.

Change-Id: Ibfd3223b38b96701f839cdc91207a49f20789fec
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

ARM64: dts: rockchip: add watchdog node for rk3366

Change-Id: I44f6fc21d9b55f2229fef0fd8fe0091367c2a8fa
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>

ASoC: rt5640: fix rt5640_i2c_probe fail sometimes

if the codec is not initialized completely, i2c transfer will be
failed, so we just return PROBE_DEFER to let codec have chance to
be probed later.

Change-Id: I68922ffa7ddf048ebe3f95be9349d38b7b059982
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

ARM64: dts: rk3366-tb: Add wifi node and enable it

Change-Id: I7e76d78439828a21cdc2d936ee22eab7789a50e6
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

ARM64: dts: rk3366-tb: add sdio_pwrseq for sdio wifi

Change-Id: I0490827fa88a680cc449c367772bbc337ebe507e
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

arm64: configs: rockchip_defconfig enable wireless devices

Change-Id: Icc4126588bd69e6e7b09fe051a719d182ad9b087
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

net: rkwifi: initialize code to support rkwifi

Change-Id: Id8ad92690bb1565ecae45ecf1f9edba71292dfc0
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

MALI: rockchip: tidy 'platform specific code'.

We use devfreq to implement DVFS of GPU, instead of 'legacy_dvfs'.

Change-Id: If5c8ef05c8f37c88a5c22779468b21315d71eda0
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

iommu: rk-iovmm: fix back to back sg entries condition

Change-Id: Ie493d3d8b34ac4229b3a5a2a84cd52568425f106
Signed-off-by: Simon <xxm@rock-chips.com>

MALI: rockchip: modify to build in kernel 4.4.

Change-Id: Ib462c42337e655607b2e222d7d97064dfc1c76c4
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

MALI: rockchip: upgrade DDK to r8p0-02rel0.

Change-Id: I85a3bedf89a3fc27971b1d26e7bfa9a8bee32d06
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

MALI: rockchip: upgrade to DDK r7p0-02rel0.

Conflicts:

drivers/gpu/arm/midgard/mali_kbase_config.h

Change-Id: I2d93041a0525ce6f1399c3a456c4c8f7be22243e
Signed-off-by: chenzhen <chenzhen@rock-chips.com>

net: wifi: rockchip: update broadcom drivers for kernel4.4

Change-Id: I5a764afc5abdf8cae4ba12181ebd36a03cdcb110
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

Revert "UPSTREAM: regulator: core: avoid unused variable warning"

This reverts commit 40e4c3535811ea74490bfa4fbe09cf85bb305efb.

Please refer to commit 70a7fb80e85a
("regulator: core: Fix nested locking of supplies")

Change-Id: If0bee255621a7480cfc6fa232f65081c4d904897

ARM64: dts: rockchip: add i2c2, i2c4 gpio func support for rk3366

Change-Id: I8a3c5dac5c23d90706c21ffb48f4ac15e4f1cffb
Signed-off-by: David Wu <david.wu@rock-chips.com>

ARM64: configs: rockchip: add support i2c gpio config

Change-Id: If44b02f93559ddbbf8b266cc945b648d7cd7fffd
Signed-off-by: David Wu <david.wu@rock-chips.com>

arm64: configs: rockchip_defconfig enable CPU_FREQ_DEFAULT_GOV_INTERACTIVE

Change-Id: I7e241acad10a5b4dc2b7e46e75dfc4043e794f8f
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

arm64: configs: rockchip_defconfig enable ARM_CPUIDLE

Change-Id: I6d2181de4c9489da65117fa817942962b74469bf
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

arm64: configs: update rockchip_defconfig by savedefconfig

Change-Id: I5380b58e9053238f16ca8ed11f7c9459083e1798
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

cpufreq: interactive: fix cpufreq object duplicate creatation in sysfs

[    4.216722] sysfs: cannot create duplicate filename '/devices/system/cpu/cpufreq'
[    4.233798] ------------[ cut here ]------------
[    4.244376] WARNING: at fs/sysfs/dir.c:31
[    4.253556]
[    4.256975] CPU: 3 PID: 1 Comm: swapper/0 Not tainted 4.4.0 #156
[    4.270730] Hardware name: Rockchip SDK tb board (DT)
[    4.282302] task: ffffffc039670000 ti: ffffffc039678000 task.ti: ffffffc039678000
[    4.299444] PC is at sysfs_warn_dup+0x5c/0x78
[    4.309422] LR is at sysfs_warn_dup+0x5c/0x78

Change-Id: Id21fe74dc082ec6c94fcb3e0cc11b78226549f7d
Fixes: bc68f6c4efbd ("cpufreq: interactive: build fixes for 4.4")
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>

FROMLIST: usb: dwc3: Enable support for 64-bit system

Add 64-bit DMA operation support to the USB DWC3 driver.
First attempt to set the coherent DMA mask for 64-bit DMA.
If that failed, attempt again with 32-bit DMA.

Change-Id: I6d8e0e35ed606aa38d1dbadbb48f5629c1b39552
Signed-off-by: Thang Q. Nguyen <tqnguyen@apm.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(am from https://patchwork.kernel.org/patch/8109031/)

FROMLIST: usb: dwc3: pass arch data to xhci-hcd child

The xhci-hcd child node needs to inherit archdata attribute to use
dma_ops functions and attributes. This patch enables the USB DWC3
driver to pass archdata attributes to its xhci-hcd child node.

Signed-off-by: Thang Q. Nguyen <tqnguyen@apm.com>
Change-Id: I82abc58fd8d01d2233499958713dd69ed58dedb5
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(am from https://patchwork.kernel.org/patch/8109041/)

FROMLIST: ARM64: dts: rockchip: add syscon-reboot-mode DT node

Add syscon-reboot-mode driver DT node for rk3368 platform

Change-Id: I050579c2392fad6c7756d0d8a5dfc1a8a36023e4
Tested-by: Caesar Wang <caesar.upstream@gmail.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

ARM64: dts: rockchip: add gt9xx touchscreen support

need to modify the i2c4 scl and sda connection in hardware.

Change-Id: I57981a3891047412b9ea61112fbf5ff4a23223b3
Signed-off-by: David Wu <david.wu@rock-chips.com>

video: rockchip: vop-lite: fix get clock source failed

Rename clock name and fix deadlock when VOP irqs are disabling.

Signed-off-by: Wenlong Zhuang <daisen.zhuang@rock-chips.com>
Signed-off-by: Xubilv <xbl@rock-chips.com>
Change-Id: Ib794128e9e0dda0fc7b4c48d52d196e8ba70c11d

UPSTREAM: usb: dwc3: Fix assignment of EP transfer resources

The assignement of EP transfer resources was not handled properly in the
dwc3 driver. Commit aebda6187181 ("usb: dwc3: Reset the transfer
resource index on SET_INTERFACE") previously fixed one aspect of this
where resources may be exhausted with multiple calls to SET_INTERFACE.
However, it introduced an issue where composite devices with multiple
interfaces can be assigned the same transfer resources for different
endpoints. This patch solves both issues.

The assignment of transfer resources cannot perfectly follow the data
book due to the fact that the controller driver does not have all
knowledge of the configuration in advance. It is given this information
piecemeal by the composite gadget framework after every
SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
programming model in this scenario can cause errors. For two reasons:

1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION and
SET_INTERFACE (8.1.5). This is incorrect in the scenario of multiple
interfaces.

2) The databook does not mention doing more DEPXFERCFG for new endpoint
on alt setting (8.1.6).

The following simplified method is used instead:

All hardware endpoints can be assigned a transfer resource and this
setting will stay persistent until either a core reset or hibernation.
So whenever we do a DEPSTARTCFG(0) we can go ahead and do DEPXFERCFG for
every hardware endpoint as well. We are guaranteed that there are as
many transfer resources as endpoints.

This patch triggers off of the calling dwc3_gadget_start_config() for
EP0-out, which always happens first, and which should only happen in one
of the above conditions.

Fixes: aebda6187181 ("usb: dwc3: Reset the transfer resource index on SET_INTERFACE")
Cc: <stable@vger.kernel.org> # v3.2+
Reported-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@kernel.org>
(cherry picked from commit c450960187f45d4260db87c7dd4fc0bceb5565d8)

Change-Id: I804cb4d2f3b79b3cfd4be5b0942ed6f866c1e580
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

UPSTREAM: usb: dwc3: gadget: set the OTG flag in dwc3 gadget driver.

This patch is needed in order to pass one test case
defined in the OTG Automated Compliance Test specification.

Specification location:
http://www.usb.org/developers/onthego/otgeh_compliance_plan_1_2.pdf

This test case uses PET Tool, and PET Tool is one USB hardware
equipment provided by MQP Electronics.

Test case id is 6.8.3 B-UUT Bypass Capacitance.

We must set this otg flag in order to be able to return OTG
descriptor during enumeration, otherwise this test case with
failed with below error: "Get OTG descriptor request stalled".

Signed-off-by: Jianqiang Tang <jianqiang.tang@intel.com>
Signed-off-by: Felipe Balbi <balbi@kernel.org>
(cherry picked from commit 6a4290cc28be12d72d50644bd4bda1aede37cd41)

Change-Id: If264c2a878ee8520edc57876ab2325dce4ca869e
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

UPSTREAM: usb: dwc3: of-simple: fix build warning on !PM

if we have a !PM kernel build, our runtime
suspend/resume callbacks will be left defined but
unused. Add a ifdef CONFIG_PM guard.

Signed-off-by: Felipe Balbi <balbi@ti.com>
(cherry picked from commit 5072cfc40a80cea3749fd3413b3896630d8c787e)

Change-Id: I6a7ceb1a90162b132afce17423888ab0cbdf897b
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

UPSTREAM: usb: dwc3: gadget: don't send extra ZLP

If the request->length is zero, a ZLP should already be sent due to that
and another ZLP is not needed to terminate the transfer.

Fixes: 04c03d10e507 ("usb: dwc3: gadget: handle request->zero")
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
(cherry picked from commit d9261898a4b2c143c28568dc686a1becfc637a99)

Change-Id: Ib976552f93321f6ea52d3f0151c66fd6f2db8b17
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

UPSTREAM: usb: dwc3: gadget: pass a condition to dev_WARN_ONCE()

instead of using:

if (condition) {
dev_WARN_ONCE(dev, true, "foo");
return -EINVAL;
}

let's use:

if (dev_WARN_ONCE(dev, condition, "foo"))
return -EINVAL;

Signed-off-by: Felipe Balbi <balbi@ti.com>
(cherry picked from commit 95ca961c758cd9ce789247098b09c39017637e58)

Change-Id: I8a7ee1e00ddf619d23ab974663c11fe795e9a478
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

UPSTREAM: usb: dwc3: trace: show request flags

struct usb_request have 3 flags which might be
important to know about during debug. This patch
shows each of the 3 flags as a single letter:

z -> for zero
s -> short not okay
i -> interrupt

A capital letter means the feature is enabled
while a lower case letter means it is disabled;

Thus 'zsI' indicates that a ZLP is not needed,
that we can accept a short packet and interrupt
for this request should be enabled.

Signed-off-by: Felipe Balbi <balbi@ti.com>
(cherry picked from commit 46a01427e969e53d993b988ebbdb8c7c3562b66f)

Change-Id: I5d60411c51eff9f5a5f1233680bca6369f6fc6b8
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

UPSTREAM: usb: dwc3: gadget: handle request->zero

So far, dwc3 has always missed request->zero
handling for every endpoint. Let's implement
that so we can handle cases where transfer must
be finished with a ZLP.

Note that dwc3 is a little special. Even though
we're dealing with a ZLP, we still need a buffer
of wMaxPacketSize bytes; to hide that detail from
every gadget driver, we have a preallocated buffer
of 1024 bytes (biggest bulk size) to use (and
share) among all endpoints.

Reported-by: Ravi B <ravibabu@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
(cherry picked from commit 04c03d10e507052cfce6910ddf34091196e79e1c)

Change-Id: I4dce506b683a9381e73733d09dd03e12364bef1f
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

UPSTREAM: usb: dwc3: remove dwc3-qcom in favor of dwc3-of-simple

Now that we have a generic dwc3-of-simple.c, we can
use that instead of maintaining dwc3-qcom.c which is
extremely similar.

Cc: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
(cherry picked from commit b084662776be8b07ab9114ff1a16a4e9bf907d35)

Change-Id: I4ae3b2649b5b970ef2974d5fa41ac8ff2affb6e0
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>