ARM64: dts: rockchip: rk3399: vr: add io for syr828/827 sleep off contrl

Change-Id: Ibc9419b86c0038217a69e14a2b7dd511ebe58f5d
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

power: rk818: add power on/off source print

Change-Id: I4ea6cff9ecd0ebe87fb454cd26945c252f342e1f
Signed-off-by: Binyuan Lan <lby@rock-chips.com>

arm64: dts: rk3399-rev3: modify the cpu's opp table

The opp table can cover the chips whose leakage is between 30mA and 60mA.

Change-Id: I50be3923eb6016cba6309380006ce902d22fe123
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

arm64: dts: rockchip: enable dmc and set A53 1.5G voltage to 1.1V on rk3399 mid

Change-Id: Iba037b12276f2f4db22611e6cb944643056345c6
Signed-off-by: Zhou weixin <zwx@rock-chips.com>

arm64: dts: rockchip: add 32.768K clk node for BT on rk3399 evb/mid/vr board

Change-Id: I712fa3915e7fa071d136cdf157dceee6b1f18994
Signed-off-by: Weilong Gao <gwl@rock-chips.com>

ARM64: dts: rk3399-android: add ddr devfreq nodes for rkfb

Devfreq will register notify to rkfb, to handle vop during ddr
changing frequency.

Change-Id: I22365597054b2155ef1b9754d6ecac243520b3ee
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

PCI: rockchip: fix wrong clr for phy interrupt

We probably didn't notice this as we still use
evb-rev1 to test our SSD with PCIe on which
the client interrput is broken actually.

Change-Id: I70e2644b9017cc5cd1b7445efb24fa69e22e0901
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

arm64: rockchip_linux_defconfig: add some driver config according to cros

Some changes is made by savedefconfig

Change-Id: I19ac249e4510368299e8376bfbda30a34ade7b59
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

arm64: dts: rockchip: enable the backlight device node for Sapphire-linux

Change-Id: I6b9fe6d2563975a5524262aa3c32ebd37741f33c
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

video: rockchip: fb: add car_reversing for px5

if userspace set car_reversing 1, rk fb will ignore
buffer from hwc.

Change-Id: Ib3bb9a105a8d6b7a2cc0e71c21bf8cc208b4ffd3
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

pwm: rockchip: add rk_fb config_done for voppwm

Change-Id: Iea012bfcec972f4b722950ea06713d2df4690242
Signed-off-by: David Wu <david.wu@rock-chips.com>

video: rockchip: hdmi: add new hdmi resolution mode support for discrete vr device.

For some special hdmi pixclock we should add support for this clock in hdmi phy mpll table.

Add new format SUPPORT_RK_DISCRETE_VR for rockchip discrete vr device,if hdmi device
is rockchip discrete vr device, please set the vic = HDMI_VIDEO_DISCRETE_VR in hdmi timing.

Change-Id: I820f967a84fbb7737cd9e1c2951b89df63863298
Signed-off-by: wenping.zhang <wenping.zhang@rock-chips.com>

video: rockchip: hdmi: add SUPPORT_VESA_DMT feature support for rk3399 hdmi.

Change-Id: Idafd772831593285af864eb3adf045e99f3c8d4a
Signed-off-by: wenping.zhang <wenping.zhang@rock-chips.com>

ARM64: dts: rk3399: syr82x: support vsel pin to en/disable dcdc

Set vsel pin to active to disable DCDC,
Set vsel pin to inactive to enable DCDC.

Change-Id: Ie7d98730e5f59ffe38f0b88388cfb5b852316fe3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

regulator: fan53555: fix up the dcdc is disabled when reboot

Before reboot if the DCDC is disabled,
the DCDC is still disabled after restart.
We have an method to workaround:
Use vsel pin to switch the voltage between value in FAN53555_VSEL0
and FAN53555_VSEL1. If VSEL pin is inactive, the voltage of DCDC
are controlled by FAN53555_VSEL0, when we pull vsel pin to active,
they would be controlled by FAN53555_VSEL1.
In this case, we can set FAN53555_VSEL1 to disable dcdc,
So we can make vsel pin to active to disable dcdc,
VSEL pin is inactive to enable DCDC.

Change-Id: I14c823ed11dc3369044ad2ed0b53a6027acbccd0
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

arm64: dts: rockchip: set gpu and cpu power control in suspend on rk3399 mid

Change-Id: I0c96ccc04f18c3a5df3a045dde62c7741acbbfbd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Zhou weixin <zwx@rock-chips.com>

rockchip/vcodec: fix crash on decoder buffer empty

On vpu2 register separate interrupt bit and enable bit to different
register. When decoder found a buffer empty error which means the input
stream is not enough for one complete frame decoder will not stop
reading input stream buffer until it reach the end of buffer. This will
cause mmu fault on the buffer end.

In order to avoid this case decoder need to clear the enable bit in the
enable register to stop decoder from reading.

Change-Id: I6133aa4611fab03f6545b4775e8ee2320552445f
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>

rockchip/rga: add src1 mmu table config when ABB mode

when rga2 use alpha under mmu, it must config src1
mmu addr for src1 channel will read mmu table

Change-Id: I6131a546421a5195bf3ae183f6fc7cb50fb09cfc
Signed-off-by: Shengqin.Zhang <zsq@rock-chips.com>
Signed-off-by: Zhiqin Wei <wzq@rock-chips.com>

Revert "arm64: Increase the max granular size"

This reverts commit 97303480753e48fb313dc0e15daaf11b0451cdb8.

All Rockchip SoCs only have 64 bytes cache line length, so
it is not need this patch, which increase memory consumption.

Change-Id: Idf684189e7f7011562337a70dc7d26c8dceee7a6
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

regulator: fan53555: add regulator-initial-mode to set default mode

regulator-initial-mode: default mode to set on startup
regulator-initial-mode is set as:
        REGULATOR_MODE_FAST                     0x1
        REGULATOR_MODE_NORMAL                   0x2
Example:
 vdd_cpu_b: syr827@40 {
                compatible = "silergy,syr827";
                reg = <0x40>;
                vin-supply = <&vcc5v0_sys>;
                regulator-compatible = "fan53555-reg";
                regulator-name = "vdd_cpu_b";
                regulator-min-microvolt = <712500>;
                regulator-max-microvolt = <1500000>;
                regulator-ramp-delay = <1000>;
                fcs,suspend-voltage-selector = <1>;
                regulator-always-on;
                regulator-boot-on;
                regulator-initial-state = <3>;
                regulator-initial-mode = <1>;/*1:pwm 2: auto mode*/
                        regulator-state-mem {
                        regulator-off-in-suspend;
                };
        };

Change-Id: I4d3bbd50fd40531113f2cc6fe63905e24888a752
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

PM / devfreq: add to show current load of device

Calculate current load with busytime / totaltime from status,
also show the current frequency.

Change-Id: Ic310035db9c5478aa3d0b1e526b47c451fe09d23
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

camera: rockchip: camsys driver 0.0x21.5

Change-Id: I4855b2e31fff158ae4690781ccc8e0ab0a20273c
Signed-off-by: dalon.zhang <dalon.zhang@rock-chips.com>

HACK: lib/kobject_uevent.c: ignore thermal uevent when suspend

Android healthd try to listen power_supply subsystem uevent,
but which will block system from suspend on big.LITTLE system
because thermal_cooling_device_unregister will called when
cpufreq_exit. So ignore this uevent when suspend.

Change-Id: I35948498916560d5ec75fe561c9e9d588663ad22
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

thermal: rockchip: add temperature dump when panic

Change-Id: I8cf3bbaea76d379dcfd1c89482254854df62cfea
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>

ARM64: dts: rk3399: add pd control for i2s, spdif

Change-Id: Ifdf9b9432f66d54ce99888e41f86bd773df86dbb
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

UPSTREAM: ASoC: simple-card: Add pm callbacks to platform driver

Set snd_soc_pm_ops for the pm ops to make sure that the ASoC level of PM
operations are going to happen. This is needed to get suspend/resume
working correctly when the audio is using simple-card.

Change-Id: Id0355673bc89456fedd3d035cbfd0f7f8f51d1da
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
(cherry picked from commit 7c3767115a04bc7aa87bdbd3352d1801d4bbeea4)

ARM: dts: rockchip: vr-android: add spi1 sleep pinctrl

Change-Id: Ie3a4d8ea56dc2343a749ccc035002f0b25a356a3
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

power: rk818-battery: remove zero algorithm init and add dump info

Change-Id: I47c02b4ac383de1b6943cd63a397fc99f594c9b9
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

arm64: dts: rockchip: add cdn-dp-fb node for rk3399 android

Change-Id: Ie9651babf59d29547f6b506356cce5cd2618e5ae
Signed-off-by: xuhuicong <xhc@rock-chips.com>

arm64: rockchip: rockchip_defconfig enable dp with rk fb

Change-Id: I3208244641cb95fd14c6b814efe2cc6af214affd
Signed-off-by: xuhuicong <xhc@rock-chips.com>

video: rockchip: dp: add cdn DP support for rk3399 with rk fb

Change-Id: Iaa36594e15d19e939f0929e2d6ee2ae99b6ce799
Signed-off-by: xuhuicong <xhc@rock-chips.com>

ARM64: dts: rk3399: add dmc and dfi node

To support ddr frequency scaling function, we need
enable dmc and dfi node.

Change-Id: I84ea6bff679365d86937ff10bcdf466ea31901fb
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

spi: rockchip: set pinctrl state when suspend and resume

Change-Id: I3bfd641513dc8ad0112cb718383eb458c7659a84
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

ARM64: dts: rk3399: fix error address for wdt0

The address of wdt0 and wdt1 are swapped, let's fix it.

Change-Id: I715d181b8984a72ad234d4c1389154f15b60738a
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

video: rockchip: lcdc: add support dmc

Register dmc notify after than dmc driver.

Change-Id: I11c7daee1b4882da87d209854f0bda980c14551b
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

arm64: dts: rockchip: modify l-sensor node for rk3399 tablet product

Change-Id: I41c90b8d24b79009cbb1320e19de2e4a1a400a97
Signed-off-by: jerry.zhang <jerry.zhang@rock-chips.com>

arm64: dts: rockchip: change N key to home for rk3399 VR product

Change-Id: Ie173ee9fedec12cc1ef19e90673488d54e887807
Signed-off-by: jerry.zhang <jerry.zhang@rock-chips.com>

ARM64: configs: rockchip_defconfig: enable rk3399 dmc

Change-Id: I1e9a35d65d44a5f82c36546e5520ea5072b2231d
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

PM / devfreq: rockchip-dfi: disable irqs during accessing ddr monitor

Change-Id: Ie4817a77fcb1283f37f41ab097f02ed7dc9cd18c
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

PM / devfreq: rockchip: rk3399 dmc get opp table from dts

Get opp table from device node for rk3399 dmc table.

Change-Id: I689078d60ebdadf0954b60de70d05bc56a8d6597
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

FROMLIST: PM / devfreq: rockchip: add devfreq driver for rk3399 dmc

Base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.

Change-Id: I4cc6bd9218f6fe0ae09d79c23516c6dbdaa59af2
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

FROMLIST: Documentation: bindings: add dt documentation for rk3399 dmc

This patch adds the documentation for rockchip rk3399 dmc driver.

Change-Id: Icaff8fa2173ded5c64a08e877d32a8eca1a0c3be
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

FROMLIST: PM / devfreq: event: support rockchip dfi controller

on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.

Change-Id: I85efe7f626e636606508fdd171b14275591c0612
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

FROMLIST: Documentation: bindings: add dt documentation for dfi controller

This patch adds the documentation for rockchip dfi devfreq-event driver.

Change-Id: Ib5704cdef0c7a53abe3afda126cb1a1adba43b3a
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

FROMLIST: clk: rockchip: rk3399: add ddrc clock support

Add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.

Change-Id: Ib743ffb642fe0c7c0a3b7db14389803595d868b3
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

FROMLIST: clk: rockchip: add new clock-type for the ddrclk

On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.

Change-Id: I9e15dd9e01ab1c51a639a6a59391cd5e0de383b7
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

arm64: dts: rockchip: disable ldo8 and center in suspend on rk3399 mid

Change-Id: I5e269cc3827a203bc1e11a344557515aa57fe1c2
Signed-off-by: Yankun Zheng <zyk@rock-chips.com>
Signed-off-by: Zhou weixin <zwx@rock-chips.com>

ARM64: dts: rk3399-evb2: ajust cpu opp table to make evb2 more stable

Since evb2 couple with ES1, the power consumption is large enough to
shutdown device in some case.

Let's reduce it's support lists to make things simple.

Change-Id: I145aa0c6a21e41b3c8e6ff32fd15839baa15f81e
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

arm64: dts: rockchip: remove unused usb node for rk3399 mid

Change-Id: Ie8883d36a829b08d0963cbd7dbe183404b761093
Signed-off-by: Bin Yang <yangbin@rock-chips.com>

ethernet: rockchip: add pd_gmac support for rk3399

Change-Id: I990e02f585ae9b2ecf99a7e996cd23041ca19a2b
Signed-off-by: David Wu <david.wu@rock-chips.com>

ARM: dts: rockchip: enable tsadc for fennec

Change-Id: Id177ffb022046e569c23bf46a5546ac64450e801
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

arm64: dts: rockchip: use vop_pwm on rk3399-mid-818-android

To control backlight for support cabc.

Change-Id: I8f980174e57c91e264f0ddfb754a670196649b62
Signed-off-by: Zhou weixin <zwx@rock-chips.com>

video: rockchip: vop: 3399: cabc mode indicate whether cabc enable or not

Change-Id: Ia4911d746c934b91a887881660373e4b4824f314
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: fb: add function for vop pwm config done

Change-Id: I80350293c644fc0db1f613b3de14e34b7f3bc0f2
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

arm64: dts: rockchip: disable PCIe and PCIe-phy on rk3399-evb

Let's disable it as the auto link training of PCIe
take quite long time without add-in card or M.2
devices available.

Change-Id: I4a48a44574b68da75845a6e614a9970bb5d6685b
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

arm64: dts: rockchip: fix pcie and pcie-phy support for rk3399

Fix them for matching what the new drivers want.

Change-Id: I6ce43379ab9cf3d274b6b414ec014e431db588b7
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

PCI: rockchip: Add Rockchip PCIe controller support

Add support for the Rockchip PCIe controller found on RK3399 SoC platform.

Change-Id: Ic924a0defaef195575beba4dfc92c33b6b5bc3e7
[Shawn: manually backport to 4.4 with some minor changes]
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>

UPSTREAM: PCI: Add devm_request_pci_bus_resources()

Several host bridge drivers iterate through the list of bridge windows to
request resources.  Several others don't request the window resources at
all.

Add a devm_request_pci_bus_resources() interface to make it easier for
drivers to request all the window resources.  Export to GPL modules (from
Arnd Bergmann <arnd@arndb.de>).

Change-Id: I4b89f0739d66d6027bfd2a01e9e93f5218ade617
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 950334bcf17a6ab55ce13d3bdf050f7b429320d5)

phy: add a driver for the Rockchip SoC internal PCIe PHY

This patch to add a generic PHY driver for rockchip PCIe PHY.
Access the PHY via registers provided by GRF (general register
files) module.

Change-Id: Ieba96d9cdf0d96302f38d29789615e2ec93f3440
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM: dts: rockchip: fix i2s&spdif interrupts on rk3288

These must be translated from the values in the TRM by subtracting 32,
which has not been done.

Change-Id: I8d26bd63d39009b60b310e7ccbcd5de814863861
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>

ARM64: dts: rk3399-evb: add gsl3673 node for rk3399-evb

Change-Id: I8b8232dd280a436e330292794b36f617ae3c0a9d
Signed-off-by: buluess.li <buluess.li@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

mfd: fusb302: change to host when connect type-c to standard-a cable

When connected with type-c to standard-a cable, inno phy will
generate an interrupt before setting the state of typec to host,
which result in detecting of battery charger. This patch change
the state to host before interrupt happen.

Change-Id: I6a2e15c264bd6729c3b8d23af23ad15145559b20
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>

bluetooth: rfkill-bt: enalbe 32K for ap6356

Change-Id: I71a14f38ab1d46bbf3bfc991140a20d8c6a27eec
Signed-off-by: Xu Xuehui <xxh@rock-chips.com>

dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe controller

Add a binding that describes the Rockchip PCIe controller found on Rockchip
SoCs PCIe interface.

Change-Id: Ifb84320315c06759612f2b3d9b2b6ff3e1e5cb1e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>

Documentation: bindings: add dt documentation for Rockchip PCIe PHY

This patch adds a binding that describes the Rockchip PCIe PHY found
on Rockchip SoCs PCIe interface.

Change-Id: I18940e940e0c951d3e2d6bb3b2131a37727a430d
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

pwm: rockchip: Make pwm polarity to be configured correctly

If pwm polarity was configured with different values at uboot,
the enable_conf would not be configured correctly.

Change-Id: I55b9ccc262382951a8a82810f1be74ce9460f266
Signed-off-by: Zhou weixin <zwx@rock-chips.com>

driver,mpu6500: modify _RATE_DEBUG

Change-Id: Iaa1f9c099db659aa7ef9f05efb99c4279569bcf8
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

driver,mpu6500: improve readfifo

while (fifo_count == 0) && (kfifo_len(&st->timestamps) > 0) then flush fifo

Change-Id: I9b4ab975d708ee1bb02435bca933ce8f3b55e037
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

arm64: dts: rockchip: optimize clks for rk3399 dwc3

1. modify clock-names, according to Heiko's suggestion, clock names
should always be in the scope of the device block (named after what
it supplies), and clock-names are always meant from the perspective
of the individual ip-block.

2. remove unnecessary clocks, refer to rk3399 TRM, aclk_usb3 is the
parent of aclk_usb3otg0/1 and aclk_usb3_grf, and we will enable
aclk_usb3otg0/1 and aclk_usb3_grf, so don't need to enable aclk_usb3
again. In addition, the aclk_usb3_rksoc_axi_perf clk is used for usb3
performance monitor module which we don't use now, so don't need to
enable it.

Change-Id: I1d50a72d1523b8b70f1e5f388dc357807131dd7c
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

arm64: rockchip_defconfig: update by savedefconfig

Change-Id: Ic222560c0d8ea4af2e9a7a5429f2f49abe7e8a52
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM64: dts: rockchip: add pinctrl gpio config for rk3399

Change-Id: I84800a35a95d1de61e3ddce6e7db92efb24bbf59
Signed-off-by: David Wu <david.wu@rock-chips.com>

Revert "HACK: phy: rockchip-inno-usb2: disable otg phy suspend for rk3399"

This reverts commit d7d2a689d4b29796018e72eb050bc3d8c61fbf37.

Change-Id: I937498b790c048bcd49269f258bf59b1946e9bbd
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

phy: phy-rockchip-typec: fix rx eq training fail

When do Rx compliance test, PHY is in loopback mode, we
observed that Rx test failed with long cable, and it was
found that equalizer adaptation is not happening properly.
With rx_eq_training forced from PMA, the equalizer adaptation
working fine and Rx test can pass. The root cause is that
the Rx REE component will be turned off when control data
is being received by default PHY configuration. So we need
to unmask REE control data by setting REE control data mask
register, and with this patch, equalizer training will happen
based on the signal coming from controller only.

Change-Id: Ic4fca1045d92381470588c4afccff0cc7318ab4c
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

video: rockchip: vop: 3399: fix post empty when enable afbdc after resume

userspace will set several frame after vop suspend, so the kernel back
buffer will be freed and after resume vop will read a freed buffer and lead
to post empty, so we close all win before suspend, after resume vop will
display black until userspace set a new frame.

Change-Id: I6648861d2162f221e7fbf85d2361ad245e7b88aa
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: 3399: close auto gating when enable CABC

Change-Id: Iaeb99bbc1f25998361cd20fc57c97f33fa5ce63a
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: add win lite supprt afbdc abgr format

Change-Id: I5709c6e06e5e3ca8bd7fe19aa970fa933b178c62
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

arm64: dts: rockchip: vr: modify battery parameters

Change-Id: If3d0c2f85ba4f6dd03e1b0436072199677e1cf77
signed-off-by: Wu Liangqing <wlq@rock-chips.com>

arm64: dts: rockchip: rk3399-vr: support fusb302 and enabled Type-c phy

Change-Id: I117832db612b44b0439a0714743a0d875a2f5897
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

arm64: dts: rockchip: rk3399-android: isp config add dsi control

Change-Id: I39b3a7a7b03d2255342599d4d8b5482c4f8ac5dc
Signed-off-by: dalon.zhang <dalon.zhang@rock-chips.com>

camera: rockchip: camsys driver 0.0x21.4

Change-Id: Ieddb355952150d170ee52a5d80d25c9642a2ec8a
Signed-off-by: dalon.zhang <dalon.zhang@rock-chips.com>

arm64: dts: rk3399-sapphire-excavator-edp: add test-power

Change-Id: Iaa8632fa7faaefcf05eab96d175deab7329143c3
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

arm64: dts: rk3399-sapphire-excavator-box: add test-power

Change-Id: I7c26c8050f27e898ae951fc118fc717cd0b10fce
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

ARM64: dts: rk3399-evb3-edp: disable gt9xx

Since edp screen couple with another type of touchscreen,
so disable gt9xx to reduce i2c errors.

Change-Id: I829ae12039ecaea44c4e0734c18a5ebcd41845f8
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

ARM64: dts: rk3399-evb-edp: remove pwm3 of vdd_center

Fix the evb-edp error voltage for vdd_center.

Change-Id: I7f60ee233820ca175aa68074c6c2ba946045303d
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

ARM: dts: rk3288: remove emmc node for miniarm

This patch remove emmc node for rk3288-miniarm board.
because the new version of the hardware does not use emmc.

Change-Id: I72914a4e570342e5b0b559b3400e0a9db8aea7eb
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>

UPSTREAM: regmap: drop cache if the bus transfer error

regmap_write
->_regmap_raw_write
-->regcache_write first and than use map->bus->write to write i2c or spi
But if the i2c or spi transfer failed, But the cache is updated, So if I use
regmap_read will get the cache data which is not the real register value.

Change-Id: Iae06edf8a2a50d2561d351a8398bd3140904630c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from
 git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git
 commit 815806e39bf6f7e7b34875d4a9609dbe76661782)

arm64: dts: rockchip: modify battery parameters for rk3399 mid

Change-Id: Ib77ce93fdd5936059a1ecdc318eebc18e031e1ae
Signed-off-by: Bin Yang <yangbin@rock-chips.com>

arm64: rockchip_defconfig: add rk818 charge config

Change-Id: Ib339cfae1035f36d81d64907f4b034bc387f85b3
Signed-off-by: Bin Yang <yangbin@rock-chips.com>

test-power: add testpower dts-config

Change-Id: Ib2c78602f604d610a648397cbf08c56cdbd77eab
Signed-off-by: Shengfei Xu <xsf@rock-chips.com>

arm64: dts: rk3399-evb: add test-power

Change-Id: I269c4c667ba313d315fa6ee9443bb07f6295127a
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

arm64: dts: rk3399-box: add test-power

Change-Id: Id06771f84b07c3b943362369269274a41cabb279
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

FROMLIST: PM / devfreq: event: remove duplicate devfreq_event_get_drvdata()

there define two devfreq_event_get_drvdata() function in devfreq-event.h
when disable CONFIG_PM_DEVFREQ_EVENT, it will lead to build fail. So
remove devfreq_event_get_drvdata() function.

Change-Id: I273e91d4aac48ae25af5ef6de2feb37944cf6e39
Signed-off-by: Lin Huang <hl@rock-chips.com>

FROMLIST: clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc

Change-Id: I638d8cd8d6a7a867d10b7595c93c674619b99c30
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

FROMLIST: clk: rockchip: add clock flag parameter when register pll

add clock flag parameter so we can pass specific clock flag
(like CLK_GET_RATE_NOCACHE etc..)to pll driver.

Change-Id: I1e076b3efa6b5da082b6e68e2e2a4c9dfd93e3d4
Signed-off-by: Heiko Stübner <heiko@sntech.de>
Signed-off-by: Lin Huang <hl@rock-chips.com>

UPSTREAM: usb: dwc2: Reorder AHBIDLE and CSFTRST in dwc2_core_reset()

According to the databook, the core soft reset should be done before
checking for AHBIDLE. The gadget version of core reset had it correct
but the hcd version did not. This fixes the hcd version.

Change-Id: I49540085036982e6c496a3b911805f0b67fa79e1
Signed-off-by: John Youn <johnyoun@synopsys.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit b8ccc593eeeacde0e6794c4dcec0a57eba7356e6)

UPSTREAM: usb: dwc2: Avoid more calls to dwc2_core_reset()

Calls to dwc2_core_reset() are currently very slow, taking at least
150ms (possibly more).  It behooves us to take as many of these calls
out as possible.

It turns out that the calls in dwc2_fs_phy_init() and dwc2_hs_phy_init()
should (as documented in the code) only be needed if we need to do a PHY
SELECT.  That means that if we see that we can avoid the PHY SELECT then
we can avoid the reset.

This patch appears to successfully bypass two resets (one per USB
device) on rk3288-based ARM Chromebooks.

Change-Id: If9f7275d61af6fd8558124ff9ebc7c3622c1f4a3
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit 7d56cc2620f523eba7a831daa22186c8ae5bbdfe)

UPSTREAM: usb: dwc2: reduce dwc2 driver probe time

I found that the probe function of dwc2 driver takes much time
when kernel boot up. There are many long delays in the probe
function these take almost 1 second.

This patch trying to reduce unnecessary delay time.

In dwc2_core_reset() I see it use two at least 20ms delays to
wait AHB idle and core soft reset, but dwc2 data book said that
dwc2 core soft reset and AHB idle just need a few clocks (I think
it refers to AHB clock, and AHB clock run at 150MHz in my RK3288
board), so 20ms is too long, delay 1us for wait AHB idle and soft
reset is enough.

And in dwc2_get_hwparams() it takes 150ms to wait ForceHostMode
and ForceDeviceMode valid but in data book it said software must
wait at least 25ms before the change to take effect, so I reduce
this time to 25ms~50ms. By the way, is there any state bit show
that the force mode take effect ? Could we poll curmod bit for
figuring out if the change take effect ?

It seems that usleep_range() at boot time will pick the longest
value in the range. In dwc2_core_reset() there is a very long
delay takes 200ms, and this function run twice when probe, could
any one tell me is this delay time resonable ?

I have tried this patch in my RK3288-evb board. It works well.

Change-Id: I1f42ab6b6851f0721bf93d516bee895ebcdd994f
Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit 20bde643434d541bc5f662c5836a05e9e276eca3)

UPSTREAM: usb: dwc2: Speed dwc2_get_hwparams() on some host-only ports

On some host-only DWC2 ports (like the one in rk3288) when we set
GUSBCFG_FORCEHOSTMODE in GUSBCFG and then read back, we don't see the
bit set.  Presumably that's because the port is always forced to HOST
mode so there's no reason to implement these status bits.

Since we know dwc2_core_reset() is always called before
dwc2_get_hwparams() and we know dwc2_core_reset() should have set
GUSBCFG_FORCEHOSTMODE whenever hsotg->dr_mode == USB_DR_MODE_HOST, we
can just check hsotg->dr_mode to decide that we can skip the delays in
dwc2_get_hwparams().

Change-Id: I912ac2dd5e0ff3f8c12b8263ce268296bbed315f
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit f619473140df4e1a10f4c10f693d214807ebdb03)

UPSTREAM: usb: dwc2: Avoid double-reset at boot time

In (usb: dwc2: reset dwc2 core before dwc2_get_hwparams()) we added an
extra reset to the probe path for the dwc2 USB controllers.  This
allowed proper detection of parameters even if the firmware had already
used the USB part.

Unfortunately, this extra reset is quite slow and is affecting boot
speed.  We can avoid the double-reset by skipping the extra reset that
would happen just after the one we added.  Logic that explains why this
is safe:

* As of the CL mentioned above, we now always call dwc2_core_reset() in
  dwc2_driver_probe() before dwc2_hcd_init().

* The only caller of dwc2_hcd_init() is dwc2_driver_probe(), so we're
  guaranteed that dwc2_core_reset() was called before dwc2_hdc_init().

* dwc2_hdc_init() is the only caller that passes an irq other than -1 to
  dwc2_core_init().  Thus if dwc2_core_init() is called with an irq
  other than -1 we're guaranteed that dwc2_core_reset was called before
  dwc2_core_init().

...this allows us to remove the dwc2_core_reset() in dwc2_core_init() if
irq is not < 0.

Note that since "irq" wasn't used in the function dwc2_core_init()
anyway and since select_phy was always set at exactly the same times we
could avoid the reset, we remove "irq" and rename "select_phy" to
"initial_setup" and adjust the callers accordingly.

Change-Id: Id3b085ddc9d35baca140fc8a502fca74dcfd01b5
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit 0fe239bc190453fe82252c6d41a74e685730cd93)

UPSTREAM: usb: dwc2: reset dwc2 core before dwc2_get_hwparams()

We initiate dwc2 usb controller in BIOS, dwc2_core_reset() should
be called before dwc2_get_hwparams() to reset core registers to
default value. Without this the FIFO setting might be incorrect
because calculating FIFO size need power-on value of
GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers.

This patch could avoid warnning massage like in rk3288 platform:
[    2.074764] dwc2 ff580000.usb: 256 invalid for
host_perio_tx_fifo_size. Check HW configuration.

Change-Id: Iab346c005c9f3ea940f4070f3e433e0c7ea89087
Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit cebfdbf329ae929ccb71632888a7c2100c3d1eeb)