[fast-isel] Fast-isel doesn't use the expect intrinsic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156658 91177308-0d34-0410-b5e6-96231b3b80d8

Use regular expression to match register names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156656 91177308-0d34-0410-b5e6-96231b3b80d8

Make the URL a link instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156655 91177308-0d34-0410-b5e6-96231b3b80d8

[Support/StringRef] Add find_last_not_of and {r,l,}trim.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156652 91177308-0d34-0410-b5e6-96231b3b80d8

Remove extraneous ; and the resulting warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156649 91177308-0d34-0410-b5e6-96231b3b80d8

Add mention of Glasgow Haskell Compiler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156648 91177308-0d34-0410-b5e6-96231b3b80d8

[fast-isel] Add support for selecting @llvm.trap().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156646 91177308-0d34-0410-b5e6-96231b3b80d8

Updated instruction table due to addded intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156644 91177308-0d34-0410-b5e6-96231b3b80d8

Remove warnings from HexagonVLIWPacketizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156636 91177308-0d34-0410-b5e6-96231b3b80d8

Some release notes for dragonegg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156635 91177308-0d34-0410-b5e6-96231b3b80d8

Hexagon constant extender support.

Patch by Jyotsna Verma.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156634 91177308-0d34-0410-b5e6-96231b3b80d8

Typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156633 91177308-0d34-0410-b5e6-96231b3b80d8

[fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices.  Minor cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156632 91177308-0d34-0410-b5e6-96231b3b80d8

Hexagon V5 intrinsics support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156631 91177308-0d34-0410-b5e6-96231b3b80d8

Defer computation of SuperRegs.

Don't compute the SuperRegs list until the sub-register graph is
completely finished. This guarantees that the list of super-registers is
properly topologically ordered, and has no duplicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156629 91177308-0d34-0410-b5e6-96231b3b80d8

[fast-isel] Cleaner fix for when we're unable to handle a non-double multi-reg
retval.  Hoists check before emitting the call to avoid unnecessary work.
rdar://11430407
PR12796

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156628 91177308-0d34-0410-b5e6-96231b3b80d8

objectsize: add a few more tests and fix a bug

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156625 91177308-0d34-0410-b5e6-96231b3b80d8

[fast-isel] Rather then assert (or segfault in a non-asserts build), fall back
to selection DAG isel if we're unable to handle a non-double multi-reg retval.
rdar://11430407
PR12796

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156622 91177308-0d34-0410-b5e6-96231b3b80d8

The return type is an unsigned, not a bool.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156621 91177308-0d34-0410-b5e6-96231b3b80d8

Add space before an open parenthesis in control flow statements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156620 91177308-0d34-0410-b5e6-96231b3b80d8

Added X86 Atom latencies to X86InstrMMX.td.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156615 91177308-0d34-0410-b5e6-96231b3b80d8

PR1255: ConstantRangesSet and CRSBuilder classes moved from include/llvm to include/llvm/Support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156613 91177308-0d34-0410-b5e6-96231b3b80d8

Fix test/CodeGen/X86/tls-pie.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156612 91177308-0d34-0410-b5e6-96231b3b80d8

Implement initial-exec TLS model for 32-bit PIC x86

This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong
code here (see the update to test/CodeGen/X86/tls-pie.ll).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156611 91177308-0d34-0410-b5e6-96231b3b80d8

Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156609 91177308-0d34-0410-b5e6-96231b3b80d8

Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156608 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a use after free when the streamer is destroyed. Fixes pr12622.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156606 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a misleading comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156603 91177308-0d34-0410-b5e6-96231b3b80d8

Tidy up. Trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156602 91177308-0d34-0410-b5e6-96231b3b80d8

Tidy up. Trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156601 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a minor logic mistake transforming compares in instcombine.  PR12514.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156600 91177308-0d34-0410-b5e6-96231b3b80d8

ARM: peephole optimization to remove cmp instruction

This patch will optimize the following cases:
  sub r1, r3 | sub r1, imm
  cmp r3, r1 or cmp r1, r3 | cmp r1, imm
  bge L1

TO
  subs r1, r3
  bge  L1 or ble L1

If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.

rdar: 10734411

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156599 91177308-0d34-0410-b5e6-96231b3b80d8

Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),
but it generates int3 on x86 instead of ud2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156593 91177308-0d34-0410-b5e6-96231b3b80d8

Allow unique_file to take a mode for file permissions, but default
to user only read/write.

Part of rdar://11325849

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156591 91177308-0d34-0410-b5e6-96231b3b80d8

Fix intendation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156589 91177308-0d34-0410-b5e6-96231b3b80d8

Compute secondary sub-registers.

The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:

  Q0_Q1 = [Q0, Q1],  Q0 = [D0, D1], Q1 = [D2, D3]

But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.

This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.

This will eventually enable the coalescer to handle copies of skewed
sub-registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156587 91177308-0d34-0410-b5e6-96231b3b80d8

objectsize: add support for GEPs with non-constant indexes
add an additional parameter to InstCombiner::EmitGEPOffset() to force it to *not* emit operations with NUW flag

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156585 91177308-0d34-0410-b5e6-96231b3b80d8

Added X86 Atom latencies for instructions in X86InstrInfo.td.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156579 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for the 'X' inline asm operand modifier.

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156577 91177308-0d34-0410-b5e6-96231b3b80d8

misched: Print machineinstrs with -debug-only=misched

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156576 91177308-0d34-0410-b5e6-96231b3b80d8

misched: tracing register pressure heuristics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156575 91177308-0d34-0410-b5e6-96231b3b80d8

misched: Add register pressure backoff to ConvergingScheduler.

Prioritize the instruction that comes closest to keeping pressure
under the target's limit. Then prioritize instructions that avoid
increasing the max pressure in the scheduled region. The max pressure
heuristic is a tad aggressive. Later I'll fix it to consider the
unscheduled pressure as well.

WIP: This is mostly functional but untested and not likely to do much good yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156574 91177308-0d34-0410-b5e6-96231b3b80d8

misched: Release only unscheduled nodes into ReadyQ.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156573 91177308-0d34-0410-b5e6-96231b3b80d8

misched: Added ReadyQ container wrapper for Top and Bottom Queues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156572 91177308-0d34-0410-b5e6-96231b3b80d8

misched: Introducing Top and Bottom register pressure trackers during scheduling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156571 91177308-0d34-0410-b5e6-96231b3b80d8

Hexagon V5 Support - V5 td file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156569 91177308-0d34-0410-b5e6-96231b3b80d8

Hexagon V5 FP Support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156568 91177308-0d34-0410-b5e6-96231b3b80d8

RegPressure: API for speculatively checking instruction pressure.

Added getMaxExcessUpward/DownwardPressure. They somewhat abuse the
tracker by speculatively handling an instruction out of order. But it
is convenient for now. In the future, we will cache each instruction's
pressure contribution to make this efficient.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156561 91177308-0d34-0410-b5e6-96231b3b80d8

RegPressure: fix array index iteration style.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156560 91177308-0d34-0410-b5e6-96231b3b80d8

Teach DeadStoreElimination to eliminate exit-block stores with phi addresses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156558 91177308-0d34-0410-b5e6-96231b3b80d8

Revert: 156550 "ARM: peephole optimization to remove cmp instruction"

This commit broke an external linux bot and gave a compile-time warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156556 91177308-0d34-0410-b5e6-96231b3b80d8

Precompute lists of explicit sub-registers and indices.

The .td files specify a tree of sub-registers. Store that tree as
ExplicitSubRegs lists in CodeGenRegister instead of extracting it from
the Record when needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156555 91177308-0d34-0410-b5e6-96231b3b80d8

Rewrite ScalarEvolution::hasOperand to use an explicit worklist instead
of recursion, to avoid excessive stack usage on deep expressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156554 91177308-0d34-0410-b5e6-96231b3b80d8

teach DSE and isInstructionTriviallyDead() about calloc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156553 91177308-0d34-0410-b5e6-96231b3b80d8

formatting change: strip debug info from test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156551 91177308-0d34-0410-b5e6-96231b3b80d8

ARM: peephole optimization to remove cmp instruction

This patch will optimize the following cases:
  sub r1, r3 | sub r1, imm
  cmp r3, r1 or cmp r1, r3 | cmp r1, imm
  bge L1

TO
  subs r1, r3
  bge  L1 or ble L1

If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.

rdar: 10734411

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156550 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a problem with incomplete equality testing of PHINodes in
Instruction::IsIdenticalToWhenDefined.

This manifested itself when inlining two calls to the same function.  The
inlined function had a switch statement that returned one of a set of
global variables.  Without this modification, the two phi instructions that
chose values from the branches of the switch instruction inlined from the
callee were considered equivalent and jump-threading replaced a load for the
first switch value with a phi selecting from the second switch, thereby
producing incorrect code.

This patch has been tested with "make check-all", "lnt runteste nt", and
llvm self-hosted, and on the original program that had this problem,
wireshark.

<rdar://problem/11025519>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156548 91177308-0d34-0410-b5e6-96231b3b80d8

Fix merge-typo and cleanup

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156541 91177308-0d34-0410-b5e6-96231b3b80d8

AVX2: Add an additional broadcast idiom.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156540 91177308-0d34-0410-b5e6-96231b3b80d8

Generate AVX/AVX2 shuffles even when there is a memory op somewhere else in the program.
Starting r155461 we are able to select patterns for vbroadcast even when the load op is used by other users.

Fix PR11900.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156539 91177308-0d34-0410-b5e6-96231b3b80d8

Fix TableGen's RegPressureSet weight normalization to handle subreg DAGS.

I initially assumed that the subreg graph was a tree. That may not be true.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156524 91177308-0d34-0410-b5e6-96231b3b80d8

ExecutionEngine: Check for NULL ErrorStr before using it.

Patch by Yury Mikhaylov <yury.mikhaylov@gmail.com>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156523 91177308-0d34-0410-b5e6-96231b3b80d8

Fix warning text.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156521 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the objc_storeStrong recognizer to stop before walking off the
end of a basic block if there's no store.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156520 91177308-0d34-0410-b5e6-96231b3b80d8

Compute a backwards SubReg -> SubRegIndex map for each register.

This mapping is for internal use by TableGen. It will not be exposed in
the generated files.

Unfortunately, the mapping is not completely well-defined. The X86 xmm
registers appear with multiple sub-register indices in the ymm
registers. This is because of the odd idempotent sub_sd and sub_ss
sub-register indices. I hope to be able to eliminate them entirely, so
we can require the sub-registers to form a tree.

For now, just place the canonical sub_xmm index in the mapping, and
ignore the idempotents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156519 91177308-0d34-0410-b5e6-96231b3b80d8

Rename getSubRegs() to computeSubRegs().

That's what it does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156518 91177308-0d34-0410-b5e6-96231b3b80d8

objectsize:
refactor code a bit to enable future changes to support run-time information
add support to compute allocation sizes at run-time if penalty > 1 (e.g., malloc(x), calloc(x, y), and VLAs)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156515 91177308-0d34-0410-b5e6-96231b3b80d8

Add unittests for Triple::getMacOSXVersion and Triple::getiOSVersion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156507 91177308-0d34-0410-b5e6-96231b3b80d8

Added a regress test for the bug #9964 before close it.
This bug was fixed by Jim Grosbach in #138879, thanks Jim!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156505 91177308-0d34-0410-b5e6-96231b3b80d8

Mark .opd @progbits, thus avoiding a warning from asm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156494 91177308-0d34-0410-b5e6-96231b3b80d8

Set the default iOS version to 3.0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156492 91177308-0d34-0410-b5e6-96231b3b80d8

Use the cpuid 64 bit flag to pick the default CPU name for an unknown model.

For the Family 6 switch in sys::getHostCPUName, an unrecognized model was
reported as "i686".  That's a really bad default since it means that new
CPUs will be treated as if they can only use 32-bit code.  This just looks
at the cpuid extended feature flag for 64 bit support, and if that is set,
it uses a default x86-64 cpu.  Similar logic is already used for the Family
15 code.  <rdar://problem/11314502>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156486 91177308-0d34-0410-b5e6-96231b3b80d8

Don't return true on a function with a void return type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156484 91177308-0d34-0410-b5e6-96231b3b80d8

Add Triple::getiOSVersion.

This new function provides a way to get the iOS version number from ios triples.
Part of rdar://11409204

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156483 91177308-0d34-0410-b5e6-96231b3b80d8

Introduce llvm-c function LLVMPrintModuleToFile.

This lets you save the textual representation of the LLVM IR to a file.
Before this patch it could only be printed to STDERR from llvm-c.

Patch by Carlo Kok!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156479 91177308-0d34-0410-b5e6-96231b3b80d8

change the objectsize intrinsic signature: add a 3rd parameter to denote the maximum runtime performance penalty that the user is willing to accept.
This commit only adds the parameter. Code taking advantage of it will follow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156473 91177308-0d34-0410-b5e6-96231b3b80d8

Make it possible to switch off solution folders. VS Express does not support
them, and requires the user to click away one error message per folder on
project load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156472 91177308-0d34-0410-b5e6-96231b3b80d8

Fixed a typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156471 91177308-0d34-0410-b5e6-96231b3b80d8

Supply a C interface to the "LinkModules" method.
Patch by Andrew Wilkins!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156469 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unused variable to get rid of warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156466 91177308-0d34-0410-b5e6-96231b3b80d8

Add another peephole pattern for conditional moves.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156460 91177308-0d34-0410-b5e6-96231b3b80d8

Use ptr_rc_tailcall instead of GR32_TC.

The getPointerRegClass() hook will return GR32_TC, or whatever is
appropriate for the current function.

Patch by Yiannis Tsiouris!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156459 91177308-0d34-0410-b5e6-96231b3b80d8

Make register FP allocatable if the compiled function does not have dynamic
allocas.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156458 91177308-0d34-0410-b5e6-96231b3b80d8

Expand 64-bit shifts if target ABI is O32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156457 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unused variable to silence compiler warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156456 91177308-0d34-0410-b5e6-96231b3b80d8

Do not install llvm-config-host for cross-builds of clang. rdar://11317847

My previous change to install llvm-config-host for cross-builds resulted
in that file being installed even when the normal llvm-config was not
installed, e.g., when building the install-clang target.  Daniel suggested
this alternative, which solves the immediate problem and also avoids the gunk
in the top-level makefile.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156448 91177308-0d34-0410-b5e6-96231b3b80d8

Miscellaneous accumulated cleanups.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156445 91177308-0d34-0410-b5e6-96231b3b80d8

Fix it so llvm-objdump -arch does accept x86 and x86-64 as valid arch names.
PR12731.  Patch by Meador Inge!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156444 91177308-0d34-0410-b5e6-96231b3b80d8

add to 3.1 release notes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156443 91177308-0d34-0410-b5e6-96231b3b80d8

Fix objc_storeStrong pattern matching to catch a potential use of the
old value after the store but before it is released.
This fixes rdar:/11116986.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156442 91177308-0d34-0410-b5e6-96231b3b80d8

Use a shared function for a common operation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156441 91177308-0d34-0410-b5e6-96231b3b80d8

Fix thinko in conditional.

Part of rdar://11352000 and should bring the buildbots back.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156421 91177308-0d34-0410-b5e6-96231b3b80d8

DAGCombiner should not change the type of an extract_vector index.

When a combine twiddles an extract_vector, care should be take to preserve
the type of the index operand. No luck extracting a reasonable testcase,
unfortunately.

rdar://11391009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156419 91177308-0d34-0410-b5e6-96231b3b80d8

Remove empty directories.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156417 91177308-0d34-0410-b5e6-96231b3b80d8

Remove excess semi-colons to quiet warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156416 91177308-0d34-0410-b5e6-96231b3b80d8

[Support] Fix sys::GetRandomNumber() to always use a high quality seed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156414 91177308-0d34-0410-b5e6-96231b3b80d8

Update load/store instruction patterns in Hexagon V4.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156411 91177308-0d34-0410-b5e6-96231b3b80d8

Formatting fixes.

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156409 91177308-0d34-0410-b5e6-96231b3b80d8

Define mips16 instruction formats.

Patch by Reed Kotler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156408 91177308-0d34-0410-b5e6-96231b3b80d8

Handle OpDeref in case it comes in as a register operand.

Part of rdar://11352000

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156405 91177308-0d34-0410-b5e6-96231b3b80d8