New note, Nate, please check to see if I'm full of it :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28118 91177308-0d34-0410-b5e6-96231b3b80d8

Fix VC++ compilation error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28117 91177308-0d34-0410-b5e6-96231b3b80d8

Somehow, I missed this part of the checkin a couple days ago

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28116 91177308-0d34-0410-b5e6-96231b3b80d8

Sink noop copies into the basic block that uses them.  This reduces the number
of cross-block live ranges, and allows the bb-at-a-time selector to always
coallesce these away, at isel time.

This reduces the load on the coallescer and register allocator.  For example
on a codec on X86, we went from:

   1643 asm-printer           - Number of machine instrs printed
    419 liveintervals         - Number of loads/stores folded into instructions
   1144 liveintervals         - Number of identity moves eliminated after coalescing
   1022 liveintervals         - Number of interval joins performed
    282 liveintervals         - Number of intervals after coalescing
   1304 liveintervals         - Number of original intervals
     86 regalloc              - Number of times we had to backtrack
1.90232 regalloc              - Ratio of intervals processed over total intervals
     40 spiller               - Number of values reused
    182 spiller               - Number of loads added
    121 spiller               - Number of stores added
    132 spiller               - Number of register spills
      6 twoaddressinstruction - Number of instructions commuted to coalesce
    360 twoaddressinstruction - Number of two-address instructions

to:

   1636 asm-printer           - Number of machine instrs printed
    403 liveintervals         - Number of loads/stores folded into instructions
   1155 liveintervals         - Number of identity moves eliminated after coalescing
   1033 liveintervals         - Number of interval joins performed
    279 liveintervals         - Number of intervals after coalescing
   1312 liveintervals         - Number of original intervals
     76 regalloc              - Number of times we had to backtrack
1.88998 regalloc              - Ratio of intervals processed over total intervals
      1 spiller               - Number of copies elided
     41 spiller               - Number of values reused
    191 spiller               - Number of loads added
    114 spiller               - Number of stores added
    128 spiller               - Number of register spills
      4 twoaddressinstruction - Number of instructions commuted to coalesce
    356 twoaddressinstruction - Number of two-address instructions

On this testcase, this change provides a modest reduction in spill code,
regalloc iterations, and total instructions emitted.  It increases the number
of register coallesces.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28115 91177308-0d34-0410-b5e6-96231b3b80d8

Add a helper method.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28114 91177308-0d34-0410-b5e6-96231b3b80d8

wrap long line

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28113 91177308-0d34-0410-b5e6-96231b3b80d8

Adjust to use proper TargetData copy ctor

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28112 91177308-0d34-0410-b5e6-96231b3b80d8

Fix this to be a proper copy ctor

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28111 91177308-0d34-0410-b5e6-96231b3b80d8

Final pass of minor cleanups for MachineInstr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28110 91177308-0d34-0410-b5e6-96231b3b80d8

Initial support for register pressure aware scheduling. The register reduction
scheduler can go into a "vertical mode" (i.e. traversing up the two-address
chain, etc.) when the register pressure is low.
This does seem to reduce the number of spills in the cases I've looked at. But
with x86, it's no guarantee the performance of the code improves.
It can be turned on with -sched-vertically option.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28108 91177308-0d34-0410-b5e6-96231b3b80d8

Remove redundancy and a level of indirection when creating machine operands

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28107 91177308-0d34-0410-b5e6-96231b3b80d8

Move register numbers out of "extra" into "contents".  Other minor cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28106 91177308-0d34-0410-b5e6-96231b3b80d8

Remove and simplify some more machineinstr/machineoperand stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28105 91177308-0d34-0410-b5e6-96231b3b80d8

Rename MO_VirtualRegister -> MO_Register.  Clean up immediate handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28104 91177308-0d34-0410-b5e6-96231b3b80d8

remove hasAllocatedReg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28103 91177308-0d34-0410-b5e6-96231b3b80d8

Move some methods out of MachineInstr into MachineOperand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28102 91177308-0d34-0410-b5e6-96231b3b80d8

Fix Transforms/InstCombine/2006-05-04-DemandedBitCrash.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28101 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase that crashes the instcombine pass

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28100 91177308-0d34-0410-b5e6-96231b3b80d8

There shalt be only one "immediate" operand type!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28099 91177308-0d34-0410-b5e6-96231b3b80d8

Change "value" in MachineOperand to be a GlobalValue, as that is the only
thing that can be in it.  Remove a dead method.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28098 91177308-0d34-0410-b5e6-96231b3b80d8

Revert Nate's CR patch from last night, which caused many regressions (e.g. fhourstones).

Loading and storing off R0 isn't what we wanted.  Also, taking some CR's out of
CRRC seems to cause failures as well.  Further investigation is required.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28097 91177308-0d34-0410-b5e6-96231b3b80d8

Make external globals public; other minor cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28096 91177308-0d34-0410-b5e6-96231b3b80d8

Make Intel syntax the default when LLVM is built with VC++.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28095 91177308-0d34-0410-b5e6-96231b3b80d8

Remove a bunch more dead V9 specific stuff

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28094 91177308-0d34-0410-b5e6-96231b3b80d8

Remove a bunch more SparcV9 specific stuff

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28093 91177308-0d34-0410-b5e6-96231b3b80d8

Remove some more V9-specific stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28092 91177308-0d34-0410-b5e6-96231b3b80d8

Remove some more unused stuff from MachineInstr that was leftover from V9.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28091 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify handling of relocations

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28090 91177308-0d34-0410-b5e6-96231b3b80d8

Use movsd to shuffle in the lowest two elements of a v4f32 / v4i32 vector when
movlps cannot be used (e.g. when load from m64 has multiple uses).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28089 91177308-0d34-0410-b5e6-96231b3b80d8

Change from using MachineRelocation ctors to using static methods
in MachineRelocation to create Relocations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28088 91177308-0d34-0410-b5e6-96231b3b80d8

minor cleanups, no functionality change

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28087 91177308-0d34-0410-b5e6-96231b3b80d8

Cleanup the internal implementation of MachineRelocation.  No interface or
functionality changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28086 91177308-0d34-0410-b5e6-96231b3b80d8

Attempt to get this script working on Darwin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28085 91177308-0d34-0410-b5e6-96231b3b80d8

For PR764:
Don't check in the LibDeps.txt and FinalLibDeps.txt files to CVS because
the content differs from platform to platform. Instead, adjust the makefile
so that a dummy llvm-config is built if Perl is not available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28084 91177308-0d34-0410-b5e6-96231b3b80d8

inline a simple method

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28083 91177308-0d34-0410-b5e6-96231b3b80d8

Suck block address tracking out of targets into the JIT Emitter.  This
simplifies the MachineCodeEmitter interface just a little bit and makes
BasicBlocks work like constant pools and jump tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28082 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a bug in Owen's checkin that broke the CBE on all non sparc v9 platforms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28081 91177308-0d34-0410-b5e6-96231b3b80d8

Teach the x86 jit how to handle jump tables not directly used by a jump
instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28080 91177308-0d34-0410-b5e6-96231b3b80d8

Finish up the initial jump table implementation by allowing jump tables to
not be 100% dense.  Increase the minimum threshold for the number of cases
in a switch statement from 4 to 6 in order to create a jump table.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28079 91177308-0d34-0410-b5e6-96231b3b80d8

A few instruction scheduling test cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28077 91177308-0d34-0410-b5e6-96231b3b80d8

Bottom up register pressure reduction work: clean up some hacks and enhanced
the heuristic to further reduce spills for several test cases. (Note, it may
not necessarily translate to runtime win!)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28076 91177308-0d34-0410-b5e6-96231b3b80d8

Set isStore of instructions with ISD::TRUNCSTORE root node.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28075 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses.  This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.

This fixes PR 759.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28074 91177308-0d34-0410-b5e6-96231b3b80d8

Align function bodies correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28073 91177308-0d34-0410-b5e6-96231b3b80d8

Add a new emitAlignment method

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28072 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify some code.  Don't add memory blocks to the Blocks list twice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28071 91177308-0d34-0410-b5e6-96231b3b80d8

Add assertions that verify that the actual arguments to a call or invoke match
the prototype of the called function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28070 91177308-0d34-0410-b5e6-96231b3b80d8

Change the BasicBlockAddrs map to be a vector, indexed by MBB number.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28069 91177308-0d34-0410-b5e6-96231b3b80d8

Keep the alpha JIT similar to the PPC/X86 jits

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28068 91177308-0d34-0410-b5e6-96231b3b80d8

Keep Visual Studio happy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28067 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify some code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28066 91177308-0d34-0410-b5e6-96231b3b80d8

Several related changes:

1. Change several methods in the MachineCodeEmitter class to be pure virtual.
2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them
   from the MachineCodeEmitter interface, and reducing the amount of target-
   specific code.
3. Change the JITEmitter so that it allocates constantpools and jump tables
   *right* next to the functions that they belong to, instead of in a separate
   pool of memory.  This makes all memory for a function be contiguous, and
   means the JITEmitter only tracks one block of memory now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28065 91177308-0d34-0410-b5e6-96231b3b80d8

Add a method for allocating space from the code buffer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28064 91177308-0d34-0410-b5e6-96231b3b80d8

Remove some stuff from the README

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28063 91177308-0d34-0410-b5e6-96231b3b80d8

Do not make the JIT memory manager manage the memory for globals.  Instead
just have the JIT malloc them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28062 91177308-0d34-0410-b5e6-96231b3b80d8

Minor cleanups, no functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28061 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a purely hypothetical problem (for now): emitWord emits in the host
byte format.  This doesn't work when using the code emitter in a cross target
environment.  Since the code emitter is only really used by the JIT, this
isn't a current problem, but if we ever start emitting .o files, it would be.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28060 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor the machine code emitter interface to pull the pointers for the current
code emission location into the base class, instead of being in the derived classes.

This change means that low-level methods like emitByte/emitWord now are no longer
virtual (yaay for speed), and we now have a framework to support growable code
segments.  This implements feature request #1 of PR469.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28059 91177308-0d34-0410-b5e6-96231b3b80d8

Since we don't handle callee-save CRs right yet, don't allocate them.  Also
don't step on R11 in the middle of a function when saving and restoring CRs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28058 91177308-0d34-0410-b5e6-96231b3b80d8

Print function number instead of name

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28057 91177308-0d34-0410-b5e6-96231b3b80d8

Hooray, everyone now uses the same printBasicBlockLabel implementation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28056 91177308-0d34-0410-b5e6-96231b3b80d8

Remove dead method

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28055 91177308-0d34-0410-b5e6-96231b3b80d8

Remove a now-dead method

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28054 91177308-0d34-0410-b5e6-96231b3b80d8

There is no reason to use a virtual method to store this word.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28053 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the debug machine code emitter.  The "FilePrinterEmitter" is moreuseful for debugging.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28052 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the debug machine code emitter.  The "FilePrinterEmitter" is more
useful for debugging.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28051 91177308-0d34-0410-b5e6-96231b3b80d8

Extend printBasicBlockLabel a bit so that it can be used to print all
basic block labels, consolidating the code to do so in one place for each
target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28050 91177308-0d34-0410-b5e6-96231b3b80d8

Update the PPC compilation callback code to not need weird abi-violating
prologs and epilogs, keep all the asm in one place, and remove use of
compiler builtin functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28049 91177308-0d34-0410-b5e6-96231b3b80d8

Add pass ID's for various passes, so they can be AddRequiredID.  Patch by
Domagoj Babic!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28048 91177308-0d34-0410-b5e6-96231b3b80d8

De-virtualize SwitchSection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28047 91177308-0d34-0410-b5e6-96231b3b80d8

De-virtualize EmitZeroes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28046 91177308-0d34-0410-b5e6-96231b3b80d8

Finish support for Microsoft ML/MASM.  May still be a few rough edges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28045 91177308-0d34-0410-b5e6-96231b3b80d8

Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more work).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28044 91177308-0d34-0410-b5e6-96231b3b80d8

Put instruction names into the first non TargetInstrInfo namespace found.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28043 91177308-0d34-0410-b5e6-96231b3b80d8

New testcase that crashes the new CFE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28042 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a latent bug that my spiller patch last week exposed: we were leaving
instructions in the virtregfolded map that were deleted.  Because they
were deleted, newly allocated instructions could end up at the same address,
magically finding themselves in the map.  The solution is to remove entries
from the map when we delete the instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28041 91177308-0d34-0410-b5e6-96231b3b80d8

When promoting a load to a reg-reg copy, where the load was a previous
instruction folded with spill code, make sure the remove the load from
the virt reg folded map.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28040 91177308-0d34-0410-b5e6-96231b3b80d8

Remove previous patch, which wasn't quite right.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28039 91177308-0d34-0410-b5e6-96231b3b80d8

instructions can be in different namespaces.  Make sure to use the right
one for each instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28038 91177308-0d34-0410-b5e6-96231b3b80d8

Put PHI/INLINEASM into the correct namespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28037 91177308-0d34-0410-b5e6-96231b3b80d8

Formating

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28036 91177308-0d34-0410-b5e6-96231b3b80d8

Dis-favor stores more

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28035 91177308-0d34-0410-b5e6-96231b3b80d8

Bottom up register-pressure reduction scheduler now pushes store operations
up the schedule. This helps code that looks like this:

loads ...
computations (first set) ...
stores (first set) ...
loads
computations (seccond set) ...
stores (seccond set) ...

Without this change, the stores and computations are more likely to
interleave:

loads ...
loads ...
computations (first set) ...
computations (second set) ...
computations (first set) ...
stores (first set) ...
computations (second set) ...
stores (stores set) ...

This can increase the number of spills if we are unlucky.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28033 91177308-0d34-0410-b5e6-96231b3b80d8

Mark instructions whose pattern is (store ...) isStore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28032 91177308-0d34-0410-b5e6-96231b3b80d8

Didn't mean ScheduleDAGList.cpp to make the last checkin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28030 91177308-0d34-0410-b5e6-96231b3b80d8

Remove temp. option -spiller-check-liveout, it didn't cause any failure nor performance regressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28029 91177308-0d34-0410-b5e6-96231b3b80d8

Intel mode no longer uses %'s on registers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28028 91177308-0d34-0410-b5e6-96231b3b80d8

Remove %'s from register names when in intel mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28027 91177308-0d34-0410-b5e6-96231b3b80d8

Format #APP lines a bit nicer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28026 91177308-0d34-0410-b5e6-96231b3b80d8

Local spiller kills a store if the folded restore is turned into a copy.
But this is incorrect if the spilled value live range extends beyond the
current BB.
It is currently controlled by a temporary option -spiller-check-liveout.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28024 91177308-0d34-0410-b5e6-96231b3b80d8

Mingw32 patches supplied by Anton Korobeynikov.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28023 91177308-0d34-0410-b5e6-96231b3b80d8

Remove a bogus transformation.  This fixes SingleSource/UnitTests/2006-01-23-InitializedBitField.c
with some changes I have to the new CFE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28022 91177308-0d34-0410-b5e6-96231b3b80d8

I can't spell: Register, not Regsiter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28021 91177308-0d34-0410-b5e6-96231b3b80d8

Implemented x86 inline asm b, h, w, k modifiers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28020 91177308-0d34-0410-b5e6-96231b3b80d8

Fix InstCombine/2006-04-28-ShiftShiftLongLong.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28019 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase miscompiled by instcombine

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28018 91177308-0d34-0410-b5e6-96231b3b80d8

Fix CodeGen/Generic/2006-04-28-Sign-extend-bool.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28017 91177308-0d34-0410-b5e6-96231b3b80d8

testcase that crashes the ppc backend, which can't sextinreg(i1)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28016 91177308-0d34-0410-b5e6-96231b3b80d8

Initial caller side support (for CCC only, not FastCC) of 128-bit vector
passing by value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28015 91177308-0d34-0410-b5e6-96231b3b80d8

Bare-bone X86 inline asm printer support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28014 91177308-0d34-0410-b5e6-96231b3b80d8