LoopSimplify::FindPHIToPartitionLoops()
Use ETForest instead of DominatorSet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35222 91177308-0d34-0410-b5e6-96231b3b80d8

LoopSimplify::FindPHIToPartitionLoops()
Use ETForest instead of DominatorSet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35221 91177308-0d34-0410-b5e6-96231b3b80d8

Code clean up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35220 91177308-0d34-0410-b5e6-96231b3b80d8

Minor bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35219 91177308-0d34-0410-b5e6-96231b3b80d8

bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted:
    mov lr, pc
    bx lr
So, the function was not called.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35218 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-gcc now requires -fnested-functions to enable them in C.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35217 91177308-0d34-0410-b5e6-96231b3b80d8

Break up huge line so that this file is almost readable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35216 91177308-0d34-0410-b5e6-96231b3b80d8

Regenerate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35215 91177308-0d34-0410-b5e6-96231b3b80d8

Don't delete things before their last use (avoids bad reads).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35214 91177308-0d34-0410-b5e6-96231b3b80d8

CopyToReg source operand can be a physical register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35213 91177308-0d34-0410-b5e6-96231b3b80d8

Test handling of structs with multiple variable-sized fields.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35212 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify isHighOnes().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35211 91177308-0d34-0410-b5e6-96231b3b80d8

Ada testcase for structs with multiple variable sized fields.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35210 91177308-0d34-0410-b5e6-96231b3b80d8

Test that ARRAY_RANGE_REF returns an array not an element.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35209 91177308-0d34-0410-b5e6-96231b3b80d8

First cut trivial re-materialization support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35208 91177308-0d34-0410-b5e6-96231b3b80d8

Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35207 91177308-0d34-0410-b5e6-96231b3b80d8

New entry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35206 91177308-0d34-0410-b5e6-96231b3b80d8

Added MRegisterInfo hook to re-materialize an instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35205 91177308-0d34-0410-b5e6-96231b3b80d8

Two changes:
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
   in three-address form.

This gives us asm diffs like:

-       leal (,%eax,4), %eax
+       shll $2, %eax

which is faster on some processors and smaller on all of them.

and, more interestingly:

-       movl 24(%esi), %eax
-       leal (,%eax,4), %edi
+       movl 24(%esi), %edi
+       shll $2, %edi

Without #2, #1 was a significant pessimization in some cases.

This implements CodeGen/X86/shift-codegen.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35204 91177308-0d34-0410-b5e6-96231b3b80d8

These functions should use shll, not lea.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35203 91177308-0d34-0410-b5e6-96231b3b80d8

fix indentation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35202 91177308-0d34-0410-b5e6-96231b3b80d8

Correct the name: isStrictPositive --> isStrictlyPositive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35201 91177308-0d34-0410-b5e6-96231b3b80d8

Add a dtor to fix leaks from all clients of BitVector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35200 91177308-0d34-0410-b5e6-96231b3b80d8

Regenerate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35199 91177308-0d34-0410-b5e6-96231b3b80d8

Plug some PATypeHolder memory leaks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35198 91177308-0d34-0410-b5e6-96231b3b80d8

use types of loads and stores, not address, in CheckForIVReuse

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35197 91177308-0d34-0410-b5e6-96231b3b80d8

fix obvious comment bug

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35196 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a nasty memory leak, caused by my revamp of the value symbol table.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35195 91177308-0d34-0410-b5e6-96231b3b80d8

Make isOneBitSet faster by using APInt::isPowerOf2. Thanks Chris.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35194 91177308-0d34-0410-b5e6-96231b3b80d8

Make this test a little simpler/faster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35193 91177308-0d34-0410-b5e6-96231b3b80d8

Add test case for PR1261, currently XFAILed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35192 91177308-0d34-0410-b5e6-96231b3b80d8

Document LoopPass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35191 91177308-0d34-0410-b5e6-96231b3b80d8

APIntify the isHighOnes utility function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35190 91177308-0d34-0410-b5e6-96231b3b80d8

Fix coding standards violation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35189 91177308-0d34-0410-b5e6-96231b3b80d8

Implement isMaxValueMinusOne in terms of APInt instead of uint64_t.
Patch by Sheng Zhou.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35188 91177308-0d34-0410-b5e6-96231b3b80d8

Implement isMinValuePlusOne using facilities of APInt instead of uint64_t
Patch by Zhou Sheng.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35187 91177308-0d34-0410-b5e6-96231b3b80d8

Implement isOneBitSet in terms of APInt::countPopulation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35186 91177308-0d34-0410-b5e6-96231b3b80d8

1. Use APInt::getSignBit to reduce clutter (patch by Sheng Zhou)
2. Replace uses of the "isPositive" utility function with APInt::isPositive

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35185 91177308-0d34-0410-b5e6-96231b3b80d8

Remove a redundant clause in an if statement.
Patch by Sheng Zhou.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35184 91177308-0d34-0410-b5e6-96231b3b80d8

Regenerate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35183 91177308-0d34-0410-b5e6-96231b3b80d8

Fix test/Assembler/2007-03-19-NegValue.ll by using the new "isSigned"
parameter on ConstantInt::get to indicate the signedness of the intended
value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35182 91177308-0d34-0410-b5e6-96231b3b80d8

Allow ConstantInt::get(Ty, uint64_t) to interpret the 64-bit values as a
negative number. This is needed to fix test/Assembler/2007-03-19-NegValue.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35181 91177308-0d34-0410-b5e6-96231b3b80d8

Implement extension of sign bits for negative values in the uint64_t
constructor. This helps to fix test/Assembler/2007-03-19-NegValue.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35180 91177308-0d34-0410-b5e6-96231b3b80d8

Add an indication of signedness to the uint64_t constructor so sign bits
can be extended. This helps fix test/Assembler/2007-03-19-NegValue.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35179 91177308-0d34-0410-b5e6-96231b3b80d8

Test case noticed by Sheng that fails because negative values that are
greater than 64-bits don't have the sign bits extended on construction of
the APInt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35178 91177308-0d34-0410-b5e6-96231b3b80d8

Fix mingw32 build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35177 91177308-0d34-0410-b5e6-96231b3b80d8

Test handling of ARRAY_REF when the component type is of unknown size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35176 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1258:
Test that invalid numbered value references get an error message.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35175 91177308-0d34-0410-b5e6-96231b3b80d8

Regenerate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35174 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1248:
Eliminate support for type planes in numbered values. This simplifies the
data structures involved in managing forward definitions, etc. Instead of
requiring maps from type to value, we can now just use a vector of values.
These changes also required rewrites of some support functions such as
InsertValue, getBBVal, and ResolveDefinitions. Some other cosmetic changes
were made as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35173 91177308-0d34-0410-b5e6-96231b3b80d8

Add and Operator== method to ValID so equality can be done properly for
named or numbered ValIDs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35172 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1258:
Radically simplify the SlotMachine. There is no need to keep Value planes
around any more. This change causes slot numbering to number all un-named,
non-void values starting at 0 and incrementing monotonically through the
function, regardless of type (including BasicBlocks). Getting slot numbers
is now a single lookup operation instead of a double lookup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35171 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1258:
Revise numeric value references to accommodate collapsed type planes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35170 91177308-0d34-0410-b5e6-96231b3b80d8

fix ScalarRepl/2007-03-19-CanonicalizeMemcpy.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35169 91177308-0d34-0410-b5e6-96231b3b80d8

Use opt instead of gccas.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35168 91177308-0d34-0410-b5e6-96231b3b80d8

add a testcase the resent patches fail on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35167 91177308-0d34-0410-b5e6-96231b3b80d8

Don't upgrade these.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35166 91177308-0d34-0410-b5e6-96231b3b80d8

Remove -reduce-joining-phys-regs options. Make it on by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35165 91177308-0d34-0410-b5e6-96231b3b80d8

Fix obvious typo in comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35164 91177308-0d34-0410-b5e6-96231b3b80d8

Fix naming inconsistencies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35163 91177308-0d34-0410-b5e6-96231b3b80d8

Special LDR instructions to load from non-pc-relative constantpools. These are
rematerializable. Only used for constant generation for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35162 91177308-0d34-0410-b5e6-96231b3b80d8

Constant generation instructions are re-materializable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35161 91177308-0d34-0410-b5e6-96231b3b80d8

Added isReMaterializable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35160 91177308-0d34-0410-b5e6-96231b3b80d8

Recognize target instruction flag 'isReMaterializable'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35159 91177308-0d34-0410-b5e6-96231b3b80d8

Add a TargetInstrDescriptor flag to mark an instruction as "re-materializable".
It means the instruction can be easily re-materialized at any point. e.g.
constant generation, load from constantpool.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35158 91177308-0d34-0410-b5e6-96231b3b80d8

Add isStrictPositive() to APInt to determine if this APInt Value > 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35156 91177308-0d34-0410-b5e6-96231b3b80d8

Minor bug fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35153 91177308-0d34-0410-b5e6-96231b3b80d8

fix a warning

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35152 91177308-0d34-0410-b5e6-96231b3b80d8

add PR#

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35151 91177308-0d34-0410-b5e6-96231b3b80d8

implement the next chunk of SROA with memset/memcpy's of aggregates.  This
implements Transforms/ScalarRepl/memset-aggregate-byte-leader.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35150 91177308-0d34-0410-b5e6-96231b3b80d8

add pr#

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35149 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35148 91177308-0d34-0410-b5e6-96231b3b80d8

testcase for SROA with memset etc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35147 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up this code and fix subtract miscompile.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35146 91177308-0d34-0410-b5e6-96231b3b80d8

Implement InstCombine/and-xor-merge.ll:test[12].
Rearrange some code to simplify it now that shifts are binops

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35145 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35144 91177308-0d34-0410-b5e6-96231b3b80d8

minor updates

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35143 91177308-0d34-0410-b5e6-96231b3b80d8

This is implemented. We now generate:

entry:
        icmp ugt i32 %x, 4              ; <i1>:0 [#uses=1]
        br i1 %0, label %cond_true, label %cond_false

cond_true:              ; preds = %entry
        %tmp1 = tail call i32 (...)* @bar( i32 12 )             ; <i32> [#uses=0]
        ret void

cond_false:             ; preds = %entry
        switch i32 %x, label %cond_true15 [
                 i32 4, label %cond_true3
                 i32 3, label %cond_true7
                 i32 2, label %cond_true11
                 i32 0, label %cond_false17
        ]

...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35142 91177308-0d34-0410-b5e6-96231b3b80d8

- Merge UsedBlocks info after two virtual registers are coalesced.
- Use distance to closest use to determine whether to abort coalescing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35141 91177308-0d34-0410-b5e6-96231b3b80d8

Keep UsedBlocks info accurate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35140 91177308-0d34-0410-b5e6-96231b3b80d8

Fix comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35139 91177308-0d34-0410-b5e6-96231b3b80d8

Propagate ValueRanges across equality.

Add some more micro-optimizations: x * 0 = 0, a - x = a --> x = 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35138 91177308-0d34-0410-b5e6-96231b3b80d8

Silence warning

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35137 91177308-0d34-0410-b5e6-96231b3b80d8

Track the BB's where each virtual register is used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35135 91177308-0d34-0410-b5e6-96231b3b80d8

Joining a live interval of a physical register with a virtual one can turn out
to be really bad. Once they are joined they are not broken apart. Also, physical
intervals cannot be spilled!

Added a heuristic as a workaround for this. Be careful coalescing with a
physical register if the virtual register uses are "far". Check if there are
uses in the same loop as the source (copy instruction). Check if it is in the
loop preheader, etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35134 91177308-0d34-0410-b5e6-96231b3b80d8

Use SmallSet instead of std::set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35133 91177308-0d34-0410-b5e6-96231b3b80d8

If sdisel has decided to sink GEP index expression into any BB. Replace all uses
in that BB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35132 91177308-0d34-0410-b5e6-96231b3b80d8

GEP index sink test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35131 91177308-0d34-0410-b5e6-96231b3b80d8

Test case for X86 inline asm constraint 'I'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35130 91177308-0d34-0410-b5e6-96231b3b80d8

Support 'I' inline asm constraint.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35129 91177308-0d34-0410-b5e6-96231b3b80d8

Only ARMv6 has BSWAP.
Fix MultiSource/Applications/aha test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35128 91177308-0d34-0410-b5e6-96231b3b80d8

Turn on GEP index sinking by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35127 91177308-0d34-0410-b5e6-96231b3b80d8

Stupid bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35126 91177308-0d34-0410-b5e6-96231b3b80d8

And now support for MMX logical operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35125 91177308-0d34-0410-b5e6-96231b3b80d8

Sink a binary expression into its use blocks if it is a loop invariant
computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35123 91177308-0d34-0410-b5e6-96231b3b80d8

Added isLegalAddressExpression(). Only allows X +/- C for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35122 91177308-0d34-0410-b5e6-96231b3b80d8

Added isLegalAddressExpression hook to test if the given expression can be
folded into target addressing mode for the given type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35121 91177308-0d34-0410-b5e6-96231b3b80d8

These forward declarations are not needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35120 91177308-0d34-0410-b5e6-96231b3b80d8

Add more comments and update to new asm syntax.

Add new micro-optimizations.

Add icmp predicate snuggling. Given %x ULT 4, "icmp ugt %x, 2" becomes
"icmp eq %x, 3". This doesn't apply in any non-trivial cases yet due to missing
support for NE values in ValueRanges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35119 91177308-0d34-0410-b5e6-96231b3b80d8

Multiplication support for MMX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35118 91177308-0d34-0410-b5e6-96231b3b80d8