SuccIterator on bbs without terminator insts

Remove the assert that triggers if SuccIterator is constructed for a basic block
without a terminator instruction. Instead of triggering an assert a succ_end()
iterator is returned. This models a basic block with zero successors and allows
us to use F->viewCFG() on incompletely constructed functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134398 91177308-0d34-0410-b5e6-96231b3b80d8

PR10267: Don't combine an equality compare with an AND into an inequality compare when the AND has more than one use.

This can pessimize code, inequalities are generally more expensive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134379 91177308-0d34-0410-b5e6-96231b3b80d8

Remove accidentaly left node from previous iteration of the patch.

Noticed by Benjamin Kramer!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134376 91177308-0d34-0410-b5e6-96231b3b80d8

Move early tail duplication earlier.

This fixes the issue noted in PR10251 where early tail dup of bbs with
indirectbr would cause a bb to be duplicated into a loop preheader
and then into its predecessors, creating phi nodes with identical
operands just before register allocation.

This helps with jsinterp.o size (__TEXT goes from 163568 to 126656)
and a bit with performance 1.005x faster on sunspider (jits still enabled).

The result on webkit with the jit disabled is more significant: 1.021x faster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134372 91177308-0d34-0410-b5e6-96231b3b80d8

Move most of the pre BB code to TailDuplicateAndUpdate. Change the
HasIndirectbr variable to be just that. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134371 91177308-0d34-0410-b5e6-96231b3b80d8

Reduce indentation and fix the count of how many PHIs we have inserted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134370 91177308-0d34-0410-b5e6-96231b3b80d8

Fix PR10244.

A split point inserted in a block with a landing pad successor may be
hoisted above the call to ensure that it dominates all successors. The
code that handles the rest of the basic block must take this into
account.

I am not including a test case, it would be very fragile. PR10244 comes
from building clang with exceptions enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134369 91177308-0d34-0410-b5e6-96231b3b80d8

Make the i64 and f64 be 64bit ABI aligned in the target description.
This is what both the ABI and clang says.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134367 91177308-0d34-0410-b5e6-96231b3b80d8

test/CodeGen/X86/lsr-nonaffine.ll: Relax expressions for Win64 CC to appease Win32 hosts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134366 91177308-0d34-0410-b5e6-96231b3b80d8

Fix an easy fixme.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134364 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize another test. Reduces the llc invocations from 8 to 1, and
makes one of the tests actually mean something (as the string 'add' will
always appear in the output of this file).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134358 91177308-0d34-0410-b5e6-96231b3b80d8

Avoid writing to an arbitrary filename during the test run by writing to
a file descriptor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134355 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize another X86 test, making it more precisely verify the
desired result based on the comments in the file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134354 91177308-0d34-0410-b5e6-96231b3b80d8

Quote two greps which contain parentheses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134353 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize and simplify RUN lines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134352 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134351 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize and tighten up assertions to only check the relevant sections.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134350 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize and cleanup IR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134349 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134348 91177308-0d34-0410-b5e6-96231b3b80d8

Remove a grep that is already checked with FileCheck.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134346 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134345 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize and modernize IR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134344 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize and simplify RUNs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134343 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize and modernize the RUN line.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134342 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize, tightening checks and avoiding a temporary file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134341 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize, tightening checks and avoiding a temporary file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134340 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134339 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134338 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize a test, avoiding a temporary file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134337 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize and simplify this test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134336 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134335 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize another codegen test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134334 91177308-0d34-0410-b5e6-96231b3b80d8

Partially FileCheck-ize a test to remove a weird quoting situation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134333 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize another test, and upgrade its syntax a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134332 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize another codegen test, tightening it up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134331 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize another test, making it much more precise for testing the
individual cases, while hard coding less about registers in use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134330 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize another test. This one is more clear and runs fewer
commands as a result.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134329 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheck-ize a test, no functionality changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134328 91177308-0d34-0410-b5e6-96231b3b80d8

Use subprocess.Popen instead of popen2 to stop a deprecation warning when running lit on OS X

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134324 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unused array.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134323 91177308-0d34-0410-b5e6-96231b3b80d8

Revert previous commit.  It seems that whether casting to void
is valid or not depends on which system you build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134321 91177308-0d34-0410-b5e6-96231b3b80d8

Supress gcc-4.5 warning about the result not being used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134319 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unused constant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134318 91177308-0d34-0410-b5e6-96231b3b80d8

Use getVNInfoAt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134312 91177308-0d34-0410-b5e6-96231b3b80d8

Consistent diagnostic capitalization and redundant context elimination.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134311 91177308-0d34-0410-b5e6-96231b3b80d8

Better diagnostics when inline asm fails to allocate.

asm.c:2:7: error: ran out of registers during register allocation
  asm(""::"r"(0), "r"(1), "r"(2), "r"(3), "r"(4), "r"(5), "r"(6), "r"(7), "r"(8), "r"(9));
        ^

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134310 91177308-0d34-0410-b5e6-96231b3b80d8

Check the VN of the src register at the two copies, not just the
register number.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134309 91177308-0d34-0410-b5e6-96231b3b80d8

Be less specific about register allocation ordering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134308 91177308-0d34-0410-b5e6-96231b3b80d8

Include a source location when complaining about bad inline assembly.

Add a MI->emitError() method that the backend can use to report errors
related to inline assembly. Call it from X86FloatingPoint.cpp when the
constraints are wrong.

This enables proper clang diagnostics from the backend:

$ clang -c pr30848.c
pr30848.c:5:12: error: Inline asm output regs must be last on the x87 stack
  __asm__ ("" : "=u" (d));  /* { dg-error "output regs" } */
           ^
1 error generated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134307 91177308-0d34-0410-b5e6-96231b3b80d8

indvars -disable-iv-rewrite: bug fix involving weird geps and related cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134306 91177308-0d34-0410-b5e6-96231b3b80d8

Use a new strategy for preventing eviction loops in RAGreedy.

Every live range is assigned a cascade number the first time it is
involved in an eviction. As the evictor, it gets a new cascade number.
Every evictee is assigned the same cascade number as the evictor.

Eviction is prohibited if the evictor has a lower assigned cascade
number than the evictee.

This means that assigned cascade numbers are monotonically increasing
with every eviction, yet they are bounded by NextCascade which can only
be incremented by new live ranges. Thus, infinite loops cannot happen,
but eviction cascades can still be triggered by new live ranges as we
want.

Thanks to Andy for explaining this to me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134303 91177308-0d34-0410-b5e6-96231b3b80d8

Add getFeatureBits to extract feature bits for a given CPU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134298 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the confusing getDarwinNumber() api and friends.

Part of rdar://9714064

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134291 91177308-0d34-0410-b5e6-96231b3b80d8

Take a stab at fixing the llvm-x86_64-linux-checks failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134287 91177308-0d34-0410-b5e6-96231b3b80d8

TargetConstant immediates won't be placed into registers so tighten
up the valid constant check earlier.

rdar://9692967

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134286 91177308-0d34-0410-b5e6-96231b3b80d8

Add initial *-*-rtems* target, from Joel Sherrill

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134282 91177308-0d34-0410-b5e6-96231b3b80d8

Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8

Add MCSubtargetInfo target registry stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134279 91177308-0d34-0410-b5e6-96231b3b80d8

Teach IVUsers to stop at non-affine expressions unless they are both
outside the loop and reducible.

This more completely hides them from LSR, which isn't usually able to
do anything meaningful with non-affine expressions anyway, and this
consequently hides them from SCEVExpander, which is acutely unprepared
for non-affine expressions.

Replace test/CodeGen/X86/lsr-nonaffine.ll with a new test that tests
the new behavior.

This works around the bug in PR10117 / rdar://problem/9633149, and is
generally an improvement besides.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134268 91177308-0d34-0410-b5e6-96231b3b80d8

Generalize @llvm.ctlz, @llvm.cttz, and @llvm.ctpop to work on vectors of integers, and fix the one optimization pass that I'm aware of that needs updating for this.  At least one current target, ARM NEON, can implement these operations on vectors directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134265 91177308-0d34-0410-b5e6-96231b3b80d8

Calling-convention specifications for illegal types are no-ops.  Simplify based on this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134264 91177308-0d34-0410-b5e6-96231b3b80d8

ARMv7M vs. ARMv7E-M support.

The DSP instructions in the Thumb2 instruction set are an optional extension
in the Cortex-M* archtitecture. When present, the implementation is considered
an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation."

Add a subtarget feature hook for the v7e-m instructions and hook it up. The
cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is
a v7e-m implementation.

rdar://9572992

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134261 91177308-0d34-0410-b5e6-96231b3b80d8

Rename TargetSubtarget to TargetSubtargetInfo for consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8

- Added MCSubtargetInfo to capture subtarget features and scheduling
  itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
  and hide more details from targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8

Fix off-by-one error.

(low two bits always zero, so off by one bit of encoded value).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134247 91177308-0d34-0410-b5e6-96231b3b80d8

Hide the call to InitMCInstrInfo into tblgen generated ctor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8

Pseudo-ize t2MOVCC[ri].

t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them.
The Thumb1 versions, tMOVCC[ri] were only present for use by the size-
reduction pass, so they're no longer necessary at all and can be deleted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134242 91177308-0d34-0410-b5e6-96231b3b80d8

Eliminate one extra conversion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134240 91177308-0d34-0410-b5e6-96231b3b80d8

Disable commit 134216 ("Add 134199 back, but disable the optimization when the second
copy is a kill") to see if it fixes the i386 dragonegg buildbot, which is timing out
because gcc built with dragonegg is going into an infinite loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134237 91177308-0d34-0410-b5e6-96231b3b80d8

Another misuse of StringRef. MSVC is very sensitive to that kind of error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134236 91177308-0d34-0410-b5e6-96231b3b80d8

Fix likely typo, reduce number of instruction name collisions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134235 91177308-0d34-0410-b5e6-96231b3b80d8

Fix use after free.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134234 91177308-0d34-0410-b5e6-96231b3b80d8

Avoid DenseMap lookup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134231 91177308-0d34-0410-b5e6-96231b3b80d8

Fix off by one error. I misunderstood the comment about killedAt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134229 91177308-0d34-0410-b5e6-96231b3b80d8

Check the liveinterval, not the kill flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134228 91177308-0d34-0410-b5e6-96231b3b80d8

Don't inflate register classes used by inline asm.

The constraints are represented by the register class of the original
virtual register created for the inline asm. If the register class were
included in the operand descriptor, we might be able to do this.

For now, just give up on regclass inflation when inline asm is involved.

No test case, this bug hasn't happened yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134226 91177308-0d34-0410-b5e6-96231b3b80d8

Improve Mips back-end's handling of DBG_VALUE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134224 91177308-0d34-0410-b5e6-96231b3b80d8

Improve constant folding of undef for cmp and select operators.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134223 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for the 'j' immediate constraint. This is conditionalized on
supporting the instruction that the constraint is for 'movw'.

Part of rdar://9119939

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134222 91177308-0d34-0410-b5e6-96231b3b80d8

Improve constant folding of undef for binary operators.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134221 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for the ARM 't' register constraint. And another testcase
for the 'x' register constraint.

Part of rdar://9119939

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134220 91177308-0d34-0410-b5e6-96231b3b80d8

Switch SubtargetFeatures from std::string to StringRef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134219 91177308-0d34-0410-b5e6-96231b3b80d8

We'll return a null RC by default if we can't match.

Part of rdar://9119939

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134217 91177308-0d34-0410-b5e6-96231b3b80d8

Add 134199 back, but disable the optimization when the second copy is a kill.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134216 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for the 'x' constraint.

Part of rdar://9307836 and rdar://9119939

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134215 91177308-0d34-0410-b5e6-96231b3b80d8

Remove tabs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134212 91177308-0d34-0410-b5e6-96231b3b80d8

Capitalize the unsigned part of the initializer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134211 91177308-0d34-0410-b5e6-96231b3b80d8

Rename Pair to RCPair lacking any better naming ideas.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134210 91177308-0d34-0410-b5e6-96231b3b80d8

Improve comment: Show the register the DWARF label is added to.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134209 91177308-0d34-0410-b5e6-96231b3b80d8

Use the correct registers on X86_64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134208 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a problem with fast-isel return values introduced in r134018.

We would put the return value from long double functions in the wrong
register.

This fixes gcc.c-torture/execute/conversion.c

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134205 91177308-0d34-0410-b5e6-96231b3b80d8

Refact ARM Thumb1 tMOVr instruction family.

Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134204 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for the 'h' constraint.

Part of rdar://9119939

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134203 91177308-0d34-0410-b5e6-96231b3b80d8

Add target a target hook to get the register number used by the compact unwind
encoding for the registers it knows about. Return -1 if it can't handle that
register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134202 91177308-0d34-0410-b5e6-96231b3b80d8

Revert my previous patch while I debug llvm-gcc bootstrap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134201 91177308-0d34-0410-b5e6-96231b3b80d8

Add one more comment to the FDE verbose asm output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134200 91177308-0d34-0410-b5e6-96231b3b80d8

Don't give up on coalescing A and B when we find

A = X
B = X

Instead, proceed as if we had found

A = X
B = A

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134199 91177308-0d34-0410-b5e6-96231b3b80d8

Add a convenience typedef for std::pair<unsigned, const TargetRegisterClass*>.

No functional change.

Part of rdar://9119939

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134198 91177308-0d34-0410-b5e6-96231b3b80d8

Thumb1 register to register MOV instruction is predicable.

Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134197 91177308-0d34-0410-b5e6-96231b3b80d8

Add comments to the FDE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134196 91177308-0d34-0410-b5e6-96231b3b80d8