CHROMIUM: [media] v4l: Add private compound control type.

V4L2_CTRL_TYPE_PRIVATE is to be used for private driver compound
controls that use the "ptr" member of struct v4l2_ext_control.

BUG=chrome-os-partner:33728
TEST=build

Signed-off-by: Pawel Osciak <posciak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/228988
Trybot-Ready: Tomasz Figa <tfiga@chromium.org>
Tested-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Wu-cheng Li <wuchengli@chromium.org>
Commit-Queue: Tomasz Figa <tfiga@chromium.org>

Change-Id: I44083b0216ef32629d12f0910e972a3e827a599a
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

CHROMIUM: v4l2-ctrls: add function to apply a configuration store.

Drivers need to be able to select a specific store. Add a new function that can
be used to apply a given store.

Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
BUG=chrome-os-partner:33728
TEST=build

Signed-off-by: Pawel Osciak <posciak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232585
Trybot-Ready: Tomasz Figa <tfiga@chromium.org>
Tested-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Wu-cheng Li <wuchengli@chromium.org>
Commit-Queue: Tomasz Figa <tfiga@chromium.org>

Change-Id: I3b80a31681765836a134812ebc56686324ca5194
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

CHROMIUM: Add config store support

Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
BUG=chrome-os-partner:33728
TEST=build

Signed-off-by: Pawel Osciak <posciak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232584
Trybot-Ready: Tomasz Figa <tfiga@chromium.org>
Tested-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Wu-cheng Li <wuchengli@chromium.org>
Commit-Queue: Tomasz Figa <tfiga@chromium.org>

Conflicts:
drivers/media/v4l2-core/v4l2-ctrls.c
include/media/v4l2-ctrls.h

[rebase44(groeck): Resolved conflicts]
Signed-off-by: Guenter Roeck <groeck@chromium.org>
Conflicts:
drivers/media/v4l2-core/v4l2-ctrls.c

Change-Id: I0b2e66f3331cab91d209868f5d5f67f795a0e72c
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

CHROMIUM: videodev2.h: rename reserved2 to config_store in v4l2_buffer.

When queuing buffers allow for passing the configuration store ID that
should be associated with this buffer. Use the 'reserved2' field for this.

Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
BUG=chrome-os-partner:33728
TEST=build

Signed-off-by: Pawel Osciak <posciak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232583
Trybot-Ready: Tomasz Figa <tfiga@chromium.org>
Tested-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Wu-cheng Li <wuchengli@chromium.org>
Commit-Queue: Tomasz Figa <tfiga@chromium.org>

Conflicts:
drivers/media/v4l2-core/videobuf2-core.c

[rebase44(groeck): fixed conflicts; structural changes to match v4.4]
Signed-off-by: Guenter Roeck <groeck@chromium.org>
Conflicts:
drivers/media/v4l2-core/v4l2-compat-ioctl32.c

Change-Id: Ibb823e9369bec79645e09651b0dda006ed53ecc5
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

CHROMIUM: videodev2.h: add config_store to v4l2_ext_controls

The ctrl_class is fairly pointless when used with drivers that use the control
framework: you can just fill in 0 and it will just work fine. There are still
some old unconverted drivers that do not support 0 and instead want the control
class there. The idea being that all controls in the list all belong to that
class. This was done to simplify drivers in the absence of the control framework.

When using the control framework the framework itself is smart enough to allow
controls of any class to be included in the control list.

Since configuration store IDs are in the range 1..255 (or so, in any case a relatively
small non-zero positive integer) it makes sense to effectively rename ctrl_class
to config_store. Set it to 0 and you get the normal behavior (you change the current
control value), set it to a configuration store ID and you get/set the control for
that store.

Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
BUG=chrome-os-partner:33728
TEST=build

Signed-off-by: Pawel Osciak <posciak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232582
Trybot-Ready: Tomasz Figa <tfiga@chromium.org>
Tested-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Wu-cheng Li <wuchengli@chromium.org>
Commit-Queue: Tomasz Figa <tfiga@chromium.org>

Conflicts:
include/uapi/linux/videodev2.h

Change-Id: I862bb5796e27bcbbd055e22202ac9a1ed0cc6f7d
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

CHROMIUM: ARM: dts: rockchip: assigned parents for vop dclks

The VOP DCLK is used to generate panel clocks.

For veyron, we have decided to permanently assign vop0 for
use with HDMI and vop1 for use with eDP.

Furthermore, to allow us to generate a wide range of precise pixel clocks,
we will be dedicating the NPLL exclusively for use as the parent clock
for VOP0/HDMI.

To implement the exclusive assignment of NPLL in the kernel, we remove
the NPLL entry from all clock muxes that would otherwise be able to select
it (such as vop1).  For vop0, we remove all choices *except* NPLL.

Before booting the kernel, the bios will configure vop0 and vop1 as it
sees fit - potentially assigning NPLL to vop1 and some other PLL to vop0.

Thus, at boot it is possible that from the kernel's perspective, these
clocks are orphans.  To fix this, we explicitly assign their clock parents
to ensure that they are properly parented no matter what state they are
when the kernel boots.

Change-Id: Iafe301abcbf211246fda66519cea5fc946af97ee
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>

CHROMIUM: videodev2.h: add V4L2_CTRL_FLAG_CAN_STORE

Controls that have a configuration store will set this flag.

Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
BUG=chrome-os-partner:33728
TEST=build

Signed-off-by: Pawel Osciak <posciak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232581
Trybot-Ready: Tomasz Figa <tfiga@chromium.org>
Tested-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Wu-cheng Li <wuchengli@chromium.org>
Commit-Queue: Tomasz Figa <tfiga@chromium.org>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Conflicts:
include/uapi/linux/videodev2.h

[rebase44(groeck): Resolved conflicts]
Signed-off-by: Guenter Roeck <groeck@chromium.org>
Change-Id: I88ccf65a5c6f11381cfacb4c328b589194f249ec
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

FROMLIST: ARM: dts: rockchip: add the panel power supply for rk3288-evb board with rk808 pmu

Panel regulator is controller by a normal GPIO, so we need to
write a regulator-fixed node for it.

Change-Id: I24a0f2787ef3bb93422296e8a97c076040460ccc
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9201801/)

FROMLIST: ARM: dts: rockchip: add the panel power supply for rk3288-evb board with act8846 pmu

Panel regulator is controller by a normal GPIO, so we need to
write a regulator-fixed node for it.

Change-Id: I4368b16bf49ef04a539aad154f7c16b094bfc382
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9201803/)

FROMLIST: ARM: dts: rockchip: add eDP/panel display device nodes for rk3288-evb

The default eDP panel on RK3288 EVB board is LG LP079QX1-SP0V TFT LCD,
we haven't declared the panel regulator in the 'panel-simple' device
node here, so the specific board like ACT8846 / RK8080 need to support
the panel power supply.

Change-Id: Ibf4a6457d606027eaa91cacf6fde2241376afd13
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9201815/)

dt-bindings: Add support for AUO B101EW05 1280x800 panel

The AUO B101EW05 panel is a 10.1" 1280(RGB)x800 WXGA TFT-LCD panel,
connected using LVDS interfaces.

Change-Id: Ic80369353f5e1726d2ea2ace6d53bb2bcdae6fc2
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm/panel: simple: Add support for AUO B101EW05 1280x800 panel

The AUO B101EW05 panel is a 10.1" 1280(RGB)x800 WXGA TFT-LCD panel,
connected using LVDS interfaces

Change-Id: Ic67fe5793a975b585cecfb8da02e81cd9fa6346f
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

dt-bindings: add support Chunghwa CLAA070WP03 800x1280 panel

Chunghwa CLAA070WP03 is 7” color TFT-LCD module composed of LCD
panel, LVDS driver ICs, control circuit and backlight. This module
supports 800x1280 mode.

Change-Id: I7f71464a80725d648802918740e64a0368f5c480
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

drm/panel: simple: add support Chunghwa CLAA070WP03 800x1280 panel

Chunghwa CLAA070WP03 is 7” color TFT-LCD module composed of LCD panel,
LVDS driver ICs, control circuit and backlight. This module supports
800x1280 mode.

Change-Id: I6a6339ad25664e2e47fc0e0de5c079db3494bd25
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM: dts: rockchip: enable GPU support on RK3288 EVB board with act8846 pmu

Change-Id: I92e43f6dd5563a9b8f423cf03f17dad60b4497ab
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

ARM: dts: rockchip: add GPU device node for RK3288

RK3288 have integrated the Mali-T760

Change-Id: Id5f98f8c236049c7936c44290e93dfef9dee0c3b
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

UPSTREAM: ARM: dts: rockchip: add 2 regulators for rk3288-evb-act8846

vcc_wl and vcc_lcd are 2 gpio switches for rk3288-evb-act8846 board.

Change-Id: I49fc20665adf4176d672fdd3e4030ee472f558a8
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(cherry pick from commit 662513a14c9dd1ba2b4d5928d6eae443744edefc)

video: rockchip: vop: 3399: fix layer0 perpixel alpha error

Change-Id: I5d4947ab131d39ebc611ba78100e05aa95c4b3e9
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

ARM64: kernel: dump kernel addresses larger than VA_START

The arm64 virtual addresses of kernel are like:
VA_START < MODULES_VADDR < KIMAGE_VADDR < PAGE_OFFSET.
PAGE_OFFSET is the virtual address of the start of the linear map.
And the vmalloc, kernel code and so on are between VA_START and
PAGE_OFFSET, so it is necessary to expand dump addresses to VA_START,
instead of PAGE_OFFSET.

Change-Id: I810ed216862de4c6e68b92d483de4aa68da532b8
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

ARM: dts: rockchip: add the supports-emmc for rk3288 emmc property

I don't need send for upstream since the rockchip inside kernel
need it for tuning. At least the upstream can work it with dwmmc.

Change-Id: I73c12b455c7dc5320d6c06f9e29ddec5c4a6def5
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

UPSTREAM: ARM: dts: rockchip: add GMAC nodes for RK322x SoCs

This patch add the GMAC dt nodes for rk322x SoCs.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-armsoc/dts32 commit 5d3d7c72b920f9aa44f9b64cdd8a1c5bf5cbea07)

Change-Id: I85467b7253fda16c242d91bcdd207d0175ee0db3
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ARM: dts: rockchip: add i2s nodes for RK322x SoCs

This patch add the i2s dt nodes for rk322x SoCs.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-armsoc/dts32 commit ccada2489206b5f1870ac132408bf41ffe51995a)

Change-Id: I51607de71835be896b2134516c159f9d6831ae3e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ARM: dts: rockchip: rename rk3228.dtsi to rk322x.dtsi

We have the brother chipset that RK3228 and RK3229, they share most
of dts configuration, but there are a number of different features.
In order to develop the future when they are easy to distinguish,
we need them to be independent.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-armsoc/dts32 commit 8372d93df7c265a67676dcd329da9588cc769192)

Change-Id: I0b3c91cddb3ca919b165ba1ec5b2b9466945546d
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ARM: dts: rockchip: add i2c nodes for RK3228 SoCs

This patch add the i2c dt nodes for rk3228 SoCs.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-armsoc/dts32 commit d549df4b225ad2386cbf59254eab2ec116babdca)

Change-Id: I8f607b3af6b07bec509bb3645af6bf3ad59af3f5
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ARM: dts: rockchip: remove broken-cd from emmc and sdio

Only one of "broken-cd" and "non-removable" should be supplied
according to Documentation/devicetree/bindings/mmc/mmc.txt.
Obviously emmc and sdio-wifi are non-removable devices, while
broken-cd is for removable device whose card detect pin is broken.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-armsoc/dts32 commit 57375d88fa3f6bf9351051529464c708f72adb1d)

Change-Id: Ie8df62156fbc96c0c9e16d05389b2f230b261f0e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ARM: dts: rockchip: enable the tsadc for rk3228 evb

This patch enables the tsadc for rk3228 evb board.

The rk3228 evb board uses the CRU to reset the chip since it hasn't the
PMIC to connect it, and TSHUT is low active on evb board.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-armsoc/dts32 commit 26f5e19dfb07de627112074721f254482f941dab)

Change-Id: I12ce9b1e2fb2c740bef100a22d746d5e128253e6
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ARM: dts: rockchip: add the thermal main info found on rk3228

This patch adds the thermal needed main information for rk3228 SoCS.

Basically has the following content:

1) TSADC controller:
Add the needed attributes for rk3036 TSADC controller.

Especially for the TSHUT, in some cases if we are unable to shut it down
in orderly fashion (says: kernel is stuck holding a lock or similar), then
hardware TSHUT will reset it.
If the temperature is over 95C over a period of time the thermal shutdown
of the tsadc is invoked with can either reset the entire chip via the CRU,
or notify the PMIC via a GPIO. This should be set in the specific board.

2) Thermal zones:
Add the needed device mode for thermal generic framework.
Detail in Documentation/devicetree/bindings/thermal/thermal.txt.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-armsoc/dts32 commit 7796031eec9e41099af35bc531f04843358fa3f1)

Change-Id: I415d5ac7ba2bca2259821dae6af98970e039d455
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ARM: dts: rockchip: add rk3228-evb board

Initial release for rk3228 sdk board.

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-armsoc/dts32 commit 67e044a510d0e00656ae2ab4f0ee30971a2f40e7)

Conflicts:

Documentation/devicetree/bindings/arm/rockchip.txt
[zx: conflict with rk339 description, place over it.]

Change-Id: I10d4e71abb424f8997145cd51fa30257c8401cfb
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: ARM: dts: rockchip: add core rk3228 dtsi

Initial release for rk3228 shared dtsi.

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-armsoc/v4.8-armsoc/dts32 commit 9848ebeb952d2a46852bdde96101d280fc69b54b)

Change-Id: I98ae8a73a5a46c2d2e82ae590d24f932c5426ddb
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM: dts: rockchip: remove unused rk3228 dts files

There are old v3.10 dts and unsuitable for v4.4, we need to remove them.

Change-Id: I070fb1fd5d513883f43dfbdab6f173e68fe48e72
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM: rockchip: rk3288: Switch to use the proper PWM IP

The rk3288 SoC has an option to switch all of the PWMs in the system
between the old IP block and the new IP block.  The new IP block is
working and tested and the suggested PWM to use, so setup the SoC to
use it and then we can pretend that the other IP block doesn't exist.

This code could go lots of other places, but we've put it here.  Why?
- Pushing it to the bootloader just makes the code harder to update in
  the field.  If we later find a bug in the new IP block and want to
  change our mind about what to use we want it to be easy to update.
- Putting this code in the driver for IP block is a lot of extra work,
  device tree bindings, etc.  Now that the new IP block is validated
  it's likely no future SoCs will need this code.  Why pollute the PWM
  driver with this?  This is an rk3288 thing so it should be in rk3288
  code.
- There's a single bit that switches over PWMs, which makes it extra
  hard to put this under the PWM device tree nodes.

Change-Id: Ib178129fc4f24f71d3a6f7315f757f91b5bdf534
Signed-off-by: Doug Anderson <dianders@chromium.org>

ARM64: dts: rk3366-tb: change usb2-host vbus supply as a regulator

Change-Id: I16cef5cc1b925ac26e92301ec84172213e4eb93f
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

ARM64: dts: rk3366: add usb2-vbus gpio into pinctrl entry

Change-Id: I3379360efc32ba455f1934760af8b968c8748984
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

FROMLIST: phy: rockchip-inno-usb2: add a new driver for Rockchip usb2phy

The newer SoCs (rk3366, rk3399) take a different usb-phy IP block
than rk3288 and before, and most of phy-related registers are also
different from the past, so a new phy driver is required necessarily.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Suggested-by: Heiko Stuebner <heiko@sntech.de>
Suggested-by: Guenter Roeck <linux@roeck-us.net>
Suggested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
(merge from https://patchwork.kernel.org/patch/9190287/)

Change-Id: I3e7739dee6057928172904565c10cebf9785fec6
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

FROMLIST: Documentation: bindings: add DT documentation for Rockchip
USB2PHY

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
(merge from https://patchwork.kernel.org/patch/9190285/)

Change-Id: I7199a4e84f13e58e98d5c0d21ce01837e961c3e8
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

FROMLIST: dt-bindings: Add support for LG LP079QX1-SP0V 1536x2048 panel

The LG LP079QX1-SP0V is an 7.9" QXGA TFT with LED Backlight unit and
32 pins eDP interface. This module supports 1536x2048 mode.

Change-Id: I3f56b58935e47bb062d62521a019f36baae4be7a
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9201795/)

FROMLIST: drm/panel: simple: Add support for LG LP079QX1-SP0V 1536x2048 panel

The LG LP079QX1-SP0V is an 7.9" QXGA TFT with LED Backlight unit and
32 pins eDP interface. This module supports 1536x2048 mode.

Change-Id: Ib42185ffce772160133a3edf3c3cf61bff4b85c5
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9201799/)

iio: imu: inv-mpu6xxx: Fix interrupt pin assignment

When add spi support, introduce a new bug that
i2c intrerupt pin assignment after request_irq.

Change-Id: Id41a953c8c7ea8a94a584c584ee012025a4a6921
Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>

FROMLIST: drm/rockchip: vop: correct the source size of uv scale factor setting

When the input color format is YUV, we need to do some external scale
for CBCR. Like,
 * In YUV420 data format:
     cbcr_xscale = dst_w / src_w * 2;
     cbcr_yscale = dst_h / src_h * 2;
 * In YUV422 data format:
     cbcr_xscale = dst_w / src_w * 2;
     cbcr_yscale = dst_h / src_h;
 * In YUV444 data format
     cbcr_xscale = dst_w / src_w;
     cbcr_yscale = dst_h / src_h;

Change-Id: I73e0423d3662bd340b5d155996f13d31c22dcc29
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9157353/)

FROMLIST: drm/rockchip: vop: add uv_vir register field for RK3036 VOP

The WIN0 of RK3036 VOP could support YUV data format, but driver
forget to add the uv_vir register field for it.

Change-Id: Ie27216d0612d41fec02346ce65412207ed26d4a1
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9157349/)

soc: rockchip: power-domain: fix up the PMU_GPU_PWRDW/UP_CNT for RK3399

According to the advice of the IC,
setting the PMU_GPU_PWRDW/PWRUP_CNT regs 6 cycel(250ns) for RK3399 SOC.

Change-Id: I0449069a3b5035bd0442fcd74b645de9480a1d89
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: dts: rockchip: rk3366: assign parent for i2s_src

As the 750MHz cpll can't produce accurate frequancy for i2s,
for example 11289600Hz, so assign their parents to the 576MHz gpll.

Change-Id: I430bce21ae69b47e561a95e691276d0c921a702c
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: add clock ids for i2s_src on RK3366

Set the newly added id for i2s_src, so that they can be called
in other parts.

Change-Id: Ie4ecc4d19e3ae64a07d1f2a80aa08d40f38d09ad
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

FIXUP: drm/bridge: analogix_dp: misc update to upstream version

This misc update would try to fix below comments from my eDP thread[0],
and lucky to say this version is stable, and i'm start to perpare the
pull request to David with this version. So i guess it's time to create
a misc FIXUP patch to address the comments.

[0]: https://patchwork.kernel.org/patch/9175613/

- Correct the misspell of "marcos" in commit message (Dominik, reviewed at Google Gerrit)
- Write a kerneldoc-style comment explaining the chips data fields (Tomasz, reviewed at Google Gerrit)
- Drop the '.lcdcsel_mask' number in chips data field (Tomasz, reviewed at Google Gerrit)
- Make this hack code more clear (Tomasz, reviewed at Google Gerrit)
  reg = ~reg & REF_CLK_MASK;  --->  reg ^= REF_CLK_MASK;
- Give the "rk3399-edp" a separate line for clarity in document (Tomasz, reviewed at Google Gerrit)
- Move 'output_type' setting before the return statement (Tomasz, reviewed at Google Gerrit)
- Avoid to change any internal driver state in .mode_valid interface. (Tomasz, reviewed at Google Gerrit)
- Hook the connector's color_formats in .get_modes directly. (Tomasz, reviewed at Google Gerrit)

Change-Id: Ic35f166ebac04e417ff3d135e7bf4573bbca2004
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

UPSTREAM: ARM: dts: rockchip: add rk3288-veyron-minnie backlight and panel settings

The pwm for Minnie's backlight needs to be above 1%, so adapt the start
of non-zero brightness accordingly. Minnie is also using a different
panel, so re-set the compatible property.

Change-Id: I4fd13be0a848ca7a33213e07864637bf3792f9af
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
(cherry pick from commit 712e6051c440a41f5e797412afa7b246d27adc69)

UPSTREAM: ARM: dts: rockchip: add core rk3288-veyron backlight and panel nodes

Many Veyron chromebooks share the same panel type, so define the core
settings for all of them and allow the few runaways to override it later.

Change-Id: I48668b9fa156f02de94a2ac8c0a20a3407a201b0
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
(cherry pick from commit dfb2146efc6b07f1a6cc04938248c2ce948c9c98)

UPSTREAM: ARM: dts: rockchip: move edp-hpd pin definition into common location

The edp hotplug pin is fixed on the soc side, anybody wanting to use it
will need the same definition anyway, so move it to a common location.

Change-Id: I49a424eeb755d6bfaf38b91cadfd6d8ff7be8ccf
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
(cherry pick from commit a4e00345b29dbc93fe7e6f4070458f325261b0ac)

UPSTREAM: ARM: dts: rockchip: add rk3288 displayport controller node

Add the rk3288 edp node and its hooks into the display-subsystem.

Change-Id: I1bd7617203e9c36c426bd69fd23f99c1e10a8c99
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
(cherry pick from commit 6df7ec6186644a4ffb4f0c859327ef41a1145a5f)

UPSTREAM: ARM: dts: rockchip: add rk3288 edp-phy node

Add the core device node of the edp-phy on rk3288 socs.

Change-Id: I34d23617abfaeefa5ec527c7b2ce67bc3b614c68
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
(cherry pick from commit f5663969d8125a5c5b7835812e1e636ecedf030b)

UPSTREAM: drm/rockchip: remove rockchip_drm_encoder_get_mux_id

It is replaced by drm_of_encoder_active_endpoint_id.

Change-Id: I0d09b768951192cd781d0b5c3e5652f66dc4cdaa
Suggested-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Yakir Yang <ykk@rock-chips.com>
[for dw_hdmi-rockchip]
Acked-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
(cherry-pick from commit 16450616790af5ef5dda79e3081916af723756da)

UPSTREAM: drm: add drm_of_encoder_active_endpoint helpers

This patch adds a helper to parse the encoder endpoint connected to the
encoder's crtc and two helpers to return its id and port id.

This can be used to determine input mux setting from endpoint or port ids.

Change-Id: I48eb7c66edb951af40085e4e388afbd5d4b2c77b
Suggested-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
(cherry pick from commit 4cacf91fcb1d7118e93caf9cb6651d7f7b56e58d)

UPSTREAM: phy: Add driver for rockchip Display Port PHY

Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.

Change-Id: Ied28937c12584aee9654af775d4cf0cac4eddec5
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
(cherry pick from commit fd968973de95c68982babf3d9723dcde2f2a87cf)

mmc: dw_mmc: fix unmap sg twice when finding data err

DATA_OVER(the same for RI/TI of IDMAC) interrupt may come
up together with data error interrupts. If so, the interrupt
routine set EVENT_DATA_ERR to the pending_events and schedule
the tasklet but we may still fallback to the IDMAC interrupt
case as the tasklet may come up a little late, namely right
after the IDMAC interrupt checking. This will casue dw_mmc
unmap sg twice. We can easily see it with CONFIG_DMA_API_DEBUG
enabled.

WARNING: CPU: 0 PID: 0 at lib/dma-debug.c:1096 check_unmap+0x7bc/0xb38
dwmmc_exynos 12200000.mmc: DMA-API: device driver tries to free DMA memory it
has not allocated [device address=0x000000006d9d2200]
[size=128 bytes]
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.7.0-rc4 #26
Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
[<c0112b4c>] (unwind_backtrace) from [<c010d888>] (show_stack+0x20/0x24)
[<c010d888>] (show_stack) from [<c03fab0c>] (dump_stack+0x80/0x94)
[<c03fab0c>] (dump_stack) from [<c0123548>] (__warn+0xf8/0x110)
[<c0123548>] (__warn) from [<c01235a8>] (warn_slowpath_fmt+0x48/0x50)
[<c01235a8>] (warn_slowpath_fmt) from [<c042ac90>] (check_unmap+0x7bc/0xb38)
[<c042ac90>] (check_unmap) from [<c042b25c>] (debug_dma_unmap_sg+0x118/0x148)
[<c042b25c>] (debug_dma_unmap_sg) from [<c077512c>] (dw_mci_dma_cleanup+0x7c/0xb8)
[<c077512c>] (dw_mci_dma_cleanup) from [<c0773f24>] (dw_mci_stop_dma+0x40/0x50)
[<c0773f24>] (dw_mci_stop_dma) from [<c0777d04>] (dw_mci_tasklet_func+0x130/0x3b4)
[<c0777d04>] (dw_mci_tasklet_func) from [<c0129760>] (tasklet_action+0xb4/0x150)
[<c0129760>] (tasklet_action) from [<c0101674>] (__do_softirq+0xe4/0x3cc)
[<c0101674>] (__do_softirq) from [<c0129030>] (irq_exit+0xd0/0x10c)
[<c0129030>] (irq_exit) from [<c01778a0>] (__handle_domain_irq+0x90/0xfc)
[<c01778a0>] (__handle_domain_irq) from [<c0101548>] (gic_handle_irq+0x64/0xa8)
[<c0101548>] (gic_handle_irq) from [<c010e3d4>] (__irq_svc+0x54/0x90)
Exception stack(0xc1101ef8 to 0xc1101f40)
1ee0:                                                       00000001 00000000
1f00: 00000000 c011b600 c1100000 c110753c 00000000 c11c3984 c11074d4 c1107548
1f20: 00000000 c1101f54 c1101f58 c1101f48 c010a1fc c010a200 60000013 ffffffff
[<c010e3d4>] (__irq_svc) from [<c010a200>] (arch_cpu_idle+0x48/0x4c)
[<c010a200>] (arch_cpu_idle) from [<c01669d8>] (default_idle_call+0x30/0x3c)
[<c01669d8>] (default_idle_call) from [<c0166d3c>] (cpu_startup_entry+0x358/0x3b4)
[<c0166d3c>] (cpu_startup_entry) from [<c0aa6ab8>] (rest_init+0x94/0x98)
[<c0aa6ab8>] (rest_init) from [<c1000d58>] (start_kernel+0x3a4/0x3b0)
[<c1000d58>] (start_kernel) from [<4000807c>] (0x4000807c)
---[ end trace 256f83eed365daf0 ]---

Change-Id: Idc1b46aeac92d715e368533352b2bb75d65d4bbd
Reported-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

UPSTREAM: net: stmmac: dwmac-rk: add rk3228-specific data

Add constants and callback functions for the dwmac on rk3228/rk3229 socs.
As can be seen, the base structure is the same, only registers and the
bits in them moved slightly.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git
master commit e7ffd81233334b7755050523cb7e0456ae3d2e53)

Conflicts:

Documentation/devicetree/bindings/net/rockchip-dwmac.txt
[zx: conflict with rk3366 and rk3399 that have not been sent to upstream.]

Change-Id: Ibae845ded567e11a8428f6f45510cd5443845e17
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

ARM64: dts: rk3399-evb2: remove 1.8G support for A72

Some RK3399 evb2 cannot support 1.8G for A72, maybe caused by
current limit, but remove it anyway for evb2.

Change-Id: Ibaa940696ccbdc59131c49e9a643a63863768ea2
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

spi: rockchip: set tx burst len 16, rx burst len 1.

Set ROCKCHIP_SPI_DMATDLR (rs->fifo_len - 16 - 1), which
can keep spi transferring. By the way, rx burst len must be
set 1, because it is hard to deal with the unaligned length.
Such as burst leng 16, ROCKCHIP_SPI_DMARDLR 16, when rx fifo
reaches 16, dma receive 16 bytes. But if the last bytes is less
than 16, dma will miss the bytes left in the rx fifo.

Change-Id: I846db94a87955453e617620ade32f2e68f01c01d
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

dmaengine: pl330: support transfer that doesn't align with (burst len * burst size)

Below code transfers 0x10002 bytes:
First loop 256*16*16=0x10000, burst size is 1, burst length is 16.
Then the second loop 2 bytes, burst size is 1, burst length is 1.

f0041000:        DMAMOV CCR 0xbc02f1
f0041006:        DMAMOV SAR 0xdd6c0000
f004100c:        DMAMOV DAR 0xff1d0400
f0041012:        DMALP_0 15
f0041014:        DMALP_1 255
f0041016:        DMAWFPB 12
f0041018:        DMALDA
f0041019:        DMASTPB 12
f004101b:        DMAFLUSHP 12
f004101d:        DMALPENDA_1 bjmpto_7
f004101f:        DMALPENDA_0 bjmpto_b
f0041021:        DMAMOV CCR 0x800201
f0041027:        DMALP_1 1
f0041029:        DMAWFPB 12
f004102b:        DMALDA
f004102c:        DMASTPB 12
f004102e:        DMAFLUSHP 12
f0041030:        DMALPENDA_1 bjmpto_7
f0041032:        DMASEV 0
f0041034:        DMAEND

Change-Id: I97ef33aeac8ebe18c63201cf4c1c04f5548e9a4a
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

UPSTREAM: ASoC: hdmi-codec: select CONFIG_HDMI

SND_SOC_HDMI_CODEC can be enabled without HDMI support, leading
to a link error:

In function `hdmi_codec_hw_params':
sound/soc/codecs/hdmi-codec.c:188: undefined reference to `hdmi_audio_infoframe_init'
sound/built-in.o:(.debug_addr+0x1a5c0): undefined reference to `hdmi_audio_infoframe_init'

This changes the Kconfig file to select HDMI, as the other codec using
hdmi_audio_infoframe_init already does.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git fix/hdmi
 commit 6de7df8d1b1a45a07d6ecc6b4f94179e1e68f5ec)

Change-Id: Iddf276cef778db8cb28e5ea86dec146136887056
Signed-off-by: Chris Zhong <zyw@rock-chips.com>

UPSTREAM: ASoC: hdmi-codec: Add ELD control

Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit db71336b9eec22c21cef65c90cea49130c464994)

Change-Id: Ie82a1f72c3601b64c61b2d17f5849f892010f5ef
Signed-off-by: Chris Zhong <zyw@rock-chips.com>

UPSTREAM: ASoC: hdmi-codec: Add ELD control

ALSA doesn't know about all the different compressed audio formats,
so there is no interface to let userspace enumerate the formats that
are supported by the connected sink. Exporting the raw ELD bytes to
userspace allows an application to select the appropriate audio format
depending on the current capabilities of the connected HDMI sink device.
Usually userspace then just pretends to ALSA that the data is in one of
the raw 16-bit PCM audio formats and relies on the IEC controls to tell
the sink how to interpret the data.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Jyri Sarha <jsarha@ti.com>
Tested-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 81151cfb6bfe69f1c5a52b795eb005226a322c9e)

Change-Id: I37a90865af97be1c1e21b5e677aa7d8ce58bdf23
Signed-off-by: Chris Zhong <zyw@rock-chips.com>

UPSTREAM: ASoC: hdmi-codec: Add hdmi-codec for external HDMI-encoders

The hdmi-codec is a platform device driver to be registered from
drivers of external HDMI encoders with I2S and/or spdif interface. The
driver in turn registers an ASoC codec for the HDMI encoder's audio
functionality.

The structures and definitions in the API header are mostly redundant
copies of similar structures in ASoC headers. This is on purpose to
avoid direct dependencies to ASoC structures in video side driver.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
Acked-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Acked-by: PC Liao <pc.liao@mediatek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 09184118a8abae030539469848d475adcc0e5839)

Change-Id: I4fc0651b732c2604df58cb2e0ec5f5edeecdf412
Signed-off-by: Chris Zhong <zyw@rock-chips.com>

UPSTREAM: ALSA: pcm: Allow 32 bit sample format in IEC958 channel status helper

Treat 32 bit sample width as if it was 24 bits when generating IEC958
channel status bits. On some platforms 24 sample width is problematic
and to get full 24 bit precision a 32 bit format, using only the 24
most significant bits, may have to be used.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 4a462ce084d5beb92cfc68f53f88c035c82e6b59)

Change-Id: I26461c0d8b92bfc6547f81006dacb7a7b3068782
Signed-off-by: Chris Zhong <zyw@rock-chips.com>

UPSTREAM: ALSA: pcm: add IEC958 channel status helper for hw_params

Add IEC958 channel status helper that gets the audio properties from
snd_pcm_hw_params instead of snd_pcm_runtime. This is needed to
produce the channel status bits already in audio stream configuration
phase.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 4a4436573a6669516f73bac25016683d396ed4c4)

Change-Id: Ie19500cd63fb311ec273035c336acc8c568d84db
Signed-off-by: Chris Zhong <zyw@rock-chips.com>

UPSTREAM: clocksource/drivers/rockchip: Add support for the rk3399 SoC

The only difference between the rk3399 SoC and the other ones is the control
register offset which is different.

Add a new field to store the control register address depending on the SoC
and use it instead of the <base> + <control offset>.

BUG=chrome-os-partner:54522
TEST=Tested on gru, cat /proc/interrupts |grep timer

Change-Id: I37f4d30a8b4609887b175ab7e9b1117b2ac436e4
Signed-off-by: Huang Tao <huangtao@rock-chips.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Heiko Stuebner <heiko@sntech.de>
Tested-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
(cherry picked from git.linaro.org/people/daniel.lezcano/linux.git clockevents/next
 commit d0e2b96b2f723cb2d3ca992eaa2fe643367830f8)
Reviewed-on: https://chromium-review.googlesource.com/353977
Reviewed-by: Douglas Anderson <dianders@chromium.org>

UPSTREAM: clocksource/drivers/rockchip: Add the dynamic irq flag to the timer

The rockchip timer is a broadcast timer. Add the CLOCK_EVT_FEAT_DYNIRQ flag
and set the cpumask to all possible cpus to save power by avoiding
unnecessary wakeups and IPIs.

BUG=chrome-os-partner:54522
TEST=Tested on gru, cat /proc/interrupts |grep timer

Change-Id: Ic7de570f35921a292e4687c2bcf408b37334f781
Signed-off-by: Huang Tao <huangtao@rock-chips.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Heiko Stuebner <heiko@sntech.de>
Tested-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
(cherry picked from git.linaro.org/people/daniel.lezcano/linux.git clockevents/next
 commit 11932c2ac6f8c0f20f12a38569a36f0d1b5cfd6b)
Reviewed-on: https://chromium-review.googlesource.com/353976
Reviewed-by: Douglas Anderson <dianders@chromium.org>

Revert "clocksource: rockchip: remove unnecessary clear irq before request_irq"

This reverts commit c380160aeae8b786868bd8483b9c1c9f22d15b61.

Change-Id: I435f0989976627e9892ff2bdba91cf41b8b77ef9
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

Revert "clocksource: rockchip: add dynamic irq flag to the timer"

This reverts commit fb50410985e6f6874dcfe6e3f12b4bccd5d0335b.

Change-Id: I1d04b207ae34a15688c1dc77f08525a45541e39e
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

Revert "clocksource: rockchip: add support for rk3399 SoC"

This reverts commit b7355e9f6230d28ee92de14426c36ab0b208f51a.

Change-Id: If04877735b4b99e3f1f6a691480413872a0a9562
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

video: rockchip: mipi: modify judgment condition for rk32_dsi_set_bits

Change-Id: I71a2515f871dc3d8bbcd8567565fc412c39d9a81
Signed-off-by: xubilv <xbl@rock-chips.com>

arm64: dts: rockchip: add rk3399 box 0505 board support

Add minimal DT files for the rockchip box board, based on
the rockchip rk3399 SoC.

Change-Id: I6b63e9d4e217412cc6e1a01a4cb9e0be58ff3d6f
Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>

UPSTREAM: clk: rockchip: export rk3228 MAC clocks

This patch exports related MAC clocks for dts reference.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-clk/next commit af5cf5deb074d9011209d3979096620d1dadf44a)

Change-Id: I12d60a82b08ba528b3e0ac3f45dc437514df6f8a
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclk

The sclk_macphy_50m is confusing, the sclk_mac_extclk describes
a external clock  clearly.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-clk/next commit 24449885d79d79ae22a5ee2cb749161ccb5a141e)

Change-Id: I81aaed6cb9d766d9c558eaf8659eb9943290f409
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: export rk3228 audio clocks

This patch exports related i2s/spdif clocks for dts reference.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-clk/next commit c64032c5026f55cf496adc4281b9356b713ee56f)

Change-Id: Id979feaf98be2879b23b1759bbcb5fa022b71be6
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: add clock-ids for rk3228 MAC clocks

This patch exports related MAC clocks for dts reference.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-shared/clkids commit 9ff59360b863706b50cbcd7ffad9287d67254063)

Change-Id: Ib6f5f2a0ccd19a8b71c384abddacadbd4da291bb
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: add clock-ids for rk3228 audio clocks

This patch exports related i2s/spdif clocks for dts reference.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-shared/clkids commit 5f6d71044f4d766c3636b9fd2c43e7c9d71d31af)

Change-Id: I85e535307b0fa479b50a66bc25e9c3c5132deaa0
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: include rk3288 downstream muxes into fractional dividers

During the initial conversion to the newly introduced combined fractional
dividers+muxes the rk3228 clocks were left out, so convert them now.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-clk/next commit c73f689eea9f1e1706a600a506ba89f82bd84349)

Change-Id: Iea91d23ec1fa09c4777f7ccdb016514c301f90ec
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: fix incorrect rk3228 clock registers

Due to copy and paste carelessly, RK3288_CLKxxx references are incorrect,
we need to fix them.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-clk/next commit 67de7901c441f7516d3ca967fa64533556cae4e7)

Change-Id: I3910b05343e0f8353ee277f969e4ab32ed94ad6d
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: release io resource when failing to init clk

We should call iounmap to relase reg_base since it's not going
to be used any more if failing to init clk.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-clk/next commit 1d003eb0805ac5b549e76202a1e95da33f62cb9a)

Change-Id: Ia0161885786d6504fee7e76c6620df98bb2cdb21
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: fix wrong mmc phase shift for rk3228

mmc sample shift is 0 for rk3228 refer to user manaul.
So it's broken if we enable mmc tuning for rk3228.

Fixes: 307a2e9ac ("clk: rockchip: add clock controller for rk3228")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-clk/next commit bb07698fc8d13ec74f4f5bd87b04953777ee6982)

Change-Id: I9bb7e18fe8c1cdb5661219f078f4992de7ad06bd
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: set the clock ids for RK3228 HDMI

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-clk/next from commit bdc7deec2fe86555ab0039ba52bcf35721dc1577)

Change-Id: I33e4850717853d3ea94479b087d32f114e5b1a59
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: set the clock ids for RK3228 VOP

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-clk/next from commit 0a9d4ac08ebc6bddc97228600c4d7e247d9d7a36)

Change-Id: I9e995f3e1fe35d5b3b44adec174fd58df9b90380
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: add the new clock ids for RK3228 HDMI

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-shared/clkids commit 2d2671ea4b35454b30a69744ce258489920e4d2b)

Change-Id: I670ae08d8cac91e0cf4985ca50e3f64916d527ba
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: add the new clock ids for RK3228 VOP

There are four clocks that vop module would need to operate:
    DCLK_VOP,  HCLK_VOP,  SCLK_VOP,  ACLK_VOP,

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-shared/clkids commit 31b1fed36eb56ae8bd25af42ad1625c4110615eb)

Change-Id: Iea57109b85928c4139283e366ce5d60430e8984b
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: add the tsadc clocks found on rk3228 SoCs

This patch adds the needed clocks for rk3228 tsadc.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-clk/next commit a3cb9aa4bad3392e23c48e186714a1c96c7d0d6b)

Change-Id: Ie7328cc5de2e3909360e5655acb93d4f0eff025c
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: add id of the tsadc clock found on rk3228 SoCs

This patch adds 'SCLK_TSADC' and 'PCLK_TSADC' id found on rk3228 SoCs.
That will be needed by TSADC controller.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-clk/next commit 3629e70b8c78ec7a40d5c4fd1356b9dc1937d326)

Change-Id: Ia4c926d4decc9affd63510a794d7f2553f6be3a5
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

BACKPORT: clk: rockchip: add clock controller for rk3228

Add the clock tree definition for the new rk3228 SoC.

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-clk/next commit 307a2e9ac524bbec707c0e2b47ca50adaecc23f2)

[zx:
previouslly we miss the clock driver for rk3228, it may cause
conflict with struct rockchip_clk_provider on the new CCF,
let's update them directly, therefore, there are include 4
BACKPORT CLs in gerrit:
https://10.10.10.29/#/c/20659/1
https://10.10.10.29/#/c/20661/1
https://10.10.10.29/#/c/20662/1
https://10.10.10.29/#/c/20663/1
]

Change-Id: I8d335e17340291f00f8e1643c8e893f88b06457c
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

UPSTREAM: clk: rockchip: add dt-binding header for rk3228

Add the dt-bindings header for the rk3228, that gets shared between
the clock controller and the clock references in the dts.

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-shared/clkids commit abf1296599fd679ece61a6c145cc7ee0c490e573)

Change-Id: Id164aa064046276f22dc763c746e9e85c344cd81
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

fiq debugger: add resume for debug uart

The uart power domain is off after suspend, which makes
uart registers reseted. So, when resume, uart driver gets
wrong registers value, and enters endless loop.

Change-Id: I90eb805d85cc27486e94949b9a84c4f8a12430b7
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

UPSTREAM: platform: Do not detach from PM domains on shutdown

Shutdown is carried out when the driver is still bound to the
device, so it is incorrect to detach it from a PM domain (if any)
at this point.

Change-Id: I325d018c98307fc3386273e2ca6f021ead5069b5
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reported-and-tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 2d30bb0b3889adf09b342722b2ce596c0763bc93)

drm/rockchip: enable pm_runtime after clock enable

Power domain recommand order is that:
  -> enable clock
  -> pm_runtime_get_sync
  -> pm_runtime_put
  -> disable clock

Change-Id: Ia8d5c961afe8da6407a7cca1e48696a285460686
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

ARM64: dts: rk3399: add powerdomain for vop

Change-Id: I308b22833c00b6ae6e19a53335b34bca31a92804
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

clk: rockchip: rk3399: Add support frac mode frequencies for independent VPLL

These clock rate are used for HDMI display.

Change-Id: I4742dcfe8ddedfa6b86c38ce03bcaa5c28b34c4e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

phy: rockchip-inno-usb2: support phy default parameters tunning.

This patch does not aim to upstream, just use locally.

If needed, the different SoC can register its own callback function
to tunning the default parameters of phy.

Change-Id: I19b2a4f9e0cb04b139dd64eae1c856fbe9142665
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

ARM64: dts: rk3399: android: add fiq_debugger

Change-Id: I537633e25241531ce49bad896f5a18d7f2835aa8
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

ARM64: dts: rk3399: android: enable early console only

Disable the normal console of 8250, because we use fiq_debugger
console named ttyFIQ0.

Change-Id: I107cf950d646f8d42d2f3e7a6846762a59f3eb97
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

arm64: configs: rockchip_defconfig select fiq debugger

Change-Id: I96a45e0b580430a67c89f3b7d1bb952124928791
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

fiq_debugger: fix code error in fiq_debugger_arm64.c

Change-Id: I6163602bf0190db85714c68086f61c89b7629687
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

soc: rockchip: add rk fiq debugger platform driver

Change-Id: Ibb32efc190ce49d657973133a30632c71f0d806c
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

clk: rockchip: rk3399: add 65M for PLL freq

VPLL need 65M freq for some HDMI display.

Change-Id: I4f07c97282fb48fc504b54a07838ccb0bbb0355a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

i2c: rk3x: sync with i2c-next branch

Change-Id: Id698758616934b8816f0b8be12ea45887dc0aca9
Signed-off-by: David Wu <david.wu@rock-chips.com>