When no memoperands are present, assume unaligned, volatile.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107114 91177308-0d34-0410-b5e6-96231b3b80d8

Strip resulting binaries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107112 91177308-0d34-0410-b5e6-96231b3b80d8

Reapply my if-conversion cleanup from svn r106939 with fixes.
There are 2 changes relative to the previous version of the patch:

1) For the "simple" if-conversion case, there's no need to worry about
RemoveExtraEdges not handling an unanalyzable branch.  Predicated terminators
are ignored in this context, so RemoveExtraEdges does the right thing.
This might break someday if we ever treat indirect branches (BRIND) as
predicable, but for now, I just removed this part of the patch, because
in the case where we do not add an unconditional branch, we rely on keeping
the fall-through edge to CvtBBI (which is empty after this transformation).

The change relative to the previous patch is:

@@ -1036,10 +1036,6 @@
     IterIfcvt = false;
   }

-  // RemoveExtraEdges won't work if the block has an unanalyzable branch,
-  // which is typically the case for IfConvertSimple, so explicitly remove
-  // CvtBBI as a successor.
-  BBI.BB->removeSuccessor(CvtBBI->BB);
   RemoveExtraEdges(BBI);

   // Update block info. BB can be iteratively if-converted.

2) My patch exposed a bug in the code for merging the tail of a "diamond",
which had previously never been exercised.  The code was simply checking that
the tail had a single predecessor, but there was a case in
MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was
neither edge of the diamond.  I added the following change to check for
that:

@@ -1276,7 +1276,18 @@
   // tail, add a unconditional branch to it.
   if (TailBB) {
     BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
-    if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
+    bool CanMergeTail = !TailBBI.HasFallThrough;
+    // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
+    // check if there are any other predecessors besides those.
+    unsigned NumPreds = TailBB->pred_size();
+    if (NumPreds > 1)
+      CanMergeTail = false;
+    else if (NumPreds == 1 && CanMergeTail) {
+      MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
+      if (*PI != BBI1->BB && *PI != BBI2->BB)
+        CanMergeTail = false;
+    }
+    if (CanMergeTail) {
       MergeBlocks(BBI, TailBBI);
       TailBBI.IsDone = true;
     } else {

With these fixes, I was able to run all the SingleSource and MultiSource
tests successfully.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107110 91177308-0d34-0410-b5e6-96231b3b80d8

Add an Intraprocedural form of BasicAliasAnalysis, which aims to
properly handles instructions and arguments defined in different
functions, or across recursive function iterations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107109 91177308-0d34-0410-b5e6-96231b3b80d8

Described the missing AVX forms of SSE2 convert instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107108 91177308-0d34-0410-b5e6-96231b3b80d8

Fix Thumb encoding of VMOV (scalar to ARM core register).  The encoding is
the same as ARM except that the condition code field is always set to ARMCC::AL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107107 91177308-0d34-0410-b5e6-96231b3b80d8

The comment string does not match for all targets. PowerPC uses ;.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107103 91177308-0d34-0410-b5e6-96231b3b80d8

Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so they
can't be changed arbitrarily by the DAGCombiner without checking if it is
running after legalization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107097 91177308-0d34-0410-b5e6-96231b3b80d8

Refix XTARGET.  Previous attempt matches on powerpc-apple-darwin,
although I don't see why.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107090 91177308-0d34-0410-b5e6-96231b3b80d8

Attempt to fix XTARGET.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107088 91177308-0d34-0410-b5e6-96231b3b80d8

Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead
of the Subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107086 91177308-0d34-0410-b5e6-96231b3b80d8

Use DW_FORM_addr for DW_AT_entry_pc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107085 91177308-0d34-0410-b5e6-96231b3b80d8

Add a blurb about -scev-aa.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107080 91177308-0d34-0410-b5e6-96231b3b80d8

In asm's, output operands with matching input constraints
have to be registers, per gcc documentation.  This affects
the logic for determining what "g" should lower to.  PR 7393.
A couple of existing testcases are affected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107079 91177308-0d34-0410-b5e6-96231b3b80d8

Added the darwin .secure_log_unique and .secure_log_reset directives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107077 91177308-0d34-0410-b5e6-96231b3b80d8

Constant fold x == undef to undef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107074 91177308-0d34-0410-b5e6-96231b3b80d8

tidy up style. no functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107073 91177308-0d34-0410-b5e6-96231b3b80d8

Fix Value::stripPointerCasts and BasicAA to avoid trouble on
code in unreachable blocks, which have have use-def cycles.
This fixes PR7514.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107071 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor encoding function for NEON 1-register with modified immediate format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107070 91177308-0d34-0410-b5e6-96231b3b80d8

Support Thumb mode encoding of NEON instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107068 91177308-0d34-0410-b5e6-96231b3b80d8

Reduce indentation via early exit. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107067 91177308-0d34-0410-b5e6-96231b3b80d8

Include inlined function in list of processed subprograms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107065 91177308-0d34-0410-b5e6-96231b3b80d8

new, no longer brain-dead, r106907

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107060 91177308-0d34-0410-b5e6-96231b3b80d8

Remove this weak test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107059 91177308-0d34-0410-b5e6-96231b3b80d8

Testcase for llvm-gcc fix 107051.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107052 91177308-0d34-0410-b5e6-96231b3b80d8

Don't write temporary files in test directory

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107049 91177308-0d34-0410-b5e6-96231b3b80d8

After physreg coalescing, physical registers might not have live ranges where
you would expect.

Don't assert on that case, just give up.

This fixes PR7513.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107046 91177308-0d34-0410-b5e6-96231b3b80d8

Add a triple so test runs on Linux as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107045 91177308-0d34-0410-b5e6-96231b3b80d8

Add more special treatment for inline asm in RegAllocFast.

When an instruction has tied operands and physreg defines, we must take extra
care that the tied operands conflict with neither physreg defs nor uses.

The special treatment is given to inline asm and instructions with tied operands
/ early clobbers and physreg defines.

This fixes PR7509.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107043 91177308-0d34-0410-b5e6-96231b3b80d8

Fix thinko.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107042 91177308-0d34-0410-b5e6-96231b3b80d8

Pull in the libCrashReporterClient.a information with a warning comment.

Remove library check and regenerate configure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107028 91177308-0d34-0410-b5e6-96231b3b80d8

Preserve deleted function's local variables' debug info.
Radar 8122864.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107027 91177308-0d34-0410-b5e6-96231b3b80d8

Make this test darwin specific.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107025 91177308-0d34-0410-b5e6-96231b3b80d8

use ArgOperand API

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107017 91177308-0d34-0410-b5e6-96231b3b80d8

use ArgOperand API

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107016 91177308-0d34-0410-b5e6-96231b3b80d8

employ CallInst::ArgOffset (for now)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107015 91177308-0d34-0410-b5e6-96231b3b80d8

simplify: we have solid argument iterator range

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107014 91177308-0d34-0410-b5e6-96231b3b80d8

Generalize AAEval so that it can be used both per-function and
interprocedurally. Note that as of this writing, existing alias
analysis passes are not prepared to be used interprocedurally.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107013 91177308-0d34-0410-b5e6-96231b3b80d8

Fix this build message so that it displays the correct library
name, specifically the "lib" prefix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107011 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r106907, "make sure to handle dbg_value instructions in the middle of the
block, not...", it caused a bunch of nightly test regressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107009 91177308-0d34-0410-b5e6-96231b3b80d8

use setArgOperand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107004 91177308-0d34-0410-b5e6-96231b3b80d8

use CallInst::ArgOffset

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107003 91177308-0d34-0410-b5e6-96231b3b80d8

use ArgOperand API and CallInst::ArgOffset

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107002 91177308-0d34-0410-b5e6-96231b3b80d8

extend ArgOperand interface: setArgOperand
(in both CallInst and InvokeInst)

also add a (short-lived) constant to CallInst, that names
the operand index of the first call argument. This is
strictly transitional and should not be used for new code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107001 91177308-0d34-0410-b5e6-96231b3b80d8

use cached value

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107000 91177308-0d34-0410-b5e6-96231b3b80d8

Remove dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106990 91177308-0d34-0410-b5e6-96231b3b80d8

Use named MDNode, llvm.dbg.sp, to collect subprogram info. This will be used to emit  local variable's debug info of deleted functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106989 91177308-0d34-0410-b5e6-96231b3b80d8

minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106988 91177308-0d34-0410-b5e6-96231b3b80d8

Do not forget last element, function, while creating Subprogram definition MDNode from subprogram declare MDNode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106985 91177308-0d34-0410-b5e6-96231b3b80d8

minor cleanup to SROA: when lowering type unsafe accesses to
large integers, the first inserted value would always create
an 'or X, 0'.  Even though this is trivially zapped by
instcombine, don't bother creating this pointless instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106979 91177308-0d34-0410-b5e6-96231b3b80d8

add some named accessors for StoreInst

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106969 91177308-0d34-0410-b5e6-96231b3b80d8

fit in 80 cols

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106968 91177308-0d34-0410-b5e6-96231b3b80d8

this test is failing nondeterministically and blaming me, just disable
it for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106960 91177308-0d34-0410-b5e6-96231b3b80d8

Fix test weirdness.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106959 91177308-0d34-0410-b5e6-96231b3b80d8

Fix some tests that didn't test anything.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106954 91177308-0d34-0410-b5e6-96231b3b80d8

Partial specialization test should not depend on the order of specialization operations or the names assigned to the specialized functions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106953 91177308-0d34-0410-b5e6-96231b3b80d8

When splitting a VAARG, remember its alignment.
This produces terrible but correct code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106952 91177308-0d34-0410-b5e6-96231b3b80d8

Revert my if-conversion cleanup since it caused a bunch of nightly test
regressions.

--- Reverse-merging r106939 into '.':
U    test/CodeGen/Thumb2/thumb2-ifcvt3.ll
U    lib/CodeGen/IfConversion.cpp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106951 91177308-0d34-0410-b5e6-96231b3b80d8

Fix PR7328: when turning a tail recursion into a loop, need to preserve
the returned value after the tail call if it differs from other return
values.  The optimal thing to do would be to introduce a phi node for
the return value, but for the moment just fix the miscompile.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106947 91177308-0d34-0410-b5e6-96231b3b80d8

use ArgOperand API

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106946 91177308-0d34-0410-b5e6-96231b3b80d8

use ArgOperand API

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106945 91177308-0d34-0410-b5e6-96231b3b80d8

use ArgOperand API

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106944 91177308-0d34-0410-b5e6-96231b3b80d8

VNInfos don't need to be destructed anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106943 91177308-0d34-0410-b5e6-96231b3b80d8

resort to ArgOperand API

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106942 91177308-0d34-0410-b5e6-96231b3b80d8

Remove bogus test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106941 91177308-0d34-0410-b5e6-96231b3b80d8

Followup to r106770: actually generate SXTB and SXTH for sign-extensions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106940 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up some problems with extra CFG edges being introduced during
if-conversion.  The RemoveExtraEdges function doesn't work for blocks that
end with unanalyzable branches, so in those cases, the "extra" edges must
be explicitly removed.  The CopyAndPredicateBlock and MergeBlocks methods
can also avoid copying successor edges due to branches that have already
been removed.  The latter case is especially helpful when MergeBlocks is
called for handling "diamond" if-conversions, where otherwise you can end
up with some weird intermediate states in the CFG.  Unfortunately I've
been unable to find cases where this cleanup actually makes a significant
difference in the code.  There is one test where we manage to remove an
empty block at the end of a function.  Radar 6911268.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106939 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for encoding NEON VMOV (from scalar to core register) instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106938 91177308-0d34-0410-b5e6-96231b3b80d8

It's now possible to run code placement pass for ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106935 91177308-0d34-0410-b5e6-96231b3b80d8

When creating X86 MUL8 and DIV8 instructions, make sure we don't produce
CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast
register allocator.

Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit).

This fixes PR7312.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106934 91177308-0d34-0410-b5e6-96231b3b80d8

Renumber NEON instruction formats to be consecutive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106927 91177308-0d34-0410-b5e6-96231b3b80d8

Rename ARM instruction formats NEONGetLnFrm, NEONSetLnFrm and NEONDupFrm to
"N..." instead of "NEON..." for consistency with the other NEON format names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106921 91177308-0d34-0410-b5e6-96231b3b80d8

Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106917 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.
Renumber MiscFrm to 25.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106916 91177308-0d34-0410-b5e6-96231b3b80d8

Reapply r106896:
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106912 91177308-0d34-0410-b5e6-96231b3b80d8

Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This was
introduced in r106343, but only showed up recently (with a particular compiler &
linker combination) because of the particular check, and because we have no
builtin checking for dereferencing the end of an array, which is truly
unfortunate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106908 91177308-0d34-0410-b5e6-96231b3b80d8

make sure to handle dbg_value instructions in the middle of the block, not
just at the head, when doing diamond if-conversion. rdar://7797940

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106907 91177308-0d34-0410-b5e6-96231b3b80d8

revert this now, it's using avx instead of sse :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106906 91177308-0d34-0410-b5e6-96231b3b80d8

Don't track kills in VNInfo. Use interval ends instead.

The VNInfo.kills vector was almost unused except for all the code keeping it
updated. The few places using it were easily rewritten to check for interval
ends instead.

The two new methods LiveInterval::killedAt and killedInRange are replacements.

This brings us down to 3 independent data structures tracking kills.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106905 91177308-0d34-0410-b5e6-96231b3b80d8

Change if-conversion block size limit checks to add some flexibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106901 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for encoding 3-register NEON instructions, and fix
emitNEON2RegInstruction's handling of 2-address operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106900 91177308-0d34-0410-b5e6-96231b3b80d8

In GenerateReassociations, don't bother thinking about individual
SCEVUnknown values which are loop-variant, as LSR can't do anything
interesting with these values in any case. This fixes very slow compile
times on loops which have large numbers of such values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106897 91177308-0d34-0410-b5e6-96231b3b80d8

Add several AVX MOV flavors
Support VEX encoding for MRMDestReg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106896 91177308-0d34-0410-b5e6-96231b3b80d8

Collect debug info for optimized variables of inlined functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106895 91177308-0d34-0410-b5e6-96231b3b80d8

80 column and typo fix

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106894 91177308-0d34-0410-b5e6-96231b3b80d8

The hasMemory argument is irrelevant to how the argument
for an "i" constraint should get lowered; PR 6309.  While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for encoding 2-register NEON instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106891 91177308-0d34-0410-b5e6-96231b3b80d8

pcmpeqd and friends are Commutable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106886 91177308-0d34-0410-b5e6-96231b3b80d8

80-column and trailing whitespace cleanup

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106885 91177308-0d34-0410-b5e6-96231b3b80d8

Fix indentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106881 91177308-0d34-0410-b5e6-96231b3b80d8

- Reapply r106066 now that the bzip2 build regression has been fixed.
- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106880 91177308-0d34-0410-b5e6-96231b3b80d8

We should remove the live range from the destination register only if *all* defs
are dead, not just the def of this register. I.e., a register could be dead, but
it's subreg isn't.

Testcase to follow with a subsequent patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106878 91177308-0d34-0410-b5e6-96231b3b80d8

Move the last piece of SSE2 convert instructions to the Convert Instructions section

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106877 91177308-0d34-0410-b5e6-96231b3b80d8

More SSE refactoring, this time with different types of MOVs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106876 91177308-0d34-0410-b5e6-96231b3b80d8

Eliminate a redundant FoldingSet lookup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106872 91177308-0d34-0410-b5e6-96231b3b80d8

IT instructions are considered to be scheduling hazards, but are scheduled
with the following instructions. This is done via trickery by considering the
instruction preceding the IT to be the hazard. Care must be taken to ensure
it's the first non-debug instruction, or the presence of debug info will
affect codegen.

Part of the continuing work for rdar://7797940, making ARM code-gen unaffected
by the presence of debug information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106871 91177308-0d34-0410-b5e6-96231b3b80d8

Refactoring of more SSE conversion instructions. Also add some AVX instrinsics Int_V... placeholders

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106867 91177308-0d34-0410-b5e6-96231b3b80d8

Cosmetic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106865 91177308-0d34-0410-b5e6-96231b3b80d8

XFAIL this test on powerpc for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106862 91177308-0d34-0410-b5e6-96231b3b80d8

Fix LLVM CMake PACKAGE_VERSION variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106861 91177308-0d34-0410-b5e6-96231b3b80d8