Jakob Stoklund Olesen [Wed, 20 Apr 2011 18:19:48 +0000 (18:19 +0000)]
Prefer cheap registers for busy live ranges.
On the x86-64 and thumb2 targets, some registers are more expensive to encode
than others in the same register class.
Add a CostPerUse field to the TableGen register description, and make it
available from TRI->getCostPerUse. This represents the cost of a REX prefix or a
32-bit instruction encoding required by choosing a high register.
Teach the greedy register allocator to prefer cheap registers for busy live
ranges (as indicated by spill weight).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864
91177308-0d34-0410-b5e6-
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Stuart Hastings [Wed, 20 Apr 2011 18:09:26 +0000 (18:09 +0000)]
Excise unintended hunk in 129858. <rdar://problem/
7662569>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129862
91177308-0d34-0410-b5e6-
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Stuart Hastings [Wed, 20 Apr 2011 16:47:52 +0000 (16:47 +0000)]
ARM byval support. Will be enabled by another patch to the FE. <rdar://problem/
7662569>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129858
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Wed, 20 Apr 2011 15:44:33 +0000 (15:44 +0000)]
sys/Host: Change getHostTriple() to return the full Darwin version on OS X.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129852
91177308-0d34-0410-b5e6-
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Justin Holewinski [Wed, 20 Apr 2011 15:37:17 +0000 (15:37 +0000)]
PTX: Add intrinsics to list of built-in intrinsics, which allows them to be
used by Clang. To help Clang integration, the PTX target has been split
into two targets: ptx32 and ptx64, depending on the desired pointer size.
- Add GCCBuiltin class to all intrinsics
- Split PTX target into ptx32 and ptx64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129851
91177308-0d34-0410-b5e6-
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Rafael Espindola [Wed, 20 Apr 2011 14:01:45 +0000 (14:01 +0000)]
Behave like gnu as when a relocation crosses sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129850
91177308-0d34-0410-b5e6-
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Che-Liang Chiou [Wed, 20 Apr 2011 09:28:55 +0000 (09:28 +0000)]
ptx: add integer div and rem instruction
Patched by Dan Bailey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129848
91177308-0d34-0410-b5e6-
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Che-Liang Chiou [Wed, 20 Apr 2011 09:28:20 +0000 (09:28 +0000)]
ptx: add floating-point comparison to setp
Patched by Dan Bailey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129847
91177308-0d34-0410-b5e6-
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Che-Liang Chiou [Wed, 20 Apr 2011 09:27:19 +0000 (09:27 +0000)]
ptx: fix parameter ordering
Patched by Dan Bailey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129846
91177308-0d34-0410-b5e6-
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Nick Lewycky [Wed, 20 Apr 2011 03:19:42 +0000 (03:19 +0000)]
This should always be signed chars, so use int8_t. This fixes a miscompile when
llvm is built with unsigned chars where an immediate such as 0xff would be zero
extended to 64-bits, turning "cmp $0xff,%eax" into
"cmp $0xffffffffffffffff,%eax".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129845
91177308-0d34-0410-b5e6-
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Rafael Espindola [Wed, 20 Apr 2011 03:08:09 +0000 (03:08 +0000)]
Remove unused arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129844
91177308-0d34-0410-b5e6-
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Eric Christopher [Wed, 20 Apr 2011 01:19:45 +0000 (01:19 +0000)]
Rewrite the expander for umulo/smulo to remember to sign extend the input
manually and pass all (now) 4 arguments to the mul libcall. Add a new
ExpandLibCall for just this (copied gratuitously from type legalization).
Fixes rdar://
9292577
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129842
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Wed, 20 Apr 2011 00:47:19 +0000 (00:47 +0000)]
llc: Fix a refacto, .loc support didn't work before 10.6.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129841
91177308-0d34-0410-b5e6-
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Sean Callanan [Wed, 20 Apr 2011 00:43:34 +0000 (00:43 +0000)]
Made the MC disassembler check before accessing
MCInst operands for ARM. This allows it to be
more tolerant of malformed MCInsts or incorrect
instruction metadata.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129840
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Wed, 20 Apr 2011 00:14:25 +0000 (00:14 +0000)]
ADT/Triple: Renambe isOSX... methods to isMacOSX for consistency with the OS
triple component.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129838
91177308-0d34-0410-b5e6-
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Johnny Chen [Tue, 19 Apr 2011 23:58:52 +0000 (23:58 +0000)]
Fix typo in the comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129837
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Tue, 19 Apr 2011 23:55:20 +0000 (23:55 +0000)]
ADT/Triple: Drop support for -osx style triples, we are going with -macosx
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129836
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Tue, 19 Apr 2011 23:34:12 +0000 (23:34 +0000)]
ADT/Triple: Add support for Triple::MacOSX per feedback from Chris, will remove
Triple::OSX once Clang has moved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129833
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Tue, 19 Apr 2011 21:14:45 +0000 (21:14 +0000)]
ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows()
predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129816
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Tue, 19 Apr 2011 21:12:05 +0000 (21:12 +0000)]
ADT/Triple: Add isOSDarwin() and isOSWindows() helper functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129815
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Tue, 19 Apr 2011 21:07:03 +0000 (21:07 +0000)]
ADT/Triple: Fix Triple::getArchNameForAssembler to support OSX and iOS
enumeration values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129814
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Tue, 19 Apr 2011 21:04:12 +0000 (21:04 +0000)]
Target/X86: Eliminate uses of getDarwinVers().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129813
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Tue, 19 Apr 2011 21:01:47 +0000 (21:01 +0000)]
Target/X86: Add getTargetTriple() accessor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129812
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Tue, 19 Apr 2011 20:59:24 +0000 (20:59 +0000)]
Target/PPC: Kill off DarwinVers, which is now dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129811
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Tue, 19 Apr 2011 20:57:03 +0000 (20:57 +0000)]
Target/PPC: Eliminate a use of getDarwinVers().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129810
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Tue, 19 Apr 2011 20:54:28 +0000 (20:54 +0000)]
Target/PPC: Add a TargetTriple field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129809
91177308-0d34-0410-b5e6-
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Chris Lattner [Tue, 19 Apr 2011 20:47:57 +0000 (20:47 +0000)]
add a helper method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129806
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Tue, 19 Apr 2011 20:46:13 +0000 (20:46 +0000)]
llc: Eliminate a use of getDarwinMajorNumber().
- As before, there is a minor semantic change here (evidenced by the test
change) for Darwin triples that have no version component. I debated changing
the default behavior of isOSVersionLT, but decided it made more sense for
triples to be explicit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129805
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Tue, 19 Apr 2011 20:44:08 +0000 (20:44 +0000)]
Target: Eliminate a use of getDarwinMajorNumber().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129803
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Tue, 19 Apr 2011 20:32:39 +0000 (20:32 +0000)]
CodeGen: Eliminate a use of getDarwinMajorNumber().
- There is a minor semantic change here (evidenced by the test change) for
Darwin triples that have no version component. I debated changing the default
behavior of isOSVersionLT, but decided it made more sense for triples to be
explicit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129802
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Tue, 19 Apr 2011 20:30:10 +0000 (20:30 +0000)]
ADT/Triple: Add helper function for OS X version checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129801
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Tue, 19 Apr 2011 20:30:07 +0000 (20:30 +0000)]
ADT/Triple: Add isOSVersionLT helper function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129800
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Tue, 19 Apr 2011 20:24:34 +0000 (20:24 +0000)]
ADT/Triple: Generalize and simplify getDarwinNumber to just be getOSVersion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129799
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Tue, 19 Apr 2011 20:19:27 +0000 (20:19 +0000)]
ADT/Triple: Add support for more explicit "osx" and "ios" OS names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129798
91177308-0d34-0410-b5e6-
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Stuart Hastings [Tue, 19 Apr 2011 20:09:38 +0000 (20:09 +0000)]
Delete unnecessary variable. <rdar://problem/
7662569>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129796
91177308-0d34-0410-b5e6-
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Eric Christopher [Tue, 19 Apr 2011 18:49:19 +0000 (18:49 +0000)]
Remove some duplicate op action entries and reorganize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129781
91177308-0d34-0410-b5e6-
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Bob Wilson [Tue, 19 Apr 2011 18:11:57 +0000 (18:11 +0000)]
This patch combines several changes from Evan Cheng for rdar://
8659675.
Making use of VFP / NEON floating point multiply-accumulate / subtraction is
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.
Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.
A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.
Enable these fp vmlx codegen changes for Cortex-A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129775
91177308-0d34-0410-b5e6-
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Bob Wilson [Tue, 19 Apr 2011 18:11:52 +0000 (18:11 +0000)]
Add -mcpu=cortex-a9-mp. It's cortex-a9 with MP extension. rdar://
8648637.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129774
91177308-0d34-0410-b5e6-
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Bob Wilson [Tue, 19 Apr 2011 18:11:49 +0000 (18:11 +0000)]
Avoid some 's' 16-bit instruction which partially update CPSR
(and add false dependency) when it isn't dependent on last CPSR defining
instruction. rdar://
8928208
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129773
91177308-0d34-0410-b5e6-
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Bob Wilson [Tue, 19 Apr 2011 18:11:45 +0000 (18:11 +0000)]
Avoid write-after-write issue hazards for Cortex-A9.
Add a avoidWriteAfterWrite() target hook to identify register classes that
suffer from write-after-write hazards. For those register classes, try to avoid
writing the same register in two consecutive instructions.
This is currently disabled by default. We should not spill to avoid hazards!
The command line flag -avoid-waw-hazard can be used to enable waw avoidance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129772
91177308-0d34-0410-b5e6-
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Bob Wilson [Tue, 19 Apr 2011 18:11:38 +0000 (18:11 +0000)]
Some single-precision VFP instructions can execute in either the VPF or Neon
pipelines, at least on Cortex-A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129771
91177308-0d34-0410-b5e6-
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Bob Wilson [Tue, 19 Apr 2011 18:11:36 +0000 (18:11 +0000)]
Improvements for the Cortex-A9 scheduling itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129770
91177308-0d34-0410-b5e6-
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Eli Friedman [Tue, 19 Apr 2011 17:22:22 +0000 (17:22 +0000)]
Add support for FastISel'ing varargs calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129765
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Tue, 19 Apr 2011 17:17:58 +0000 (17:17 +0000)]
Force the greedy register allocator to be linked alongside linear scan.
This means that the new register allocator can be used with 'clang -mllvm -regalloc=greedy'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129764
91177308-0d34-0410-b5e6-
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Eli Friedman [Tue, 19 Apr 2011 17:01:08 +0000 (17:01 +0000)]
SelectBasicBlock is rather slow even when it doesn't do anything; skip the
unnecessary work where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129763
91177308-0d34-0410-b5e6-
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Stuart Hastings [Tue, 19 Apr 2011 16:16:58 +0000 (16:16 +0000)]
Support nested CALLSEQ_BEGIN/END; necessary for ARM byval support. <rdar://problem/
7662569>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129761
91177308-0d34-0410-b5e6-
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Jay Foad [Tue, 19 Apr 2011 15:23:29 +0000 (15:23 +0000)]
Trivial simplification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129759
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Tue, 19 Apr 2011 06:14:45 +0000 (06:14 +0000)]
Tighten test case a bit.
Ideally, we would match an S-register to its containing D-register, but that
requires arithmetic (divide by 2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129756
91177308-0d34-0410-b5e6-
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Chris Lattner [Tue, 19 Apr 2011 05:52:03 +0000 (05:52 +0000)]
Implement support for x86 fastisel of small fixed-sized memcpys, which are generated
en-mass for C++ PODs. On my c++ test file, this cuts the fast isel rejects by 10x
and shrinks the generated .s file by 5%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129755
91177308-0d34-0410-b5e6-
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Chris Lattner [Tue, 19 Apr 2011 05:15:59 +0000 (05:15 +0000)]
tidy up
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129753
91177308-0d34-0410-b5e6-
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Chris Lattner [Tue, 19 Apr 2011 05:09:50 +0000 (05:09 +0000)]
Implement support for fast isel of calls of i1 arguments, even though they are illegal,
when they are a truncate from something else. This eliminates fully half of all the
fastisel rejections on a test c++ file I'm working with, which should make a substantial
improvement for -O0 compile of c++ code.
This fixed rdar://
9297003 - fast isel bails out on all functions taking bools
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129752
91177308-0d34-0410-b5e6-
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Chris Lattner [Tue, 19 Apr 2011 04:42:38 +0000 (04:42 +0000)]
Handle i1/i8/i16 constant integer arguments to calls by prepromoting them.
Before we would bail out on i1 arguments all together, now we just bail on
non-constant ones. Also, we used to emit extraneous code. e.g. test12 was:
movb $0, %al
movzbl %al, %edi
callq _test12
and test13 was:
movb $0, %al
xorl %edi, %edi
movb %al, 7(%rsp)
callq _test13f
Now we get:
movl $0, %edi
callq _test12
and:
movl $0, %edi
callq _test13f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129751
91177308-0d34-0410-b5e6-
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Chris Lattner [Tue, 19 Apr 2011 04:26:32 +0000 (04:26 +0000)]
be layout aware, to produce:
testb $1, %al
je LBB0_2
## BB#1: ## %if.then
movb $0, %al
instead of:
testb $1, %al
jne LBB0_1
jmp LBB0_2
LBB0_1: ## %if.then
movb $0, %al
how 'bout that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129749
91177308-0d34-0410-b5e6-
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Chris Lattner [Tue, 19 Apr 2011 04:22:17 +0000 (04:22 +0000)]
fix rdar://
9297006 - fast isel bails out on trunc to i1 -> bools cry,
a common cause of fast isel rejects on c++ code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129748
91177308-0d34-0410-b5e6-
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Evan Cheng [Tue, 19 Apr 2011 01:21:49 +0000 (01:21 +0000)]
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That
is, it assumes addresses are 64-bit aligned (which should be the more common
case). If the alignment is found not to be aligned, then getOperandLatency()
would adjust the operand latency computation by one to compensate for it.
rdar://
9294833
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129742
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Tue, 19 Apr 2011 00:14:43 +0000 (00:14 +0000)]
Make tests register allocation independent again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129739
91177308-0d34-0410-b5e6-
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Evan Cheng [Tue, 19 Apr 2011 00:04:03 +0000 (00:04 +0000)]
Do not lose mem_operands while lowering VLD / VST intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129738
91177308-0d34-0410-b5e6-
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Francois Pichet [Tue, 19 Apr 2011 00:03:17 +0000 (00:03 +0000)]
Disable warning C4181: "qualifier applied to reference type; ignored"
This was causing a flooding of warnings with MSVC 2008. This warning was removed in MSVC 2010.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129737
91177308-0d34-0410-b5e6-
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NAKAMURA Takumi [Mon, 18 Apr 2011 23:59:50 +0000 (23:59 +0000)]
docs: Use <Hn> as Heading elements instead of <DIV class="doc_foo">.
H1 ... doc_title
H2 ... doc_section
H3 ... doc_subsection
H4 ... doc_subsubsection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129736
91177308-0d34-0410-b5e6-
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Devang Patel [Mon, 18 Apr 2011 23:51:03 +0000 (23:51 +0000)]
Use ArrayRef variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129735
91177308-0d34-0410-b5e6-
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Ted Kremenek [Mon, 18 Apr 2011 22:44:46 +0000 (22:44 +0000)]
Add BumpPtrAllocator::getTotalMemory() to allow clients to query how much memory a BumpPtrAllocator allocated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129727
91177308-0d34-0410-b5e6-
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Devang Patel [Mon, 18 Apr 2011 22:27:20 +0000 (22:27 +0000)]
Remove test to check line numbers. There are other numerous tests in our test harness to check line number information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129725
91177308-0d34-0410-b5e6-
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Jim Grosbach [Mon, 18 Apr 2011 21:35:54 +0000 (21:35 +0000)]
Trim a few unneeded includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129723
91177308-0d34-0410-b5e6-
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Eric Christopher [Mon, 18 Apr 2011 21:28:11 +0000 (21:28 +0000)]
Invert the meaning of printAliasInstr's return value. It now returns
true on success and false on failure. Update callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129722
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Eli Friedman [Mon, 18 Apr 2011 21:21:37 +0000 (21:21 +0000)]
Simplify declarations slightly by using typedefs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129720
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Eli Friedman [Mon, 18 Apr 2011 20:54:46 +0000 (20:54 +0000)]
malloc elimination: it's a bad idea to use raw_svector_ostream on a
small heap-allocated SmallString because it unconditionally forces a malloc.
(Revised version of r129688, with the necessary flush() call.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129716
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Devang Patel [Mon, 18 Apr 2011 20:26:49 +0000 (20:26 +0000)]
Reduce clutter in asm output. Do not emit source location as comment for each instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129715
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Jakob Stoklund Olesen [Mon, 18 Apr 2011 20:23:27 +0000 (20:23 +0000)]
Handle spilling around an instruction that has an early-clobber re-definition of
the spilled register.
This is quite common on ARM now that some stores have early-clobber defines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129714
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Sean Callanan [Mon, 18 Apr 2011 20:20:44 +0000 (20:20 +0000)]
Small fix to the ARM AsmParser to ensure that a
superclass variable is instantiated properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129713
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Eric Christopher [Mon, 18 Apr 2011 19:26:25 +0000 (19:26 +0000)]
Fix a bug where we were counting the alias sets as completely used
registers for fast allocation a different way. This has us updating
used registers only when we're using that exact register.
Fixes rdar://
9207598
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129711
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Chandler Carruth [Mon, 18 Apr 2011 18:49:44 +0000 (18:49 +0000)]
Mark some functions as used which are used within debug-only code. This
silences Clang's -Wunused-function when building in release mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129709
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Owen Anderson [Mon, 18 Apr 2011 18:42:26 +0000 (18:42 +0000)]
Enhance the fixed-length disassembler to support the callbacks necessary for symbolic disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129708
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Anders Carlsson [Mon, 18 Apr 2011 14:02:06 +0000 (14:02 +0000)]
Make the empty StructType::get overload use an empty ArrayRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129696
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Chris Lattner [Mon, 18 Apr 2011 07:00:40 +0000 (07:00 +0000)]
while we're at it, handle 'sdiv exact' of a power of 2 also,
this fixes a few rejects on c++ iterator loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129694
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Chris Lattner [Mon, 18 Apr 2011 06:55:51 +0000 (06:55 +0000)]
fix rdar://
9297011 - udiv by power of two causing fast-isel rejects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129693
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Chris Lattner [Mon, 18 Apr 2011 06:36:55 +0000 (06:36 +0000)]
Add a new bit that ImmLeaf's can opt into, which allows them to duck out of
the generated FastISel. X86 doesn't need to generate code to match ADD16ri8
since ADD16ri will do just fine. This is a small codesize win in the generated
instruction selector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129692
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Chris Lattner [Mon, 18 Apr 2011 06:22:33 +0000 (06:22 +0000)]
Implement major new fastisel functionality: the matcher can now handle immediates with
value constraints on them (when defined as ImmLeaf's). This is particularly important
for X86-64, where almost all reg/imm instructions take a i64immSExt32 immediate operand,
which has a value constraint. Before this patch we ended up iseling the examples into
such amazing code as:
movabsq $7, %rax
imulq %rax, %rdi
movq %rdi, %rax
ret
now we produce:
imulq $7, %rdi, %rax
ret
This dramatically shrinks the generated code at -O0 on x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129691
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Chris Lattner [Mon, 18 Apr 2011 06:15:35 +0000 (06:15 +0000)]
relax this test to just check that the lock prefix is encoded properly,
and to not rely on the register allocator's arbitrary operand choices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129690
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Eli Friedman [Mon, 18 Apr 2011 05:54:54 +0000 (05:54 +0000)]
Revert r129688; it's breaking buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129689
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Eli Friedman [Mon, 18 Apr 2011 05:38:58 +0000 (05:38 +0000)]
More malloc elimination: it's a bad idea to use raw_svector_ostream on a
small heap-allocated SmallString because it unconditionally forces a malloc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129688
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Eli Friedman [Mon, 18 Apr 2011 05:02:31 +0000 (05:02 +0000)]
Make the StringMaps attached to MCContext use the MCContext's allocator;
reduces the number of calls to malloc().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129687
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Anders Carlsson [Mon, 18 Apr 2011 04:55:06 +0000 (04:55 +0000)]
Use an empty ArrayRef instead of an empty std::vector for the Function::get overload that takes no parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129686
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NAKAMURA Takumi [Mon, 18 Apr 2011 01:17:51 +0000 (01:17 +0000)]
docs: Redefine Heading elements as below;
H1 ... Title (and might be Chapter in future)
H2 ... Section
H3 ... Subsection
H4 ... Sub-subsection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129683
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Chris Lattner [Sun, 17 Apr 2011 23:29:05 +0000 (23:29 +0000)]
introduce a new OpKind abstraction which wraps up operand flavors in a tidy little wrapper.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129680
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Chris Lattner [Sun, 17 Apr 2011 22:24:13 +0000 (22:24 +0000)]
change OperandsSignature to use SmallVector<char> instead of std::vector<string>
since the strings are always exactly one character, and there are usually only 2-3 operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129678
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Chris Lattner [Sun, 17 Apr 2011 22:17:27 +0000 (22:17 +0000)]
since the VT is fixed for a ImmLeaf, there is no reason to expose it to the matching code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129677
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Chris Lattner [Sun, 17 Apr 2011 22:12:55 +0000 (22:12 +0000)]
switch the rest of the x86 immediate patterns over to ImmLeaf,
simplifying them and exposing more information to tblgen. It would be nice
if other target authors adopted this as well, particularly arm since it has fastisel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129676
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Chris Lattner [Sun, 17 Apr 2011 22:05:17 +0000 (22:05 +0000)]
now that predicates have a decent abstraction layer on them, introduce a new
kind of predicate: one that is specific to imm nodes. The predicate function
specified here just checks an int64_t directly instead of messing around with
SDNode's. The virtue of this is that it means that fastisel and other things
can reason about these predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129675
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Chris Lattner [Sun, 17 Apr 2011 21:38:24 +0000 (21:38 +0000)]
Rework our internal representation of node predicates to expose more
structure and fix some fixmes. We now have a TreePredicateFn class
that handles all of the decoding of these things. This is an internal
cleanup that has no impact on the code generated by tblgen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129670
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Chris Lattner [Sun, 17 Apr 2011 21:36:19 +0000 (21:36 +0000)]
remove some debugging code I added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129668
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Chris Lattner [Sun, 17 Apr 2011 20:23:29 +0000 (20:23 +0000)]
1. merge fast-isel-shift-imm.ll into fast-isel-x86-64.ll
2. implement rdar://
9289501 - fast isel should fold trivial multiplies to shifts
3. teach tblgen to handle shift immediates that are different sizes than the
shifted operands, eliminating some code from the X86 fast isel backend.
4. Have FastISel::SelectBinaryOp use (the poorly named) FastEmit_ri_ function
instead of FastEmit_ri to simplify code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129666
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Chris Lattner [Sun, 17 Apr 2011 17:47:38 +0000 (17:47 +0000)]
fix an x86 fast isel issue where we'd completely give up on folding an address
when we have a global variable base an an index. Instead, just give up on
folding the global variable.
Before we'd geenrate:
_test: ## @test
## BB#0:
movq _rtx_length@GOTPCREL(%rip), %rax
leaq (%rax), %rax
addq %rdi, %rax
movzbl (%rax), %eax
ret
now we generate:
_test: ## @test
## BB#0:
movq _rtx_length@GOTPCREL(%rip), %rax
movzbl (%rax,%rdi), %eax
ret
The difference is even more significant when there is a scale
involved.
This fixes rdar://
9289558 - total fail with addr mode formation at -O0/x86-64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129664
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Chris Lattner [Sun, 17 Apr 2011 17:12:08 +0000 (17:12 +0000)]
fix an oversight which caused us to compile the testcase (and other
less trivial things) into a dummy lea. Before we generated:
_test: ## @test
movq _G@GOTPCREL(%rip), %rax
leaq (%rax), %rax
ret
now we produce:
_test: ## @test
movq _G@GOTPCREL(%rip), %rax
ret
This is part of rdar://
9289558
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129662
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Chris Lattner [Sun, 17 Apr 2011 17:05:12 +0000 (17:05 +0000)]
tidy up and reduce indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129661
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Chris Lattner [Sun, 17 Apr 2011 06:35:44 +0000 (06:35 +0000)]
Fix rdar://
9289512 - not folding load into compare at -O0
The basic issue here is that bottom-up isel is matching the branch
and compare, and was failing to fold the load into the branch/compare
combo. Fixing this (by allowing folding into any instruction of a
sequence that is selected) allows us to produce things like:
cmpb $0, 52(%rax)
je LBB4_2
instead of:
movb 52(%rax), %cl
cmpb $0, %cl
je LBB4_2
This makes the generated -O0 code run a bit faster, but also speeds up
compile time by putting less pressure on the register allocator and
generating less code.
This was one of the biggest classes of missing load folding. Implementing
this shrinks 176.gcc's c-decl.s (as a random example) by about 4% in (verbose-asm)
line count.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129656
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Chris Lattner [Sun, 17 Apr 2011 06:03:19 +0000 (06:03 +0000)]
split a complex predicate out to a helper function. Simplify two for loops,
which don't need to check for falling off the end of a block *and* end of phi
nodes, since terminators are never phis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129655
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Eli Friedman [Sun, 17 Apr 2011 02:36:27 +0000 (02:36 +0000)]
Remove working entry from README.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129654
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Chris Lattner [Sun, 17 Apr 2011 01:16:47 +0000 (01:16 +0000)]
fix rdar://
9289583 - fast isel should handle non-canonical commutative binops
allowing us to fold the immediate into the 'and' in this case:
int test1(int i) {
return 8&i;
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129653
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Eli Friedman [Sat, 16 Apr 2011 23:25:34 +0000 (23:25 +0000)]
PR9055: extend the fix to PR4050 (r70179) to apply to zext and anyext.
Returning a new node makes the code try to replace the old node, which
in the included testcase is killed by CSE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129650
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Frits van Bommel [Sat, 16 Apr 2011 14:32:34 +0000 (14:32 +0000)]
Rename a misleadingly-named variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129644
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