driver: mpu: to support mpu6881/mpu6880

Change-Id: I731788cd35d27d2aab946ccb22f744aad85f7be3
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

ARM64: dts: rk3368-p9: set sleep mode config RKPM_SLP_ARMOFF

Change-Id: I65b87a37f029e316cf048bf7da790d51a046cca2
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

ARM64: dts: rockchip: enable rockchip_suspend node of rk3368-p9 and rk3368-sheep board

Change-Id: Iff11ec889c372f279cf638ff2f3f2b72824abd4c
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

arm64: dts: rockchip: enable dp for rk3399 evb rev3 board

Change-Id: I91043fd5caa8a639844658cc0410372785b1c43d
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

arm64: dts: rockchip: rk3399: add dclk pll sources

Change-Id: I0e29d67d5e3738b18a7407a049d216f8dcebb8e8
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

Documentation: dt-bindings: rockchip: introduce dclk_source

Change-Id: Iee4d40ede334f418fd4edb51319b5e03f25467c0
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

Documentation: dt-bindings: rockchip: introduce display plls

Change-Id: Ifa7129bc5dd625c7f78040b0d506930be24c5aa0
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: support setting specail pll for hdmi

In order to get lower jitter clock for hdmi tmds, Hardware
design that: direct get tmds clock from vpll, bypass vop.

This design can make hdmi good works, but also limit hdmi's
clock source, the vop which hdmi use need also assign to vpll,
and use same clock rate, it's hardware limitation.

This patch add a mechanism to select dclk's parent pll, then
can allocate correct pll for hdmi.

Change-Id: I9e3b4b6d3756c409782df0605706be4203d69a32
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Suggested-by: Heiko Stuebner <heiko@sntech.de>

driver: sensor: ak09911: to match hal code, compatible with ak8963

Change-Id: Ia5768a4466512063948c48c2139356522a4557ac
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

dmaengine: pl330: redefine the cyclic transfer

dmaengine_prep_dma_cyclic, to use buf_addr with size buf_len,
generate an interrupt every period_len. But DMA must restart
every period_len, it may be blocked. If i2s use it, it may
cause sound break. Infiniteloop is helpful to solve this
issue. In infiniteloop mode, when DMA transfers all buf_len
data, it goes back to the start of buf_addr and continue to
transfer endless.

Change-Id: Ibbc92c416d0a9dd58633e7991176c86300c3da98
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

arm64: dts: rockchip: config dr_mode as otg for usb on rk3328-evb

Because we have supported to force otg mode for rk3328 in the commit
2b9b897141f1 ("phy: rockchip-inno-usb2: support to force otg mode"),
so let's config dr_mode as otg for usb otg port, and then user can
use otg peripheral mode and host mode as needed.

Change-Id: I6f55fb2aad1b8c49498af829475a8b59215251e5
Signed-off-by: William Wu <william.wu@rock-chips.com>

arm: dts: rk322x-android: add otg vbus gpio for usb2 phy0

This patch adds otg vbus gpio for usb2 phy0, and then we
can control otg vbus for otg host mode.

Change-Id: I685060270f9cb0963931a84035cad7286d99a469
Signed-off-by: William Wu <william.wu@rock-chips.com>

phy: rockchip-inno-usb2: support to force otg mode

This patch creates an usb2 phy attribute group and
provides an attribute "otg_mode" for otg port to
force otg mode independently of the voltage of otg
id pin.

In order to implement the force mode function, we can
select otg plug indicator output (AKA iddig) from GRF,
and set GRF USB otg plug indicator to "0" or "1" to
control iddig status.

We only support rk322x/rk3328 to force otg mode for
the time being.

And we need to disable usb auto suspend function if
we want to force otg mode. Add 'usbcore.autosuspend=-1'
in cmdline to disable usb auto suspend.

Usage:
[1] Force host mode
    echo host > /sys/devices/platform/<u2phy dev name>/mode

[2] Force peripheral mode
    echo peripheral > /sys/devices/platform/<u2phy dev name>/mode

[3] Force otg mode
    echo otg > /sys/devices/platform/<u2phy dev name>/mode

Legacy Usage:
[1] Force host mode
    echo 1 > /sys/devices/platform/<u2phy dev name>/mode

[2] Force peripheral mode
    echo 2 > /sys/devices/platform/<u2phy dev name>/mode

[3] Force otg mode
    echo 0 > /sys/devices/platform/<u2phy dev name>/mode

Change-Id: I875b60b0390e3bd9af34b740cba8f5d53e1df752
Signed-off-by: William Wu <william.wu@rock-chips.com>

dt-bindings: display: screen-timing: add physical size for h546dlb01

Change-Id: I51ba6c2bdacddbc16dbf79df1f36ef6f09340989
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

phy: rockchip-inno-usb2: fix possibe deadlock

The commit 611ec35fa148 ("phy: rockchip-inno-usb2: fix some
race conditions") use mutex lock to protect charger detect
work, but it will cause the following possible deadlock.

[ INFO: possible circular locking dependency detected ]
4.4.66 #563 Not tainted
-------------------------------------------------------
kworker/3:1/145 is trying to acquire lock:
(&rport->mutex){+.+...}, at: [<ffffff80083f286c>] rockchip_chg_detect_work+0x6c/0x3d0

but task is already holding lock:
((&(&rport->chg_work)->work)){+.+...}, at: [<ffffff80080be6e4>] process_one_work+0x1c4/0x6ac

which lock already depends on the new lock.
the existing dependency chain (in reverse order) is:

-> #1 ((&(&rport->chg_work)->work)){+.+...}:
[<ffffff80080fda40>] __lock_acquire+0x15c0/0x195c
[<ffffff80080fe5e8>] lock_acquire+0x190/0x250
[<ffffff80080bf534>] flush_work+0x4c/0x274
[<ffffff80080bf944>] __cancel_work_timer+0x130/0x1c0
[<ffffff80080bf9fc>] cancel_delayed_work_sync+0x10/0x18
[<ffffff80083f17a8>] rockchip_usb2phy_exit+0x54/0x6c
[<ffffff80083f07ac>] phy_exit+0x64/0xb4
[<ffffff8008772810>] dwc3_core_exit+0x44/0x98
[<ffffff80087728b0>] dwc3_suspend_common+0x4c/0x5c
[<ffffff8008772a68>] dwc3_runtime_suspend+0x38/0x5c
[<ffffff8008571784>] pm_generic_runtime_suspend+0x28/0x38
[<ffffff8008573464>] __rpm_callback+0x40/0x74
[<ffffff80085734f4>] rpm_callback+0x5c/0x80
[<ffffff8008573bc4>] rpm_suspend+0x31c/0x688
[<ffffff80085751ec>] __pm_runtime_suspend+0x58/0xa4
[<ffffff800877efc0>] dwc3_rockchip_probe+0x3f8/0x574
[<ffffff800856bcd0>] platform_drv_probe+0x58/0xa4
[<ffffff8008569bb0>] driver_probe_device+0x118/0x2b0
[<ffffff8008569e9c>] __device_attach_driver+0x88/0x98
[<ffffff8008567f4c>] bus_for_each_drv+0x7c/0xac
[<ffffff80085699e4>] __device_attach+0xa8/0x128
[<ffffff800856a00c>] device_initial_probe+0x10/0x18
[<ffffff8008569000>] bus_probe_device+0x2c/0x90
[<ffffff800856948c>] deferred_probe_work_func+0x78/0xa8
[<ffffff80080be858>] process_one_work+0x338/0x6ac
[<ffffff80080bfd54>] worker_thread+0x300/0x428
[<ffffff80080c5758>] kthread+0x104/0x10c
[<ffffff8008083080>] ret_from_fork+0x10/0x50

-> #0 (&rport->mutex){+.+...}:
[<ffffff80080faacc>] print_circular_bug+0x64/0x2c4
[<ffffff80080fd70c>] __lock_acquire+0x128c/0x195c
[<ffffff80080fe5e8>] lock_acquire+0x190/0x250
[<ffffff8008c67ac0>] mutex_lock_nested+0x80/0x3d0
[<ffffff80083f286c>] rockchip_chg_detect_work+0x6c/0x3d0
[<ffffff80080be858>] process_one_work+0x338/0x6ac
[<ffffff80080bfd54>] worker_thread+0x300/0x428
[<ffffff80080c5758>] kthread+0x104/0x10c
[<ffffff8008083080>] ret_from_fork+0x10/0x50

other info that might help us debug this:

Possible unsafe locking scenario:

        CPU0                    CPU1
        ----                    ----
   lock((&(&rport->chg_work)->work));
                                lock(&rport->mutex);
                                lock((&(&rport->chg_work)->work));
   lock(&rport->mutex);

  *** DEADLOCK ***

2 locks held by kworker/3:1/145:

stack backtrace:
CPU: 3 PID: 145 Comm: kworker/3:1 Not tainted 4.4.66 #563
Hardware name: Rockchip RK3399 Evaluation Board v3 (Android) (DT)
Workqueue: events rockchip_chg_detect_work
Call trace:
[<ffffff800808a814>] dump_backtrace+0x0/0x1c8
[<ffffff800808a9f0>] show_stack+0x14/0x1c
[<ffffff80083c1fa0>] dump_stack+0xb0/0xec
[<ffffff80080fad10>] print_circular_bug+0x2a8/0x2c4
[<ffffff80080fd70c>] __lock_acquire+0x128c/0x195c
[<ffffff80080fe5e8>] lock_acquire+0x190/0x250
[<ffffff8008c67ac0>] mutex_lock_nested+0x80/0x3d0
[<ffffff80083f286c>] rockchip_chg_detect_work+0x6c/0x3d0
[<ffffff80080be858>] process_one_work+0x338/0x6ac
[<ffffff80080bfd54>] worker_thread+0x300/0x428
[<ffffff80080c5758>] kthread+0x104/0x10c
[<ffffff8008083080>] ret_from_fork+0x10/0x50

Change-Id: I4289afb05d334bf79000090f9071cf428817a583
Signed-off-by: William Wu <william.wu@rock-chips.com>

arm64: rockchip_linux_defconfig: enable MPP_SERVICE

Change-Id: I12cb15a44e31f768bac960e3a5e6b9371d221ed3
Signed-off-by: Hans Yang <yhx@rock-chips.com>

drm/rockchip: limit gem buffer to 32bit mapping

Change-Id: I64537668aa10a2e26bdd19ac79bc417aa6c4a437
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm: support loader protect for panel

Change-Id: Ie9330e3380a4925a4b7603e7206f1e0d186d2156
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

ARM64: dts: rk3328-evb: enable vepu & h265e default

Change-Id: I94685dbeea3ceffa106593ff597f50404f58f34a
Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>

ARM64: dts: rk3328: add vepu & h265e dts node

Change-Id: I2990ac7e43d4b2d2efbf5e9cf3abe124e8767648
Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>

driver: video: rockchip: add new driver of vpu

this driver only support h264e & h265e. if you want to
enable the driver, you must modify the menuconfig and
turn on MPP_SERVICE & MPP_DEVICE.

Change-Id: I7f1c6e473eaf7aedb4fa86791412b5fbcb2c531d
Signed-off-by: buluess.li <buluess.li@rock-chips.com>
Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>

Merge tag 'lsk-v4.4-17.05-android' of git://git.linaro.org/kernel/linux-linaro-stable.git

LSK 17.05 v4.4-android

* tag 'lsk-v4.4-17.05-android': (266 commits)
  BACKPORT: mm/slab: clean up DEBUG_PAGEALLOC processing code
  Linux 4.4.70
  UPSTREAM: arm64: hibernate: Support DEBUG_PAGEALLOC
  BACKPORT: arm64: vmlinux.ld: Add mmuoff data sections and move mmuoff text into idmap
  BACKPORT: arm64: Create sections.h
  ANDROID: uid_sys_stats: defer io stats calulation for dead tasks
  ANDROID: AVB: Fix linter errors.
  ANDROID: AVB: Fix invalidate_vbmeta_submit().
  drivers: char: mem: Check for address space wraparound with mmap()
  nfsd: encoders mustn't use unitialized values in error cases
  drm/edid: Add 10 bpc quirk for LGD 764 panel in HP zBook 17 G2
  PCI: Freeze PME scan before suspending devices
  PCI: Fix pci_mmap_fits() for HAVE_PCI_RESOURCE_TO_USER platforms
  tracing/kprobes: Enforce kprobes teardown after testing
  osf_wait4(): fix infoleak
  genirq: Fix chained interrupt data ordering
  uwb: fix device quirk on big-endian hosts
  metag/uaccess: Check access_ok in strncpy_from_user
  metag/uaccess: Fix access_ok()
  iommu/vt-d: Flush the IOTLB to get rid of the initial kdump mappings
  ...

Revert "UPSTREAM: pinctrl: rockchip: avoid hardirq-unsafe functions in irq_chip"

This reverts commit a8b4e18cf1e98ed3b36175cb4e3ef422c03ac01c.

Which will cause such error:

BUG: sleeping function called from invalid context at kernel/locking/mutex.c:620
in_atomic(): 1, irqs_disabled(): 128, pid: 141, name: irq/95-fusb302
1 lock held by irq/95-fusb302/141:
 #0:  (&(&chip->irq_lock)->rlock){......}, at: [<ffffff800859e3a0>] fusb_irq_disable+0x20/0x68
irq event stamp: 52
hardirqs last  enabled at (51): [<ffffff80080bcc30>] queue_work_on+0x68/0x80
hardirqs last disabled at (52): [<ffffff8008c6f41c>] _raw_spin_lock_irqsave+0x20/0x60
softirqs last  enabled at (0): [<ffffff800809e9ec>] copy_process.isra.54+0x390/0x1728
softirqs last disabled at (0): [<          (null)>]           (null)
Preemption disabled at:[<ffffff800859e3a0>] fusb_irq_disable+0x20/0x68

CPU: 5 PID: 141 Comm: irq/95-fusb302 Not tainted 4.4.70 #30
Hardware name: Rockchip RK3399 Evaluation Board v3 (Android) (DT)
Call trace:
[<ffffff800808a82c>] dump_backtrace+0x0/0x1c4
[<ffffff800808aa04>] show_stack+0x14/0x1c
[<ffffff80083c3b90>] dump_stack+0xa8/0xe0
[<ffffff80080cf560>] ___might_sleep+0x214/0x224
[<ffffff80080cf5e4>] __might_sleep+0x74/0x84
[<ffffff8008c6c1ac>] mutex_lock_nested+0x48/0x3cc
[<ffffff80083fe2b0>] rockchip_irq_bus_lock+0x28/0x34
[<ffffff800810b680>] __irq_get_desc_lock+0x68/0x88
[<ffffff800810d558>] __disable_irq_nosync+0x28/0x70
[<ffffff800810d5ac>] disable_irq_nosync+0xc/0x14
[<ffffff800859e3b4>] fusb_irq_disable+0x34/0x68
[<ffffff800859e410>] cc_interrupt_handler+0x28/0x38
[<ffffff800810cd48>] irq_thread_fn+0x28/0x68
[<ffffff800810cf80>] irq_thread+0x130/0x234
[<ffffff80080c58e8>] kthread+0x104/0x10c
[<ffffff8008083080>] ret_from_fork+0x10/0x50

or

BUG: sleeping function called from invalid context at kernel/locking/mutex.c:620
in_atomic(): 1, irqs_disabled(): 128, pid: 0, name: swapper/0
INFO: lockdep is turned off.
irq event stamp: 111558
hardirqs last  enabled at (111557): [<ffffff8008116cdc>] rcu_idle_exit+0x70/0x80
hardirqs last disabled at (111558): [<ffffff80080f1078>] cpu_startup_entry+0xc0/0x42c
softirqs last  enabled at (111554): [<ffffff80080a6794>] _local_bh_enable+0x3c/0x44
softirqs last disabled at (111553): [<ffffff80080a7000>] irq_enter+0x28/0x64
Preemption disabled at:[<ffffff80080f1308>] cpu_startup_entry+0x350/0x42c

CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.4.70 #30
Hardware name: Rockchip RK3399 Evaluation Board v3 (Android) (DT)
Call trace:
[<ffffff800808a82c>] dump_backtrace+0x0/0x1c4
[<ffffff800808aa04>] show_stack+0x14/0x1c
[<ffffff80083c3b90>] dump_stack+0xa8/0xe0
[<ffffff80080cf560>] ___might_sleep+0x214/0x224
[<ffffff80080cf5e4>] __might_sleep+0x74/0x84
[<ffffff8008c6c1ac>] mutex_lock_nested+0x48/0x3cc
[<ffffff80083fe2b0>] rockchip_irq_bus_lock+0x28/0x34
[<ffffff800810b680>] __irq_get_desc_lock+0x68/0x88
[<ffffff800810d558>] __disable_irq_nosync+0x28/0x70
[<ffffff800810d5ac>] disable_irq_nosync+0xc/0x14
[<ffffff8008621f20>] bcmsdh_oob_intr_set+0x4c/0x6c
[<ffffff8008621f5c>] wlan_oob_irq+0x1c/0x38
[<ffffff800810bd28>] handle_irq_event_percpu+0x150/0x3e8
[<ffffff800810c004>] handle_irq_event+0x44/0x74
[<ffffff800810f53c>] handle_level_irq+0xe4/0x11c
[<ffffff800810b228>] generic_handle_irq+0x1c/0x2c
[<ffffff80083fe068>] rockchip_irq_demux+0xe0/0x188
[<ffffff800810b228>] generic_handle_irq+0x1c/0x2c
[<ffffff800810b5b0>] __handle_domain_irq+0xb0/0xec
[<ffffff8008080f70>] gic_handle_irq+0xbc/0x154

Change-Id: I7cfbeaf7df17fc4e923e89917199b7f1c773455a
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

arm64: dts: rk3328: dmac: add peripherals-req-type-burst

Change-Id: I097e13f3e9e88c5624bcd67eaaf66d773465939b
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

ARM: dts: rk3xxx: dmac: add peripherals-req-type-burst

Change-Id: Iab3df00b2d228498d059ef2ede8d2ed0e598f408
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

ARM: dts: rk322x: dmac: add peripherals-req-type-burst

Change-Id: I2a748a2a7a5b00a2c7ff116bac7358d6267cb45f
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

ARM: dts: rk312x: dmac: add quirks

1. arm,pl330-broken-no-flushp
2. peripherals-req-type-burst

Change-Id: I33a357e10a011b5c22fb8aa7c8362fa20f051d66
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

ASoC: rockchip: i2s: fixup clk div

we found mclk maybe not precise as required because of PLL,
but it still can be used and no side effect. for example, if we
require mclk 11289600, but get 11289598, it doesn't matter.
so using DIV_ROUND_CLOSEST to fix it.

Change-Id: If8453a7a08b319da81b07d572b02247bd7e7bd27
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

arm64: dts: rockchip: enable video decoder for RK3328 EVB

This commit would enable the VDPU and RKVDEC devices.
The VDPU works in the non combo mode.

Change-Id: I643350d5a2ac17759984fda2e95fb2b82701e7cf
Signed-off-by: Randy Li <randy.li@rock-chips.com>

video: rockchip: vpu: introduce safe reset method

Even the same type video IP would request a different numbers
of reset control.

From the RK3328 times, the video IP also request decrease the
frequency of the clock to lower than 300 MHZ before resetting.
It seems no hard to apply it into the previous platform.

Change-Id: Iacf1accf24c8776bb8b425b613e6e34215380203
Signed-off-by: Randy Li <randy.li@rock-chips.com>

arm64: dts: rockchip: add video decoder nodes on rk3328

Jung and I meet some problem the video decoder, so
we just release the VDPU standalone this time.

It seems that the iommu can't attach to two different
IP at the same time.

Change-Id: I24d73cd5ab2c3d32da6ef29661061c7fda9186f2
Signed-off-by: Randy Li <randy.li@rock-chips.com>

ARM: dts: rockchip: enable sdmmc and sdio for rk322x-android

Change-Id: Ibed59e1bded5e81dd2f84438d3fa16a3dc0a1ba1
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM: dts: rockchip: add sdmmc and sdio nodes for rk3228 SoC

Change-Id: I50309e972b9c606782195b91d1f034f1336af0cd
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

ARM: dts: rockchip: fix compatible string for eMMC node of rk3228 SoC

Change-Id: I2ee59491c79dd0e8a201f6478c6ca40cb8437e42
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

Documentation: rockchip-dw-mshc: add description for rk3228

Add "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc" for
dwmmc on rk322x platform.

Change-Id: I8217d237260a33ce5b115080cf4d41ad4a5733e8
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

arm64: dts: rk3399: sapphire: enabled dp default

Change-Id: Icfdea500e35164c90c75c9b538285a2a9691cbb6
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

clk: rockchip: rk3228: add more flags for dclk_vop

Change-Id: Ie5838b20f419d667831e7d99f4b95856731ef0ef
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

clk: rockchip: rk3228: export hdmiphy clock

Change-Id: Ib7acd4c2f576ad320e069ab2bd9137156062e2d9
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

arm64: dts: rk3328-evb: enable hdmi audio

Change-Id: Ic67744ac5554b90b6d9f85eeedf4721562f8155f
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

phy: rockchip-inno-usb2: fix some race conditions

There are some race conditions related to phy power on/off
and otg charger detection work, otg sm work. I can find at
least three race conditions at present.

Race condition[1]:
The first race condition involving phy power on/off which
may be caused by the following case.

Test on rk3399 evaluation board Type-C0, connect to PC usb
port with Type-C cable, then phy power on/off operation may
be done twice because of race condition between phy driver
and usb controller driver.

CPU 0:
- rockchip_usb2phy_bvalid_irq()
 - rockchip_usb2phy_otg_sm_work()
  - detect connect to PC usb, do phy power on
   - rockchip_usb2phy_power_on()

CPU 1:
- dwc3 driver do runtime resume process
 - dwc3_runtime_resume()
  - dwc3_core_init()
   - phy_power_on()
    - rockchip_usb2phy_power_on()

Although we use a suspended flag in rockchip_usb2phy_power_on()
to avoid doing the same things twice, but it's not enough to
prevent race condition if phy driver and usb controller driver
access the rockchip_usb2phy_power_on() at the same time. This
race condition may cause clk management unbalanced.

Race condition[2]:
The second race condition related to phy power on/off and otg
charger detection work. We need to keep the usb phy staying in
suspend mode when do usb charger detection. But now it don't
have any protection to prevent the other threads to operate phy
during charger detection.

The problem can also be easily reproduced on rk3399 evaluation
board Type-C0 when connect to PC usb port with Type-C cable.

CPU 0:
- rockchip_chg_detect_work()
 - power off phy and start to do charge detection work

CPU 1:
- dwc3 driver do runtime resume process
 - dwc3_runtime_resume()
  - dwc3_core_init()
   - phy_power_on()
    - power on phy again

This race condition may cause charger detection and later usb
enumeration abnormally.

Race condition[3]:
The third race condition involving otg sm work. The otg sm
work can be interrupted by bvalid irq, and the bvalid irq
handler rockchip_usb2phy_bvalid_irq() will do otg sm work,
which may cause unknown error.

This patch uses mutex lock to protect the phy operations,
otg charger detection work and otg sm work.

Change-Id: Ic6845a10b3e69fe9ae6cf0b2d4e2beb098232abd
Signed-off-by: William Wu <william.wu@rock-chips.com>

Revert "drm/rockchip: vop: round_up pitches to word align"

This reverts commit 7e705c4974eaa8abaf44cb1542d3ec49d520fde8.

Change-Id: I498ade43de012f65ea39624bd2982b4a84bcbf54
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: logo: round_up pitches to word align

Change-Id: I836193ca37fb62c72c61aa47a807959c3c189925
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: logo: use unique plane property logo mirror

The logo framework use state->rotation may conflict to common drm
update, cause display abnormal

Change-Id: I09b6b898a7606cd05371af1f4b25254945923d0d
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

UPSTREAM: clk: rockchip: mark some special clk as critical on rk3368

The jtag clk no driver to handle them.
But this clk need enable,so make it as critical.

The ddrphy/ddrupctl clks no driver to handle them,
Chip design requirements for these clock to always on,

The pmu_hclk_otg0 is Chip design defect, must be always on,

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit 223c24be740d293519ef8e03f5c075fab5512fd2)

Conflicts:
drivers/clk/rockchip/clk-rk3368.c

Change-Id: I31c1c7efb7a83652501a7f53ff5931d9f308f736
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: clk: rockchip: mark noc and some special clk as critical on rk3288

The atclk/dbg/jtag/hsic-xin12m/pclk_core clks no driver to handle them.
But this clks need enable,so make it as ignore_unused for now.

The ddrupctl0/ddrupctl1/publ0/publ1 clks no driver to handle them,
Chip design requirements for these clock to always on,

The pmu_hclk_otg0 is Chip design defect, must be always on,

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit 55bb6a633c33caf68ab470907ecf945289cb733d)

Conflicts:
drivers/clk/rockchip/clk-rk3288.c

Change-Id: I6271a903deb9ca21b5e74fd2c1ad4cf69f7021e1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036

No driver to handle this clk yet, but chip design requiress for this clock
supplying the ddr controller to be always on.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit f2893aaba435fcb55b86dc1be8c6f64f8d60e64b)

Change-Id: I3cd9578f73a69eb0f09d1f40c22ee55b393149aa
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: clk: rockchip: Make uartpll a child of the gpll on rk3036

The shared uart-pll is on boot a child of the apll that can get changed
by cpu frequency scaling. So move it away to the more stable gpll to
make sure the uart doesn't break on cpu frequency changes.

This turned up during the 4.11 merge-window when commit
6a171b299379 ("serial: 8250_dw: Allow hardware flow control to be used")
added general termios enablement making the uart on rk3036 change
frequency and thus making it susceptible for the frequency scaling issue.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit f8ba2d68e54fbca340ad0fce97397291ba9637bc)

Change-Id: Ia8683d7b49523284043457727665d7e58d1551ec
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p on rk3036

The mux_pll_src_apll_dpll_gpll_usb480m_p parent list was missing a ","
between the 3rd and 4th parent names, making them fall together and thus
lookups fail. Fix that.

Fixes: 5190c08b2989 ("clk: rockchip: add clock controller for rk3036")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit 9b1b23f03abdd25ffde8bbfe5824b89bc0448c28)

Change-Id: I535b64fc7c902a4e9c64b4b803bb03126b7ba110
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: clk: rockchip: mark noc and some special clk as critical on rk3228

The jtag/bus/peri/initmem/rom/stimer/phy clks no driver to handle them.
But this clks need enable,so make it as critical.

The ddrupctl/ddrmon/ddrphy clks no driver to handle them,
Chip design requirements for these clock to always on,

The hclk_otg_pmu is Chip design defect, must be always on,
The new document will update the description of this clock.

All these non-noc/non-arbi clocks,IC suggest always on,
Because it's have some order limitation, between the NOC clock switch
and bus IDLE(or pd on/off).

The software is not very good to solve this constraint.
Always on these clocks, has no effect on the system power consumption.
The new document will update the description of these clock.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit f18c0994cda54dc21d3b0ce2ba130b5ea8f58666)

Conflicts:
drivers/clk/rockchip/clk-rk3228.c

Change-Id: Ie2c4c8d2c73a62efe96e64a3ec638970e82051d1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

arm: rockchip_defconfig: support dtb appended and bootargs extended

This patch support using appended device tree blob to zImage and
supplementing the appended DTB with traditional ATAG information.

Change-Id: I8e8e63513c17544fdafd9107fda425740c63220e
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

rk: gcc-wrapper.py ignore atags_to_fdt.c:98

Change-Id: Ie7d1c5b7ba5d1147c1996d73f19d5e0d768998ec
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

UPSTREAM: ARM: 8500/1: fix atags_to_fdt with stack-protector-strong

Building with CONFIG_CC_STACKPROTECTOR_STRONG triggers protection code
generation under CONFIG_ARM_ATAG_DTB_COMPAT but this is too early for
being able to use any of the stack_chk code. Explicitly disable it for
only the atags_to_fdt bits.

Change-Id: Ib1f66cc4083b4f04d713c3c70610b8a337a6b0ff
Suggested-by: zhxihu <zhxihu@marvell.com>
Signed-off-by: Kees Cook <keescook@chromium.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 7f66cd3f5420e7d11abd234033e7cb7a9738fc38)

UPSTREAM: clk: rockchip: add clock controller for rk3128

Add the clock tree definition for the new rk3128 SoC.
And it also applies to the RK3126 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit f6022e88faca1a6a21cbd0f009b477bc530b9cc7)

Change-Id: Ib933e398bc8e40d8659bc1cdc419116f48f6ae30
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: clk: rockchip: add dt-binding header for rk3128

Add the dt-bindings header for the rk3128,
that gets shared between the clock controller and
the clock references in the dts.
Add softreset ID for rk3128.
And it also applies to the RK3126 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit b20841b9e0d730206de6ee95f4d00e3f8815ad50)

Change-Id: I70c055570319abe4547ac2a42b9139c7248abb13
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: dt-bindings: add bindings for rk3128 clock controller

Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit de2ddc3b694d4594d922534db19e15fc39a3fcee)

Change-Id: I7ee66379d024020a9f8bcc98c3d9c4341391cccd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

OP-TEE: fix warning when LPAE is activated on ARM

When LPAE is activated, the dma_addr_t type is u64,
but pointer is still 32bit on arm32 platform.
1. %pad is used to print dma_addr_t type in log.
2. The member paddr(dma_addr_t type) in struct shm is cast
to unsigned long when it needs to be cast to a pointer. The cast
is fine as the value of paddr in struct shm is always less than 4G.

Change-Id: I1e2112796f657759dfa845258ea19558cb84c4ec
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>

fiq debugger: rockchip: fix crash because of invalid sp_el0

(1) use cpu id from bl31 delivers;
(2) sp_el0 should point to kernel address in EL1 mode.

On ARM64, kernel uses sp_el0 to store current_thread_info(),
we see a problem: when fiq occurs, cpu is EL1 mode but sp_el0
point to userspace address. At this moment, if we read
'current_thread_info()->cpu' or other, it leads an error.

We find above situation happens when save/restore cpu context
between system mode and user mode under heavy load.
Like 'ret_fast_syscall()', kernel restore context of user mode,
but fiq occurs before the instruction 'eret', so this causes the
above situation.

Assembly code:

ffffff80080826c8 <ret_fast_syscall>:

...skipping...

ffffff80080826fc:       d503201f        nop
ffffff8008082700:       d5384100        mrs     x0, sp_el0
ffffff8008082704:       f9400c00        ldr     x0, [x0,#24]
ffffff8008082708:       d5182000        msr     ttbr0_el1, x0
ffffff800808270c:       d5033fdf        isb
ffffff8008082710:       f9407ff7        ldr     x23, [sp,#248]
ffffff8008082714:       d5184117        msr     sp_el0, x23
ffffff8008082718:       d503201f        nop
ffffff800808271c:       d503201f        nop
ffffff8008082720:       d5184035        msr     elr_el1, x21
ffffff8008082724:       d5184016        msr     spsr_el1, x22
ffffff8008082728:       a94007e0        ldp     x0, x1, [sp]
ffffff800808272c:       a9410fe2        ldp     x2, x3, [sp,#16]
ffffff8008082730:       a94217e4        ldp     x4, x5, [sp,#32]
ffffff8008082734:       a9431fe6        ldp     x6, x7, [sp,#48]
ffffff8008082738:       a94427e8        ldp     x8, x9, [sp,#64]
ffffff800808273c:       a9452fea        ldp     x10, x11, [sp,#80]
ffffff8008082740:       a94637ec        ldp     x12, x13, [sp,#96]
ffffff8008082744:       a9473fee        ldp     x14, x15, [sp,#112]
ffffff8008082748:       a94847f0        ldp     x16, x17, [sp,#128]
ffffff800808274c:       a9494ff2        ldp     x18, x19, [sp,#144]
ffffff8008082750:       a94a57f4        ldp     x20, x21, [sp,#160]
ffffff8008082754:       a94b5ff6        ldp     x22, x23, [sp,#176]
ffffff8008082758:       a94c67f8        ldp     x24, x25, [sp,#192]
ffffff800808275c:       a94d6ffa        ldp     x26, x27, [sp,#208]
ffffff8008082760:       a94e77fc        ldp     x28, x29, [sp,#224]
ffffff8008082764:       f9407bfe        ldr     x30, [sp,#240]
ffffff8008082768:       9104c3ff        add     sp, sp, #0x130
ffffff800808276c:       d69f03e0        eret

Change-Id: I071e899f8a407764e166ca0403199c9d87d6ce78
Signed-off-by: chenjh <chenjh@rock-chips.com>

firmware: rockchip: use sp_el1 from bl31 delivers

we think 'if (fiq_pt_regs.pstate & 0x10)' doesn't make any
sense, use sp_el1 from bl31 delivers is ok.

Change-Id: I0792d76e39912b4ca5484b029761daac05cd719b
Signed-off-by: chenjh <chenjh@rock-chips.com>

ARM64: dts: rk3328-evb: enable hdmi

Change-Id: I42b74009d0ddded9afc10b24e453ca26808bd18e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

ARM64: dts: rk3328: add hdmi display node

Change-Id: Ie4821b0c5e49c7b4ee083a2250a71f8ee3edb4e1
Signed-off-by: xuhuicong <xhc@rock-chips.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

arm64: rockchip_linux_defconfig: update by savedefconfig

Change-Id: I9fc62405d5fad1979d35ada78249a388b0a547dd
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM: rockchip_linux_defconfig: update by savedefconfig

Change-Id: I2b1de1cd8ee600e593d41cdad0516703d6c94558
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM: rockchip_defconfig: update by savedefconfig

Change-Id: I5503f37643bd7b9cd0b80a3afbd9e0293608d0cd
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

arm64: rockchip_defconfig: update by savedefconfig

ROCKCHIP_CPUINFO is default y now.

Change-Id: I4d56e98265ceac3dc071c440a61fbffc736120c6
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

drm/rockchip: hdmi: support RK3328

Change-Id: I7d93f0d494f6824b0b6e2f82c2c1a57342ea551e
Signed-off-by: Hans Yang <yhx@rock-chips.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

clk: rockchip: rk3328: add more flags for dclk_lcdc

Add CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT
for dclk_lcdc.

Change-Id: I19a4a8e5f9e2cc5fda8b70f1b632dccd538e02a0
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

ARM64: dts: rockchip: add cpu version in cpuinfo for rk3328

Change-Id: Ief9dd80db35b7b55285b6773f270893a66da5f9d
Signed-off-by: Liang Chen <cl@rock-chips.com>

soc: rockchip: cpuinfo: read cpu version from eFuse

Change-Id: Ia18ff4e745f09fa04690bb7bc6d95169c389b9d2
Signed-off-by: Liang Chen <cl@rock-chips.com>

optee: fix mutex_unlock after mutex_lock

Change-Id: Ic5a4b5b4691b11083e5fd9e327fc4be82d626bfb
Signed-off-by: sean.huang <sean.huang@rock-chips.com>

drm: bridge: dw-hdmi: fixup kernel crash when reboot with hdmi connected

when other devices bind failed,drm will unbind and re-bind all devices.
if don't cancel the delayed work but flush and destroy workqueue directly,
kernel point is likely to become NULL.

Change-Id: Ib48704186ee298cbd4daac1cdbbac5fb3906b6bb
Signed-off-by: algea.cao <algea.cao@rock-chips.com>

usb: dwc_otg_310: pcd: fix force device mode issue

When tested usb device through force device mode method,
we found that usb device failed to connect to usb host
in the following case.

1. Use micro usb 2.0 OTG interface.
2. Plug in otg cable, and the id pin was pulled down
   to Ground.
3. User space force usb to enter device mode through
   'echo 2 > /sys/bus/platform/drivers/usb20_otg/force_usb_mode'
4. Use usb 2.0 Standard-A to Standard-A cable assembly,
   plug into otg cable receptor on one side, and connect
   to PC on the other side.
5. PC fail to enumerate our device, because of usb driver
   logical issue.

This is because that the dwc_otg_pcd_check_vbus_work()
only enable usb to start connecting if check the bvalid
and iddig is high. But in the above test case, the iddig
is low, so fail to start connection work. In this patch,
we enable usb to connect if iddig is high or usb is in
force device mode.

In addition, fix some coding style to increase the readability.

Change-Id: I08f1a4e6e7e5fb246b1716a20d4572d8b866f238
Signed-off-by: William Wu <william.wu@rock-chips.com>

ARM: rockchip: select ARCH_DMA_ADDR_T_64BIT for LPAE

Rockchip RK3288 has some 64-bit capable DMA and therefore needs
dma_addr_t to be a 64-bit size. One user is the Mali GPU.

Change-Id: I47335415fb101b377c408a2631ce211cb3ae3bd8
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM: rockchip: enable ZONE_DMA for non 64-bit capable peripherals

Most IP cores on ARM Rockchip platforms can only address 32 bits of
physical memory for DMA. Thus ZONE_DMA should be enabled when LPAE
is activated.

Change-Id: I3fce3e01ba31270f066f49bc14fc2078c70d83ea
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

usb: dwc_otg_310: fix compile warning

When build with CONFIG_ARCH_DMA_ADDR_T_64BIT enabled:
drivers/usb/dwc_otg_310/dwc_otg_hcd.c: In function 'assign_and_init_hc':
drivers/usb/dwc_otg_310/dwc_otg_hcd.c:1093:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd.c:1131:21: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd.c:1161:21: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd.c:1189:21: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd_ddma.c: In function 'init_non_isoc_dma_desc':
drivers/usb/dwc_otg_310/dwc_otg_hcd_ddma.c:632:8: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd_intr.c: In function 'handle_hc_ahberr_intr':
drivers/usb/dwc_otg_310/dwc_otg_hcd_intr.c:1699:14: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

Change-Id: I4159d1d66ce24c97cc8085ee6e0fc4abde8c7423
Signed-off-by: William Wu <wulf@rock-chips.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit b001ce5aa46de28c1f52c82d1e3c111e172bd5e4)
(cherry picked from commit 4952c8819aa0f0902ae620bf5de18f7a19f85e17)

dmaengine: pl330: make transfer run infinitely without CPU intervention

this patch is based on "https://patchwork.kernel.org/patch/8349321/"

Change-Id: I377d1590186ce6e17983b931ad035d58a9e69e85
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

drm/rockchip: Don't r-b swap for 32bit logo

Change-Id: Id664731fc92fe4b770b49b4c2772e14bdf276cf2
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: vop: round_up pitches to word align

VOP pitch register is word align, need align to word.

VOP_WIN0_VIR:
  bit[31:16] win0_vir_stride_uv
    Number of words of Win0 uv Virtual width
  bit[15:0] win0_vir_width
    Number of words of Win0 yrgb Virtual width
    ARGB888 : win0_vir_width
    RGB888 : (win0_vir_width*3/4) + (win0_vir_width%3)
    RGB565 : ceil(win0_vir_width/2)
    YUV : ceil(win0_vir_width/4)

Change-Id: I89a74fae725e88cf618c5b02c45538419feba28f
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

UPSTREAM: pinctrl: rockchip: Add iomux-route switching support for rk3399

There are 2 IP blocks pin routes need to be switched, that are
uart2dbg, pcie_clkreq.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git for-next
 commit accc1ce7d2ffc6419a8eaf8c0190d9240df0c43f)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I940fbec4869f1395e66c8e693b838f58aa84a7a1

UPSTREAM: pinctrl: rockchip: Add iomux-route switching support for rk3328

There are 8 IP blocks pin routes need to be switched, that are
uart2dbg, gmac-m1-optimized, pdm, spi, i2s2, card, tsp, cif.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git for-next
 commit cedc964a59d48c793ddc0884b2f72a68fc234ae4)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I48fb4e8aa73930068b9ff6e8e547db267534b04d

UPSTREAM: pinctrl: rockchip: Add iomux-route switching support for rk3228

There are 9 IP blocks pin routes need to be switched, that are
pwm-0, pwm-1, pwm-2, pwm-3, sdio, spi, emmc, uart2, uart1.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git for-next
 commit d4970ee076f9aed396c322b41f56443a617116df)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I9e4fbfb22f37add2ba5941b2b2ae9e55ed2d28b8

UPSTREAM: pinctrl: rockchip: Add iomux-route switching support

On the some rockchip SOCS, some things like rk3399 specific uart2 can use
multiple pins. Somewhere between the pin io-cells and the uart it seems
to have some sort of switch to decide to which pin to actually route the
data.

+-------+    +--------+  /- GPIO4_B0 (pinmux 2)

| uart2 | -- | switch | --- GPIO4_C0 (pinmux 2)

+-------+    +--------+  \- GPIO4_C3 (pinmux 2)
(switch selects one of the 3 pins base on the GRF_SOC_CON7[BIT0, BIT1])

The routing switch is determined by one pin of a specific group to be set
to its special pinmux function. If the pinmux setting is wrong for that
pin the ip block won't work correctly anyway.

Change-Id: I4de8dbe8a9183dd866b7dd8289f00c6e14f83dac
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git for-next
 commit bd35b9bf8284338db35b3ff0d391b95d67b90444)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I4de8dbe8a9183dd866b7dd8289f00c6e14f83dac

UPSTREAM: pinctrl: rockchip: avoid hardirq-unsafe functions in irq_chip

With real-time preemption, regmap functions cannot be used in the
implementation of irq_chip since they use spinlocks which may sleep.

Move the setting of the mux for IRQs to an irq_bus_sync_unlock handler
where we are allowed to sleep.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: David Wu <david.wu@rock-chips.com>
(cherry picked from commit 88bb94216f59e10802aaf78c858a4146085faf18)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I94ae59be60c34022fdfdf67cd5b3059d852a5969

UPSTREAM: pinctrl: rockchip: split out verification of mux settings

We need to avoid calling regmap functions from irq handlers, so the next
commit is going to move the call to rockchip_set_mux() into an
irq_bus_sync_unlock handler.  But we can't return an error from there so
we still need to check the settings from rockchip_irq_set_type() and we
will use this new rockchip_verify_mux() function from there.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: David Wu <david.wu@rock-chips.com>
(cherry picked from git.kernel.org thierry.reding/linux-pwm.git for-next
 commit 05709c3e88f5f0adb7889facbfd546c998f65d59)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I421f9c2faf835ca821c574602d6b4a66cdde9769

UPSTREAM: pinctrl: rockchip: convert to raw spinlock

This lock is used from rockchip_irq_set_type() which is part of the
irq_chip implementation and thus must use raw_spinlock_t as documented
in Documentation/gpio/driver.txt.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: David Wu <david.wu@rock-chips.com>
(cherry picked from commit 70b7aa7a87b4593f50f634dc721e18bd1f9e5448)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I039ee4067832026f564989a05503e7507d178ee1

UPSTREAM: pinctrl: rockchip: remove unnecessary locking

regmap_update_bits does its own locking and everything else accessed
here is a local variable so there is no need to lock around it.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit f07bedc37f3cfb7b182e1337fe7c8acce71e3a25)

Change-Id: Id15c7ed10f32202c986c951ef328a84be5798af4
Signed-off-by: David Wu <david.wu@rock-chips.com>

UPSTREAM: pinctrl: rockchip: Add input schmitt support for rk3328

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from git.kernel.org thierry.reding/linux-pwm.git for-next
 commit 728d3f5afd991a44b4ec9d019d8556d8cb68db3f)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I15202d4fdd2fc35906d25e04cee63109d872405d

UPSTREAM: pinctrl: rockchip: Add input schmitt support

To prevent external signal crosstalk, some pins need to
enable input schmitt, like i2c pins, 32k-input pin and so on.

Change-Id: I2465e9df8abab3d8f46924e76a9084cda76a5a85
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit e3b357d7dfe6b38a6064562bacf5c912b3443ac0)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I2465e9df8abab3d8f46924e76a9084cda76a5a85

pinctrl: rockchip: sync with upstream for iomux recalculation

Change-Id: I795e2490e88203e8fb3d457cf293d70e34ab47e0
Signed-off-by: David Wu <david.wu@rock-chips.com>

optee: add res of cpumask_to_cpu0 and restore

if res is error,break;

Change-Id: I4c8a11ae02fef2aa30849a94afcce3af5569bbeb
Signed-off-by: sean.huang <sean.huang@rock-chips.com>
(cherry picked from commit 36bc4c52281bb9f476dc22f8bbd6e35183fa7863)
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>

camera: rockchip: camsys driver v0.0x22.0

delete node in irqpool list when thread disconnect

Change-Id: I5602e138ab9bce751e24f6dc0a0f7348755be97a
Signed-off-by: zhangyunlong <dalon.zhang@rock-chips.com>

ARM: dts: phycore-rk3288: update

Change-Id: I4aa3ffd456040c9787871096b3483995be701da5
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

net: phy: dp83867: Check if the phy is in an internal testing mode

The DP83867 seems to be always in an internal mode on our Board.
This mode can cause connection problems. We disable this mode.

Unfortunately, Register 0x31 Bit 7 is not documented and marked as reserved.
If Bit 7 is set, phy is in the internal testing mode.

Change-Id: I5d3435fcfea0e1af7c4d5ee510c249f41211f223
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

net: phy: dp83867: Disable FORCE_LINK_GOOD in PHYCTRL

With FORCE_LINK_GOOD we are not able to get a link.
According to the TRM this bit should be 0 (Normal operation) in default.

Set FORCE_LINK_GOOD to default.

Change-Id: Iaa30bef20fc6f8313c018d18646879f62db49004
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

net: phy: dp83867: Add documentation for CLK_OUT pin muxing

Add documentation of ti,clk-output-sel which can be used to select
a specific clock for CLK_OUT.

Change-Id: I5d341cac64581cd39ced0703054a70fd1eacc4a6
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

BACKPORT: net: phy: dp83867: allow RGMII_TXID/RGMII_RXID interface types

Currently dp83867 driver returns error if phy interface type
PHY_INTERFACE_MODE_RGMII_RXID is used to set the rx only internal
delay. Similarly issue happens for PHY_INTERFACE_MODE_RGMII_TXID.
Fix this by checking also the interface type if a particular delay
value is missing in the phy dt bindings. Also update the DT document
accordingly.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 34c55cf2fc75f8bf6ba87df321038c064cf2d426)
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Change-Id: Ideca1aae2512f0ee2944bc751e47436d8d1746b6

UPSTREAM: net: phy: dp83867: Add documentation for optional impedance control

Add documention of ti,min-output-impedance and ti,max-output-impedance
which can be used to correct MAC impedance mismatch using phy extended
registers.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit d6081de7e011327af089475bb60593423963526a)
Change-Id: I5e1f90caff7fee13369302a84d1dac370cb75f5e
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

net: phy: dp83867: Add binding for the CLK_OUT pin muxing option

The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.

Change-Id: I416afa8ef29d9a684068fa880f99ca7b720cfd14
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

UPSTREAM: net: phy: dp83867: Recover from "port mirroring" N/A MODE4

The DP83867 when not properly bootstrapped - especially with LED_0 pin -
can enter N/A MODE4 for "port mirroring" feature.

To provide normal operation of the PHY, one needs not only to explicitly
disable the port mirroring feature, but as well stop some IC internal
testing (which disables RGMII communication).

To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit
11 examined. When it is set, the another RESERVED bit (11) at PHYCR
(0x0010) register must be clear to disable testing mode and enable RGMII
communication.

Thorough explanation of the problem can be found at following e2e thread:
"DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) -
Linux driver"

https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit ac6e058b75be71208e98a5808453aae9a17be480)
Change-Id: I1b17b6c88e76230fde3fd1c93c3bb09ee0c2790d
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

UPSTREAM: net: phy: dp83867: Add lane swapping support in the DP83867 TI's PHY driver

This patch adds support for enabling or disabling the lane swapping (called
"port mirroring" in PHY's CFG4 register) feature of the DP83867 TI's PHY
device.

One use case is when bootstrap configuration enables this feature (because
of e.g. LED_0 wrong wiring) so then one needs to disable it in software
(at u-boot/Linux).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit fc6d39c39581f3c12c95f166ce95ef8beb2047e8)
Change-Id: Iea19a3e02a5072e5b3ab2b4ee33befd5805100e2
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

UPSTREAM: net: phy: dp83867: fix irq generation

For proper IRQ generation by DP83867 phy the INT/PWDN pin has to be
programmed as an interrupt output instead of a Powerdown input in
Configuration Register 3 (CFG3), Address 0x001E, bit 7 INT_OE = 1. The
current driver doesn't do this and as result IRQs will not be generated by
DP83867 phy even if they are properly configured in DT.

Hence, fix IRQ generation by properly configuring CFG3.INT_OE bit and
ensure that Link Status Change (LINK_STATUS_CHNG_INT) and Auto-Negotiation
Complete (AUTONEG_COMP_INT) interrupt are enabled. After this the DP83867
driver will work properly in interrupt enabled mode.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 5ca7d1ca77dc23934504b95a96d2660d345f83c2)
Change-Id: Ic4fd8e84a2e41f217850230699e00f603ea3f086
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>