ARM: dts: rockchip: fix i2s&spdif interrupts on rk3288

These must be translated from the values in the TRM by subtracting 32,
which has not been done.

Change-Id: I8d26bd63d39009b60b310e7ccbcd5de814863861
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>

ARM64: dts: rk3399-evb: add gsl3673 node for rk3399-evb

Change-Id: I8b8232dd280a436e330292794b36f617ae3c0a9d
Signed-off-by: buluess.li <buluess.li@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

mfd: fusb302: change to host when connect type-c to standard-a cable

When connected with type-c to standard-a cable, inno phy will
generate an interrupt before setting the state of typec to host,
which result in detecting of battery charger. This patch change
the state to host before interrupt happen.

Change-Id: I6a2e15c264bd6729c3b8d23af23ad15145559b20
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>

bluetooth: rfkill-bt: enalbe 32K for ap6356

Change-Id: I71a14f38ab1d46bbf3bfc991140a20d8c6a27eec
Signed-off-by: Xu Xuehui <xxh@rock-chips.com>

dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe controller

Add a binding that describes the Rockchip PCIe controller found on Rockchip
SoCs PCIe interface.

Change-Id: Ifb84320315c06759612f2b3d9b2b6ff3e1e5cb1e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>

Documentation: bindings: add dt documentation for Rockchip PCIe PHY

This patch adds a binding that describes the Rockchip PCIe PHY found
on Rockchip SoCs PCIe interface.

Change-Id: I18940e940e0c951d3e2d6bb3b2131a37727a430d
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

pwm: rockchip: Make pwm polarity to be configured correctly

If pwm polarity was configured with different values at uboot,
the enable_conf would not be configured correctly.

Change-Id: I55b9ccc262382951a8a82810f1be74ce9460f266
Signed-off-by: Zhou weixin <zwx@rock-chips.com>

driver,mpu6500: modify _RATE_DEBUG

Change-Id: Iaa1f9c099db659aa7ef9f05efb99c4279569bcf8
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

driver,mpu6500: improve readfifo

while (fifo_count == 0) && (kfifo_len(&st->timestamps) > 0) then flush fifo

Change-Id: I9b4ab975d708ee1bb02435bca933ce8f3b55e037
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

arm64: dts: rockchip: optimize clks for rk3399 dwc3

1. modify clock-names, according to Heiko's suggestion, clock names
should always be in the scope of the device block (named after what
it supplies), and clock-names are always meant from the perspective
of the individual ip-block.

2. remove unnecessary clocks, refer to rk3399 TRM, aclk_usb3 is the
parent of aclk_usb3otg0/1 and aclk_usb3_grf, and we will enable
aclk_usb3otg0/1 and aclk_usb3_grf, so don't need to enable aclk_usb3
again. In addition, the aclk_usb3_rksoc_axi_perf clk is used for usb3
performance monitor module which we don't use now, so don't need to
enable it.

Change-Id: I1d50a72d1523b8b70f1e5f388dc357807131dd7c
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

arm64: rockchip_defconfig: update by savedefconfig

Change-Id: Ic222560c0d8ea4af2e9a7a5429f2f49abe7e8a52
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM64: dts: rockchip: add pinctrl gpio config for rk3399

Change-Id: I84800a35a95d1de61e3ddce6e7db92efb24bbf59
Signed-off-by: David Wu <david.wu@rock-chips.com>

Revert "HACK: phy: rockchip-inno-usb2: disable otg phy suspend for rk3399"

This reverts commit d7d2a689d4b29796018e72eb050bc3d8c61fbf37.

Change-Id: I937498b790c048bcd49269f258bf59b1946e9bbd
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

phy: phy-rockchip-typec: fix rx eq training fail

When do Rx compliance test, PHY is in loopback mode, we
observed that Rx test failed with long cable, and it was
found that equalizer adaptation is not happening properly.
With rx_eq_training forced from PMA, the equalizer adaptation
working fine and Rx test can pass. The root cause is that
the Rx REE component will be turned off when control data
is being received by default PHY configuration. So we need
to unmask REE control data by setting REE control data mask
register, and with this patch, equalizer training will happen
based on the signal coming from controller only.

Change-Id: Ic4fca1045d92381470588c4afccff0cc7318ab4c
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

video: rockchip: vop: 3399: fix post empty when enable afbdc after resume

userspace will set several frame after vop suspend, so the kernel back
buffer will be freed and after resume vop will read a freed buffer and lead
to post empty, so we close all win before suspend, after resume vop will
display black until userspace set a new frame.

Change-Id: I6648861d2162f221e7fbf85d2361ad245e7b88aa
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: 3399: close auto gating when enable CABC

Change-Id: Iaeb99bbc1f25998361cd20fc57c97f33fa5ce63a
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: vop: 3399: add win lite supprt afbdc abgr format

Change-Id: I5709c6e06e5e3ca8bd7fe19aa970fa933b178c62
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

arm64: dts: rockchip: vr: modify battery parameters

Change-Id: If3d0c2f85ba4f6dd03e1b0436072199677e1cf77
signed-off-by: Wu Liangqing <wlq@rock-chips.com>

arm64: dts: rockchip: rk3399-vr: support fusb302 and enabled Type-c phy

Change-Id: I117832db612b44b0439a0714743a0d875a2f5897
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

arm64: dts: rockchip: rk3399-android: isp config add dsi control

Change-Id: I39b3a7a7b03d2255342599d4d8b5482c4f8ac5dc
Signed-off-by: dalon.zhang <dalon.zhang@rock-chips.com>

camera: rockchip: camsys driver 0.0x21.4

Change-Id: Ieddb355952150d170ee52a5d80d25c9642a2ec8a
Signed-off-by: dalon.zhang <dalon.zhang@rock-chips.com>

arm64: dts: rk3399-sapphire-excavator-edp: add test-power

Change-Id: Iaa8632fa7faaefcf05eab96d175deab7329143c3
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

arm64: dts: rk3399-sapphire-excavator-box: add test-power

Change-Id: I7c26c8050f27e898ae951fc118fc717cd0b10fce
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

ARM64: dts: rk3399-evb3-edp: disable gt9xx

Since edp screen couple with another type of touchscreen,
so disable gt9xx to reduce i2c errors.

Change-Id: I829ae12039ecaea44c4e0734c18a5ebcd41845f8
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

ARM64: dts: rk3399-evb-edp: remove pwm3 of vdd_center

Fix the evb-edp error voltage for vdd_center.

Change-Id: I7f60ee233820ca175aa68074c6c2ba946045303d
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

ARM: dts: rk3288: remove emmc node for miniarm

This patch remove emmc node for rk3288-miniarm board.
because the new version of the hardware does not use emmc.

Change-Id: I72914a4e570342e5b0b559b3400e0a9db8aea7eb
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>

UPSTREAM: regmap: drop cache if the bus transfer error

regmap_write
->_regmap_raw_write
-->regcache_write first and than use map->bus->write to write i2c or spi
But if the i2c or spi transfer failed, But the cache is updated, So if I use
regmap_read will get the cache data which is not the real register value.

Change-Id: Iae06edf8a2a50d2561d351a8398bd3140904630c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from
 git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git
 commit 815806e39bf6f7e7b34875d4a9609dbe76661782)

arm64: dts: rockchip: modify battery parameters for rk3399 mid

Change-Id: Ib77ce93fdd5936059a1ecdc318eebc18e031e1ae
Signed-off-by: Bin Yang <yangbin@rock-chips.com>

arm64: rockchip_defconfig: add rk818 charge config

Change-Id: Ib339cfae1035f36d81d64907f4b034bc387f85b3
Signed-off-by: Bin Yang <yangbin@rock-chips.com>

test-power: add testpower dts-config

Change-Id: Ib2c78602f604d610a648397cbf08c56cdbd77eab
Signed-off-by: Shengfei Xu <xsf@rock-chips.com>

arm64: dts: rk3399-evb: add test-power

Change-Id: I269c4c667ba313d315fa6ee9443bb07f6295127a
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

arm64: dts: rk3399-box: add test-power

Change-Id: Id06771f84b07c3b943362369269274a41cabb279
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

FROMLIST: PM / devfreq: event: remove duplicate devfreq_event_get_drvdata()

there define two devfreq_event_get_drvdata() function in devfreq-event.h
when disable CONFIG_PM_DEVFREQ_EVENT, it will lead to build fail. So
remove devfreq_event_get_drvdata() function.

Change-Id: I273e91d4aac48ae25af5ef6de2feb37944cf6e39
Signed-off-by: Lin Huang <hl@rock-chips.com>

FROMLIST: clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc

Change-Id: I638d8cd8d6a7a867d10b7595c93c674619b99c30
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

FROMLIST: clk: rockchip: add clock flag parameter when register pll

add clock flag parameter so we can pass specific clock flag
(like CLK_GET_RATE_NOCACHE etc..)to pll driver.

Change-Id: I1e076b3efa6b5da082b6e68e2e2a4c9dfd93e3d4
Signed-off-by: Heiko Stübner <heiko@sntech.de>
Signed-off-by: Lin Huang <hl@rock-chips.com>

UPSTREAM: usb: dwc2: Reorder AHBIDLE and CSFTRST in dwc2_core_reset()

According to the databook, the core soft reset should be done before
checking for AHBIDLE. The gadget version of core reset had it correct
but the hcd version did not. This fixes the hcd version.

Change-Id: I49540085036982e6c496a3b911805f0b67fa79e1
Signed-off-by: John Youn <johnyoun@synopsys.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit b8ccc593eeeacde0e6794c4dcec0a57eba7356e6)

UPSTREAM: usb: dwc2: Avoid more calls to dwc2_core_reset()

Calls to dwc2_core_reset() are currently very slow, taking at least
150ms (possibly more).  It behooves us to take as many of these calls
out as possible.

It turns out that the calls in dwc2_fs_phy_init() and dwc2_hs_phy_init()
should (as documented in the code) only be needed if we need to do a PHY
SELECT.  That means that if we see that we can avoid the PHY SELECT then
we can avoid the reset.

This patch appears to successfully bypass two resets (one per USB
device) on rk3288-based ARM Chromebooks.

Change-Id: If9f7275d61af6fd8558124ff9ebc7c3622c1f4a3
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit 7d56cc2620f523eba7a831daa22186c8ae5bbdfe)

UPSTREAM: usb: dwc2: reduce dwc2 driver probe time

I found that the probe function of dwc2 driver takes much time
when kernel boot up. There are many long delays in the probe
function these take almost 1 second.

This patch trying to reduce unnecessary delay time.

In dwc2_core_reset() I see it use two at least 20ms delays to
wait AHB idle and core soft reset, but dwc2 data book said that
dwc2 core soft reset and AHB idle just need a few clocks (I think
it refers to AHB clock, and AHB clock run at 150MHz in my RK3288
board), so 20ms is too long, delay 1us for wait AHB idle and soft
reset is enough.

And in dwc2_get_hwparams() it takes 150ms to wait ForceHostMode
and ForceDeviceMode valid but in data book it said software must
wait at least 25ms before the change to take effect, so I reduce
this time to 25ms~50ms. By the way, is there any state bit show
that the force mode take effect ? Could we poll curmod bit for
figuring out if the change take effect ?

It seems that usleep_range() at boot time will pick the longest
value in the range. In dwc2_core_reset() there is a very long
delay takes 200ms, and this function run twice when probe, could
any one tell me is this delay time resonable ?

I have tried this patch in my RK3288-evb board. It works well.

Change-Id: I1f42ab6b6851f0721bf93d516bee895ebcdd994f
Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit 20bde643434d541bc5f662c5836a05e9e276eca3)

UPSTREAM: usb: dwc2: Speed dwc2_get_hwparams() on some host-only ports

On some host-only DWC2 ports (like the one in rk3288) when we set
GUSBCFG_FORCEHOSTMODE in GUSBCFG and then read back, we don't see the
bit set.  Presumably that's because the port is always forced to HOST
mode so there's no reason to implement these status bits.

Since we know dwc2_core_reset() is always called before
dwc2_get_hwparams() and we know dwc2_core_reset() should have set
GUSBCFG_FORCEHOSTMODE whenever hsotg->dr_mode == USB_DR_MODE_HOST, we
can just check hsotg->dr_mode to decide that we can skip the delays in
dwc2_get_hwparams().

Change-Id: I912ac2dd5e0ff3f8c12b8263ce268296bbed315f
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit f619473140df4e1a10f4c10f693d214807ebdb03)

UPSTREAM: usb: dwc2: Avoid double-reset at boot time

In (usb: dwc2: reset dwc2 core before dwc2_get_hwparams()) we added an
extra reset to the probe path for the dwc2 USB controllers.  This
allowed proper detection of parameters even if the firmware had already
used the USB part.

Unfortunately, this extra reset is quite slow and is affecting boot
speed.  We can avoid the double-reset by skipping the extra reset that
would happen just after the one we added.  Logic that explains why this
is safe:

* As of the CL mentioned above, we now always call dwc2_core_reset() in
  dwc2_driver_probe() before dwc2_hcd_init().

* The only caller of dwc2_hcd_init() is dwc2_driver_probe(), so we're
  guaranteed that dwc2_core_reset() was called before dwc2_hdc_init().

* dwc2_hdc_init() is the only caller that passes an irq other than -1 to
  dwc2_core_init().  Thus if dwc2_core_init() is called with an irq
  other than -1 we're guaranteed that dwc2_core_reset was called before
  dwc2_core_init().

...this allows us to remove the dwc2_core_reset() in dwc2_core_init() if
irq is not < 0.

Note that since "irq" wasn't used in the function dwc2_core_init()
anyway and since select_phy was always set at exactly the same times we
could avoid the reset, we remove "irq" and rename "select_phy" to
"initial_setup" and adjust the callers accordingly.

Change-Id: Id3b085ddc9d35baca140fc8a502fca74dcfd01b5
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit 0fe239bc190453fe82252c6d41a74e685730cd93)

UPSTREAM: usb: dwc2: reset dwc2 core before dwc2_get_hwparams()

We initiate dwc2 usb controller in BIOS, dwc2_core_reset() should
be called before dwc2_get_hwparams() to reset core registers to
default value. Without this the FIFO setting might be incorrect
because calculating FIFO size need power-on value of
GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers.

This patch could avoid warnning massage like in rk3288 platform:
[    2.074764] dwc2 ff580000.usb: 256 invalid for
host_perio_tx_fifo_size. Check HW configuration.

Change-Id: Iab346c005c9f3ea940f4070f3e433e0c7ea89087
Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit cebfdbf329ae929ccb71632888a7c2100c3d1eeb)

UPSTREAM: usb: dwc2: Restore GUSBCFG in dwc2_get_hwparams()

Previously dwc2_get_hwparams() was changing GUSBCFG and not putting it
back the way it was (specifically it set and cleared FORCEHOSTMODE).
Since we want to move dwc2_core_reset() _before_ dwc2_get_hwparams() we
should make sure dwc2_get_hwparams() isn't messing with things in a
permanent way.

Since we're now looking at GUSBCFG, it's obvious that we shouldn't need
all the extra delays if FORCEHOSTMODE was already set.  This will avoid
some delays for any ports that have forced host mode.

Change-Id: I514aaaf77a7ee3f0871efb15e659b93b9717c5f1
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit 991824677fe0a555394d8093b64647dbd08b89b0)

arm64: configs: add Rockchip linux default configure file

This configure file is created for Linux Opensource project, and this
file is based on:
- arch/arm/configs/rockchip_linux_defconfig

Only have some light changes:

+ CONFIG_ARMV8_DEPRECATED=y
+ CONFIG_COMPAT=y
+ CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+ CONFIG_CPU_IDLE=y
+ CONFIG_ARM_CPUIDLE=y

+ CONFIG_REGULATOR=y
+ CONFIG_REGULATOR_DEBUG=y

+ CONFIG_MMC_BLOCK_MINORS=32
+ CONFIG_MMC_SDHCI_OF_ARASAN=y
+ CONFIG_PHY_ROCKCHIP_EMMC=y

+ CONFIG_FIQ_DEBUGGER=y
+ CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
+ CONFIG_FIQ_DEBUGGER_CONSOLE=y
+ CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y

- CONFIG_RT2X00=y
- CONFIG_RT2800USB=y

- CONFIG_VIDEO_ROCKCHIP_VPU=y

- CONFIG_MALI400=y
- CONFIG_MALI_SHARED_INTERRUPTS=y
- CONFIG_MALI_DT=y

Change-Id: I4557ca060647c88fd2de2d1e736f9cb0048e3c9a
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

arm64: dts: rockchip: add RK3399 Excavator Board for Linux Opensource

Add Excavator board dts file for Linux Opensource project

Change-Id: I5e5375814d2a4cfa8ae613115b2cbced47cd56ab
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

arm64: dts: rockchip: disabled the dw-hdmi-audio by default for Sapphire board

The dw-hdmi-audio driver could only work on FB dw-hdmi driver, we can't
use it on DRM display sub-system. So I think it's better to disable the
dw-hdmi-audio by default for Sapphire board, but enable this device node
for excavator-edp and excavator-box boards.

Change-Id: I8c2639d535510f1092a3da02e008986394608998
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

arm64: dts: rockchip: split the backlight device node to Sapphire SoC board

Backlight is the common device node, this would help to reduce
dumplicate code.

Change-Id: If0ee83f0bf929c242ec6dde3808a680f28e408ed
Signed-off-by: Yakir Yang <ykk@rock-chips.com>

arm64: dts: rk3399-box: and 32.768K clk node for BT

Change-Id: I7288d8e7a20aba17dca9cdb699da24af745e5567
Signed-off-by: Xu Xuehui <xxh@rock-chips.com>

arm64: dts: rockchip: use extcon for usb2/usb3 on rk3399 mid board

Change-Id: I883fb6da8e9b136e6d94213a6675b8de9e131380
Signed-off-by: Bin Yang <yangbin@rock-chips.com>

arm64: dts: rockchip: enable Type-C phy for rk3399 mid

Change-Id: I8973725588becb6620ff92da38f09e734e3fc320
Signed-off-by: Bin Yang <yangbin@rock-chips.com>

arm64: dts: rockchip: support fusb302 for rk3399 mid

Change-Id: I6eac543d9791e55d3b11b5367ac336c9c2f27296
Signed-off-by: Bin Yang <yangbin@rock-chips.com>

FROMLIST: mmc: core: fall back host->f_init if failing to init mmc card after resume

We observed the failure of initializing card after resume
accidentally. It's hard to reproduce but we did get report from
the suspend/resume test of our RK3399 mp test farm . Unfortunately,
we still fail to figure out what was going wrong at that time.
Also we can't achieve it by retrying the host->f_init without falling
back it. But this patch will solve the problem as we could add some log
there and see that we resume the mmc card successfully after falling
back the host->f_init. There is no obvious side effect found, so it seems
this patch will improve the stability.

[   93.405085] mmc1: unexpected status 0x800900 after switch
[   93.408474] mmc1: switch to bus width 1 failed
[   93.408482] mmc1: mmc_select_hs200 failed, error -110
[   93.408492] mmc1: error -110 during resume (card was removed?)
[   93.408705] PM: resume of devices complete after 213.453 msecs

Change-Id: I5b24cb84a223394392450a1f10d8bbacb9e1006e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

FROMLIST: mmc: core: move freqs table into core.h

We will reuse it outside the core.c file, so let's
move it to the header file.

Change-Id: Ibc40268d104d503603d59911d71157fcee0e5196
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

FROMLIST: mmc: sdhci: Do not allow tuning procedure to be interrupted

wait_event_interruptible_timeout() will return early if the blocked
process receives a signal, causing the driver to abort the tuning
procedure and possibly leaving the controller in a bad state.  Since the
tuning command is expected to complete quickly (<50ms) and we've set a
timeout, use wait_event_timeout() instead.

Change-Id: Ibd1c5e8076c5fde4b4e9c4ebb0a2733c8d2d4eda
Signed-off-by: Christopher Freeman <cfreeman@nvidia.com>
Tested-by: Robert Foss <robert.foss@collabora.com>
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

mmc: sdhci-of-arasan: wakeup genpd when being in suspend

Let's keep genpd for sdhci alive while entering deep
sleep which gte me out of yapping around.

Change-Id: I0da20b417621d277745bafd53d1ee461aae72e11
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

drivers,inv_mpu: fix reg name err

Change-Id: I965cdb614b2ba28bb8b61af561799fd237d7e50d
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

arm64: dts: rockchip: use extcon for usb2/usb3 on rk3399 evb/box

Change-Id: I582381af1dfc5c7bb06736d3a92d2636b1523863
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

arm64: dts: rockchip: change dr_mode for rk3399 dwc3

The DesignWare USB3 integrated in rockchip SoCs is a configurable
IP Core which can be instantiated as Dual-Role Device (DRD), Host
Only (XHCI) and Peripheral Only configurations. For rk3399, it has
two DWC3 controllers, we set DRD for DWC3_0 and Host only for DWC3_1
by default.

Change-Id: Ia0063e04e48770d8d0ec7ec86cb621c5e9979fb9
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

arm64: dts: rockchip: add usb3 phy for rk3399 dwc3

For now, we have enabled Type-C phy, so we can add
usb3 phy which integrated in Type-C phy for rk3399
dwc3, and support super speed.

Change-Id: I3da984e4f35b35d46e0b84755bcc23deaf97d18f
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

arm64: dts: rockchip: enable Type-C phy for rk3399 evb/box

Change-Id: Idb2f919e008c37aa030c114c9a11df2d69126e99
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

arm64: dts: rockchip: add usb3 controller reset for rk3399

We can assert the reset to keep the whole USB3 Controller
in resetting to hold pipe power state in P2 before
initializing Type-C PHY.

Change-Id: Ibb5716bac645ae01ee27fd019a3dfcbd3c0ffd84
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

arm64: rockchip_cros_defconfig: enable rockchip Type-C phy

Change-Id: I1fe575bd027d4843c4e5c21a4fef5bdb6a9b417a
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

arm64: rockchip_defconfig: enable rockchip Type-C phy

Change-Id: Ifef876af8f54019d7a72a3953a0b90535df23242
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

usb: dwc3: fix PM resume error for rockchip platforms

We enable PM runtime auto suspend on rockchip platforms (e.g. rk3399),
it allows DWC3 controller to enter runtime suspend if usb cable detached.
So we don't need to do anything in dwc3_suspend() and dwc3_resume()
which duplicated the same operations as dwc3_runtime_suspend() and
dwc3_runtime_resume().

And if DWC3 controller works on HOST mode, we can't do runtime resume
DWC3 gadget.

Change-Id: I63e734f51b05274251d8a88a664eee768568eb7b
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

phy: rockchip-inno-usb2: don't cancel otg_sm_work when phy exit

The otg_sm_work is a OTG state machine delay work. It will hold
a wake lock if SDP cable or CDP cable is attached, and release
the wake lock if cable dettached. If usb controller(e.g. DWC3)
call phy exit When USB cable is dettached and cancel otg_sm_work,
it will cause the usb phy keeping hold of wake lock.

Change-Id: Ie6a89e481b8d4999a996083709bacc5be901805a
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

usb: dwc3: add rockchip specific glue layer

Add rockchip specific glue layer to support USB3 Peripheral mode
and Host mode on rockchip platforms (e.g. rk3399).

The DesignWare USB3 integrated in rockchip SoCs is a configurable
IP Core which can be instantiated as Dual-Role Device (DRD), Host
Only (XHCI) and Peripheral Only configurations.

We use extcon notifier to manage usb cable detection and mode switch.
Enable DWC3 PM runtime auto suspend to allow core enter runtime_suspend
if USB cable is dettached. For host mode, it requires to keep whole
DWC3 controller in reset state to hold pipe power state in P2 before
initializing PHY. And it need to reconfigure USB PHY interface of DWC3
core after deassert DWC3 controller reset.

The current driver supports Host only and Peripheral Only well, for
now, we will add support for OTG after we have it all stabilized.

Change-Id: I821dd19eedec73e6517f0cca184f939a9f313904
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

UPSTREAM: xhci: fix platform quirks overwrite regression in 4.7-rc1

commit b1c127ae990b ("usb: host: xhci: plat: make use of new methods in
xhci_plat_priv") sets xhci->quirks before calling xhci_gen_setup(), which
will overwrite them.

Don't overwite the quirks, just add the new ones

Fixes: b1c127ae990b ("usb: host: xhci: plat: make use of new methods in xhci_plat_priv")
Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Change-Id: I7751ccaa1f3c8000ad0d47f9fba84084b2db96da
Cc: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 757de492f2d5711d4f5b386eb9bdd5cdc99eb30e)

arm64: dts: rockchip: modify dwc3 properties for rk3399

We have merged dwc3 driver from upstream, and some properties
need to be modified according to upstream coding style.

Change-Id: I4f8c4b23a941932a08eb29a0282dfb0903193c8a
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

usb: dwc3: add a quirk xhci_slow_suspend_quirk

On some xHCI controllers (e.g. Rockchip SoCs), which are
integrated in DWC3 IP, need an extraordinary delay to wait
for xHCI enter the Halted state(i.e. HCH in the USBSTS
register is '1'), especially if DWC3 is in DRD mode.

Change-Id: I67c84d4768df95f7616d6716a77cf743e4334122
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

FROMLIST: usb: dwc3: rockchip: add devicetree bindings documentation

This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.

It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).

Change-Id: I8b45a43a1a2c0399188d601c794015b4305c4795
Signed-off-by: William Wu <william.wu@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

FROMLIST: usb: dwc3: add dis_del_phy_power_chg_quirk

Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.

Change-Id: I84ce14c328aa27c5000cf76c44cbdc1ea7a926b9
Signed-off-by: William Wu <william.wu@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

FROMLIST: usb: dwc3: make usb2 phy utmi interface configurable

Support to configure the UTMI+ PHY with an 8- or 16-bit
interface via DT. The UTMI+ PHY interface is a hardware
capability, and it's platform dependent. Normally, the
PHYIF can be configured during coreconsultant.

But for some specific USB cores(e.g. rk3399 SoC DWC3),
the default PHYIF configuration value is false, so we
need to reconfigure it by software.

Change-Id: I5c5a44dcd9ef4c3b8f2b722cd066819a2983fcfc
Signed-off-by: William Wu <william.wu@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

FROMLIST: usb: dwc3: add dis_u2_freeclk_exists_quirk

Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.

Change-Id: I1b93715501f54231fc4dccebba2163d3484b2be6
Signed-off-by: William Wu <william.wu@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>

UPSTREAM: ARM: dts: rockchip: add eFuse config of rk3288 SoC

This patch add the eFuse dt config of rk3288 SoC.

Change-Id: Ib0b316946ed362d4e4adb4a82448947bfc2c0e5b
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit 8818555964eed0010044c4d85f096452b14eb8b5)

UPSTREAM: clk: rockchip: Add the clock ids of rk3288 eFuses

Add clock-ids for the two efuse blocks of the rk3288.

Change-Id: I6cc8caf49e2f5aa3c0434a2f287b0fedbda190dc
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit b457c1e440fc8580563ed7a5c3156573ecaf3dfc)

drm/panel: keep mute when panel has no device-tree timing

Since commit (f6972eb FROMLIST: drm/panel: add of display
timing support), when panel has no device-tree timing, would always
get noise message:
[    8.742157] /lvds_panel: could not find display-timings node
[    8.747878] /lvds_panel: no timings specified

Change-Id: I9104b3017faa837807a09c21d0f948e499827ad9
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

net: wireless: rockchip_wlan: add rtl8188eu support

update rtl8188eu wifi driver to version v4.3.24_16705.20160509

Change-Id: Id28e185a24eb94877cb10cfcf54b63e04da75ca1
Signed-off-by: zzc <zzc@rock-chips.com>

phy: rockchip-inno-usb2: add SDP detect retry

If detect a SDP charger type, we retry twice more to avoid
DCP falsely identified as SDP due to hardware signal error.

Change-Id: I1bf7bd076cd7767938f6944f1156daa7e64870e4
Signed-off-by: Feng Mingli <fml@rock-chips.com>

ARM64: configs: rockchip_defconfig: enable gsl3673

Change-Id: Id9ae1a78fb0f4ecf1d7561dcc1320362bd181bb1
Signed-off-by: buluess.li <buluess.li@rock-chips.com>

input: touchscreen: add touch screen of gsl3673 for rk3399-evb

Change-Id: I16a4e44c75a16aefa153b002bce83392522c7d30
Signed-off-by: buluess.li <buluess.li@rock-chips.com>

UPSTREAM: Documentation: dt: dwc3: Add snps,dis_rxdet_inp3_quirk property

Add snps,dis_rxdet_inp3_quirk property which disables receiver detection
in PHY P3 power state.

Change-Id: I434f10041f5ff3f7d81b14ba4d6e5bcdb47b1ad7
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 2c0b98ff29a7452edbbdc503857b74cfaa536808)

UPSTREAM: usb: dwc3: st: Use explicit reset_control_get_exclusive() API

We're making all reset line users specify whether their lines are
shared with other IP or they operate them exclusively.  In this case
the line is exclusively used only by this IP, so use the *_exclusive()
API accordingly.

Change-Id: I94d96af42ac63cd0c6445930f0458d36ec92f0e4
Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 5baaf3b9efe127d239038de9219d381f4d882b26)

UPSTREAM: usb: dwc3: st: Inform the reset framework that our reset line may be shared

On the STiH410 B2120 development board the MiPHY28lp shares its reset
line with the Synopsys DWC3 SuperSpeed (SS) USB 3.0 Dual-Role-Device
(DRD).  New functionality in the reset subsystems forces consumers to
be explicit when requesting shared/exclusive reset lines.

Change-Id: Id9ff5e3beadada3aeb5dc8a6085d9bd86255f45c
Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 002f17bc54ff4005260d8e6e6700de97f5b25679)

UPSTREAM: dwc3: gadget: Implement the suspend entry event handler

It had changed to be suspend event for BIT6 in DEVT register from
version 2.30a and above. Thus this patch introduces one suspend
event handler to handle the suspend event.

Change-Id: I62751ee39a2ff13c1359350a8f6c43c14aa4ea12
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 72704f876f50b00f08d41d4b13d5a5d11262254f)

UPSTREAM: usb: dwc3: core: cleanup IRQ resources

Implementations might use different IRQs for
host, gadget so use named interrupt resources
to allow device tree to specify the interrupts.

Following are the interrupt names

Peripheral Interrupt - peripheral
HOST Interrupt - host

Maintain backward compatibility for a single named
interrupt ("dwc3_usb3") for all interrupts as well as
unnamed interrupt at index 0 for all interrupts.

As platform_get_irq() variants are used, tackle
the -EPROBE_DEFER case as well.

Change-Id: Idb47d85ceee3353a219e4a9793942c7e92a6a6eb
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
(cherry picked from commit 9522def40065194aa75b0a7b7e1ff5b8e2014724)

Conflicts:
drivers/usb/dwc3/core.c

UPSTREAM: usb: dwc3: gadget: Add the suspend state checking when stopping gadget

It will be crash to stop gadget when the dwc3 device had been into suspend
state, thus we need to check if the dwc3 device had been into suspend state
when UDC try to stop gadget.

Change-Id: I1a49d4c52131ef4b4357d4a12b5da55e8127d750
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit da1410be21bfedd16740aee6d772e669cf4e852f)

UPSTREAM: usb: dwc3: gadget: issue ENDTRANSFER conditional on resource_index

Because of recent changes to transfer handling on
DWC3, we will not get XferComplete unless we
completely fill up our TRB ring. This means that we
might get a Reset or Disconnect without getting a
XferComplete first.

In order to correctly release our allocated Transfer
Resource, we must issue ENDTRANSFER command whenever
dep->resource_index is valid.

Change-Id: I6f78a239e26d754c2472f06789f820d42261d31d
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 0e146028eebf989e86d3fe9385b76434e954c84e)

UPSTREAM: usb: dwc3: fix runtime PM in error path

If there is a failure after pm_runtime_enable/get_sync()
we need to call pm_runtime_disable/put_sync().

Otherwise it will lead to an unbalanced pm_runtime_enable() on the
subsequent probe if the earlier probe bailed out due to -EPROBE_DEFER.

pm_runtime_get_sync() can fail as well so deal with that case too.

Change-Id: Ia8af31867e996eeee4b0a18e34303280b661a86c
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 328082376aea6016b63bca1e5c067a9539f9e8c9)

UPSTREAM: usb: dwc3: gadget: simplify run_stop() break condition

it's clear now that when is_on=true, we must loop
until DWC3_DSTS_DEVCTRLHLT clears; while when
is_on=false we must loop until DWC3_DSTS_DEVCTRLHLT
gets set.

Instead of adding actual if() statements, we can
rely on XOR operation to evaluate to true only when
the above conditions apply. Then, we can move the
break condition back to the while() statement
together with our timeout check and the resulting
code is very compact and simpler to read.

Change-Id: Id540c7422cd1d7e00120c26353d99e2e9888ea26
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit b6d4e16e831376b676edb3463f2bdaa192e5f7be)

UPSTREAM: usb: dwc3: gadget: avoid while(1) in run_stop()

instead of looping forever and forcing a return if
timeout reaches zero, we can just use timeout and
loop's break condition directly.

Change-Id: Ibfbe125651d117cab717c5b0b73ef534ced79a67
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit f2df679b6c556fd3b0b7ffafea170f1679086455)

UPSTREAM: usb: dwc3: gadget: remove udelay() from run_stop()

testing shows that udelay() is unnecessary as
controller reaches Halted state almost
instantenously as can be seen by our timeout
variable never actually decrementing.

Change-Id: I39aa43a4d26c4e5bf7c2c49569bb5ab0c662e718
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit d807bdd02845d53047346a4ba6d8934597fba6d6)

UPSTREAM: usb: dwc3: core: fixup dr_mode fallback selection

We shouldn't change a host-only dwc3 to gadget-only
if driver is built as gadget-only. Fix that up here.

Change-Id: I7ff835a565e1d4d06e142f3fa9990ce96e85556e
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 5f82279a0c76825bfc6f5fa213ff82c932161462)

UPSTREAM: usb: dwc3: pci: add dr-mode for Intel dwc3

It's know that Intel's SoCs' dwc3 integration is
peripheral-only since Intel implements its own
portmux for role-swapping. In order to prevent dwc3
from ever registering and XHCI platform_device,
let's just set dr-mode to peripheral-only on Intel
SoCs.

Change-Id: Ic7a57ae89a4ea2a2f04a1aff581d728add15a034
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit e6fe66fe08cdf9c5d0eb6a6e209621f74f7ee60b)

UPSTREAM: usb: dwc3: gadget: rename 'ignore' argument to 'modify'

'modify' is what the current action is called. Let's
rename it so it matches databook. While at that,
also make sure to add support 'init' action too.

Change-Id: I9fb3b445a7f8dd6acb369407eddf6d7d0994543d
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 21e64bf20df5e120b37c403b46395d4f0c5d8e86)

UPSTREAM: usb: dwc3: gadget: decrement trbs_left for each sg entry

If we don't, we will overwrite valid TRBs.

Change-Id: I8076fa857b9ae016617d58836de3d9dcf5be9e4c
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit d6dc2e76a860d6be0129daae43e5f12461531d20)

UPSTREAM: usb: dwc3: gadget: start Bulk endpoints more frequently

Now we can try to issue Update Transfer every time
gadget driver queues a new request. This will make
sure we keep controller's queue busy for as long as
possible.

Change-Id: Id0418f2b4930e442d3bae7be87270100c0b347f5
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit ba62c09d5cc240e55eb39e92d88f1036bb1d9221)

UPSTREAM: usb: dwc3: gadget: disable XFER_NOT_READY

We don't need this IRQ anymore for interrupt or bulk
endpoints.

Change-Id: I223ef88f807d7265a00d8d7be480320722d7ef88
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 13fa2e69b1dda31bddb11fe61f250b9415885ead)

UPSTREAM: usb: dwc3: gadget: use allocated/queued reqs for LST bit

Let's only set LST bit when we run out of space in
our TRB ring. For all other cases, we keep LST bit
unset which will prevent constant allocation and
deallocation of endpoint transfer resources.

Change-Id: Ia846ea0e3540c151d04488f239eb0f847c85b1fd
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 55a0237f8f47957163125e20ee9260538c5c341c)

UPSTREAM: usb: dwc3: gadget: halt and stop based HWO bit

Instead of relying on empty list of queued requests,
let's rely on the fact that we have a TRB being
processed right now.

Change-Id: I06075d3aaf695f74946ebd269746a240be7e51c0
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 69450c4dc164d9ecbc0b54cb47a2ec80cde45da4)

UPSTREAM: usb: dwc3: gadget: keep track of allocated and queued reqs

We will be using this information to change how we
figure out when we need LST bit. For now, just
update our counters.

Change-Id: I3c2019ef6649d47b89dbf1c16ef2eed6012442c6
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit 68d34c8a744d16ae449577a71c67b19a4b1100d0)

UPSTREAM: usb: dwc3: gadget: update transfer needs transfer resource

According to SNPS databook, we need to pass transfer
resource on update transfer command, let's do it.

Change-Id: I972007913ca2511f76e565a624721300c9fb754e
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
(cherry picked from commit b6b1c6db4c7f04ffe3fd411baa9df31f4dd355dd)