Bradley Smith [Wed, 9 Apr 2014 14:44:22 +0000 (14:44 +0000)]
[ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205890
91177308-0d34-0410-b5e6-
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Bradley Smith [Wed, 9 Apr 2014 14:44:18 +0000 (14:44 +0000)]
[ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a dumb alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205889
91177308-0d34-0410-b5e6-
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Bradley Smith [Wed, 9 Apr 2014 14:44:12 +0000 (14:44 +0000)]
[ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all labels types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205888
91177308-0d34-0410-b5e6-
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Bradley Smith [Wed, 9 Apr 2014 14:44:07 +0000 (14:44 +0000)]
[ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205887
91177308-0d34-0410-b5e6-
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Bradley Smith [Wed, 9 Apr 2014 14:44:03 +0000 (14:44 +0000)]
[ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205886
91177308-0d34-0410-b5e6-
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Bradley Smith [Wed, 9 Apr 2014 14:43:59 +0000 (14:43 +0000)]
[ARM64] Rename LR to the UAL-compliant 'X30'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205885
91177308-0d34-0410-b5e6-
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Bradley Smith [Wed, 9 Apr 2014 14:43:50 +0000 (14:43 +0000)]
[ARM64] Rename FP to the UAL-compliant 'X29'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205884
91177308-0d34-0410-b5e6-
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Bradley Smith [Wed, 9 Apr 2014 14:43:40 +0000 (14:43 +0000)]
[ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be zero but should be decoded/disassembled with any value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205883
91177308-0d34-0410-b5e6-
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Bradley Smith [Wed, 9 Apr 2014 14:43:35 +0000 (14:43 +0000)]
[ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205882
91177308-0d34-0410-b5e6-
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Bradley Smith [Wed, 9 Apr 2014 14:43:31 +0000 (14:43 +0000)]
[ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top bit of their immediate clear.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205881
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Bradley Smith [Wed, 9 Apr 2014 14:43:27 +0000 (14:43 +0000)]
[ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205880
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Bradley Smith [Wed, 9 Apr 2014 14:43:24 +0000 (14:43 +0000)]
[ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205879
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Bradley Smith [Wed, 9 Apr 2014 14:43:20 +0000 (14:43 +0000)]
[ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205878
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Bradley Smith [Wed, 9 Apr 2014 14:43:15 +0000 (14:43 +0000)]
[ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205877
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Bradley Smith [Wed, 9 Apr 2014 14:43:11 +0000 (14:43 +0000)]
[ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205876
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Bradley Smith [Wed, 9 Apr 2014 14:43:06 +0000 (14:43 +0000)]
[ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205875
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Bradley Smith [Wed, 9 Apr 2014 14:43:01 +0000 (14:43 +0000)]
[ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205874
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Bradley Smith [Wed, 9 Apr 2014 14:42:56 +0000 (14:42 +0000)]
[ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205873
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Bradley Smith [Wed, 9 Apr 2014 14:42:53 +0000 (14:42 +0000)]
[ARM64] Remove PrefetchOp and use ARM64PRFM instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205872
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Bradley Smith [Wed, 9 Apr 2014 14:42:49 +0000 (14:42 +0000)]
[ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205871
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Bradley Smith [Wed, 9 Apr 2014 14:42:45 +0000 (14:42 +0000)]
[ARM64] Remove ARM64SYS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205870
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Bradley Smith [Wed, 9 Apr 2014 14:42:42 +0000 (14:42 +0000)]
[ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205869
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Bradley Smith [Wed, 9 Apr 2014 14:42:36 +0000 (14:42 +0000)]
[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205868
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Bradley Smith [Wed, 9 Apr 2014 14:42:27 +0000 (14:42 +0000)]
[ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205867
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Bradley Smith [Wed, 9 Apr 2014 14:42:16 +0000 (14:42 +0000)]
[ARM64] Copy the named immediate operand mapping logic and enums from AArch64. AArch64's named immediate mapping and parsing is much more advanced than ARM64's. No functionality change - they're currently living side by side while I switch uses over.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205866
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Bradley Smith [Wed, 9 Apr 2014 14:42:11 +0000 (14:42 +0000)]
[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205865
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Bradley Smith [Wed, 9 Apr 2014 14:42:07 +0000 (14:42 +0000)]
[ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205864
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Bradley Smith [Wed, 9 Apr 2014 14:42:01 +0000 (14:42 +0000)]
[ARM64] Add missing 1Q -> 1q vector kind alias
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205863
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Bradley Smith [Wed, 9 Apr 2014 14:41:58 +0000 (14:41 +0000)]
[ARM64] Add parsing for vector lists such as {v0.8b-v3.8b}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205862
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Bradley Smith [Wed, 9 Apr 2014 14:41:53 +0000 (14:41 +0000)]
[ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather than UXTX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205861
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Bradley Smith [Wed, 9 Apr 2014 14:41:49 +0000 (14:41 +0000)]
[ARM64] STRHro and STRBro were not being decoded at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205860
91177308-0d34-0410-b5e6-
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Bradley Smith [Wed, 9 Apr 2014 14:41:45 +0000 (14:41 +0000)]
[ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205859
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Bradley Smith [Wed, 9 Apr 2014 14:41:38 +0000 (14:41 +0000)]
[ARM64] Register-offset loads and stores with the 'option' field equal to 00x or 10x are undefined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205858
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Filipe Cabecinhas [Wed, 9 Apr 2014 14:35:17 +0000 (14:35 +0000)]
Revert "YAMLIO: Encode ambiguous hex strings explicitly"
This reverts commit r205839.
It broke several tests in lld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205857
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Arnold Schwaighofer [Wed, 9 Apr 2014 14:20:47 +0000 (14:20 +0000)]
SLPVectorizer: Only vectorize intrinsics whose operands are widened equally
The vectorizer only knows how to vectorize intrinics by widening all operands by
the same factor.
Patch by Tyler Nowicki!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205855
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Elena Demikhovsky [Wed, 9 Apr 2014 12:37:50 +0000 (12:37 +0000)]
AVX-512: insert element to mask vector; store i1 data
Implemented INSERT_VECTOR_ELT operation for v16i1 and v8i1 vectors;
Implemented "store" for i1 type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205850
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Viktor Kutuzov [Wed, 9 Apr 2014 11:43:34 +0000 (11:43 +0000)]
Add support for building LLVM on FreeBSD 9.2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205847
91177308-0d34-0410-b5e6-
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Daniel Sanders [Wed, 9 Apr 2014 09:56:43 +0000 (09:56 +0000)]
Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable-no-nans-fp-math
Summary:
They behave in accordance with the Has2008 and ABS2008 configuration bits of the processor which are used to select between the 1985 and 2008 versions of IEEE 754. In 1985 mode, these instructions are arithmetic (i.e. they raise invalid operation exceptions when given NaN), in 2008 mode they are non-arithmetic (i.e. they are copies).
nmadd.[ds], and nmsub.[ds] are still subject to -enable-no-nans-fp-math because the ISA spec does not explicitly state that they obey Has2008 and ABS2008.
Fixed the issue with the previous version of this patch (r205628). A pre-existing 'let Predicate =' statement was removing some predicates that were necessary for FP64 to behave correctly.
Reviewers: matheusalmeida
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3274
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205844
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David Majnemer [Wed, 9 Apr 2014 07:56:27 +0000 (07:56 +0000)]
YAMLIO: Encode ambiguous hex strings explicitly
YAMLIO would turn a BinaryRef into the string
0000000004000000.
However, the leading zero causes parsers to interpret it as being an
octal number instead of a hexadecimal one.
Instead, escape such strings as needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205839
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Tobias Grosser [Wed, 9 Apr 2014 07:53:49 +0000 (07:53 +0000)]
Delinearize: Extend informationin -analyze output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205838
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Matt Arsenault [Wed, 9 Apr 2014 07:16:16 +0000 (07:16 +0000)]
R600/SI: Match not instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205837
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Tim Northover [Wed, 9 Apr 2014 07:07:02 +0000 (07:07 +0000)]
ARM64: scalarize v1i64 mul operation
This is the second part of fixing PR19367.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205836
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Tim Northover [Wed, 9 Apr 2014 06:55:39 +0000 (06:55 +0000)]
ARM64: add pattern for <1 x i64> custom not node.
This should fix PR19367.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205835
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Saleem Abdulrasool [Wed, 9 Apr 2014 06:18:28 +0000 (06:18 +0000)]
Object: add type names for ARM/COFF relocations
Add type name mappings for the ARM COFF relocations. This allows for objdump to
provide a more useful description of relocations in disassembly inline form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205834
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Saleem Abdulrasool [Wed, 9 Apr 2014 06:18:26 +0000 (06:18 +0000)]
ARM MC: 80 column
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205833
91177308-0d34-0410-b5e6-
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Saleem Abdulrasool [Wed, 9 Apr 2014 06:18:23 +0000 (06:18 +0000)]
ARM MC: sort source files in CMakeLists
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205832
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Craig Topper [Wed, 9 Apr 2014 06:08:46 +0000 (06:08 +0000)]
[C++11] More 'nullptr' conversion or in some cases just using a boolean check instead of comparing to nullptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205831
91177308-0d34-0410-b5e6-
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Craig Topper [Wed, 9 Apr 2014 04:50:04 +0000 (04:50 +0000)]
[C++11] Make use of 'nullptr' in TableGen library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205830
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Craig Topper [Wed, 9 Apr 2014 04:20:00 +0000 (04:20 +0000)]
[C++11] Replace some comparisons with 'nullptr' with simple boolean checks to reduce verbosity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205829
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David Majnemer [Tue, 8 Apr 2014 22:33:40 +0000 (22:33 +0000)]
WinCOFF: Emit common symbols as specified in the COFF spec
Summary:
Local common symbols were properly inserted into the .bss section.
However, putting external common symbols in the .bss section would give
them a strong definition.
Instead, encode them as undefined, external symbols who's symbol value
is equivalent to their size.
Reviewers: Bigcheese, rafael, rnk
CC: llvm-commits
Differential Revision: http://reviews.llvm.org/D3324
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205811
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Matt Arsenault [Tue, 8 Apr 2014 21:40:37 +0000 (21:40 +0000)]
Bug 19348: Check for legal ExtLoad operation before folding
(aext (zextload x)) -> (aext (truncate (*extload x)))
Patch by Stanislav Mekhanoshin!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205805
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Sebastian Pop [Tue, 8 Apr 2014 21:21:13 +0000 (21:21 +0000)]
divide by the result of the gcd
used to fail with 'Step should divide Start with no remainder.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205802
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Sebastian Pop [Tue, 8 Apr 2014 21:21:10 +0000 (21:21 +0000)]
handle special cases when findGCD returns 1
used to fail with 'Step should divide Start with no remainder.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205801
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Sebastian Pop [Tue, 8 Apr 2014 21:21:05 +0000 (21:21 +0000)]
in findGCD of multiply expr return the gcd
we used to return 1 instead of the gcd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205800
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Sean Silva [Tue, 8 Apr 2014 21:12:56 +0000 (21:12 +0000)]
[docs] VCS contains a record of authorship
No need to explicitly mention the author in the document.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205793
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Sean Silva [Tue, 8 Apr 2014 21:06:22 +0000 (21:06 +0000)]
[docs] Fix up some links to the preferred style.
:doc:`...` and :ref:`...` links help Sphinx keep track the dependencies
between documents and ensure that they are not pointing to nowhere.
Raw HTML links work just fine and are easier for people less familiar
with reST/Sphinx. They are easy to change over to the :doc:/:ref: style
after the fact so this is not a problem.
This commit doesn't fix all of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205792
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Juergen Ributzka [Tue, 8 Apr 2014 20:39:59 +0000 (20:39 +0000)]
[Constant Hoisting][ARM64] Enable constant hoisting for ARM64.
This implements the target-hooks for ARM64 to enable constant hoisting.
This fixes <rdar://problem/
14774662> and <rdar://problem/
16381500>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205791
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Duncan P. N. Exon Smith [Tue, 8 Apr 2014 19:18:56 +0000 (19:18 +0000)]
RegAlloc: Account for a variable entry block frequency
Until r197284, the entry frequency was constant -- i.e., set to 2^14.
Although current ToT still has a constant entry frequency, since r197284
that has been an implementation detail (which is soon going to change).
- r204690 made the wrong assumption for the CSRCost metric. Adjust
callee-saved register cost based on entry frequency.
- r185393 made the wrong assumption (although it was valid at the
time). Update SpillPlacement.cpp::Threshold to be relative to the
entry frequency.
Since ToT still has 2^14 entry frequency, this should have no observable
functionality change.
<rdar://problem/
14292693>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205789
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Hal Finkel [Tue, 8 Apr 2014 19:00:27 +0000 (19:00 +0000)]
[PowerPC] Don't return false from PPC::isVSLDOIShuffleMask
PPC::isVSLDOIShuffleMask should return -1, not false, when the shuffle
predicate should be false.
Noticed by inspection; no test case (yet).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205787
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Kevin Enderby [Tue, 8 Apr 2014 18:00:52 +0000 (18:00 +0000)]
Fix the ARM VLD3 (single 3-element structure to all lanes)
size 16 double-spaced registers instruction printing.
This:
vld3.16 {d0[], d2[], d4[]}, [r4]!
was being printed as:
vld3.16 {d0[], d1[], d2[]}, [r4]!
rdar://
16531387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205779
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Duncan P. N. Exon Smith [Tue, 8 Apr 2014 17:07:44 +0000 (17:07 +0000)]
Verifier: Give the right message for bad atomic loads
Talk about load (not store) on an invalid atomic load.
<rdar://problem/
16287567>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205777
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Diego Novillo [Tue, 8 Apr 2014 16:42:38 +0000 (16:42 +0000)]
Add -pass-remarks flag to 'opt'.
Summary:
This adds support in 'opt' to filter pass remarks emitted by
optimization passes. A new flag -pass-remarks specifies which
passes should emit a diagnostic when LLVMContext::emitOptimizationRemark
is invoked.
This will allow the front end to simply pass along the regular
expression from its own -Rpass flag when launching the backend.
Depends on D3227.
Reviewers: qcolombet
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D3291
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205775
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Diego Novillo [Tue, 8 Apr 2014 16:42:34 +0000 (16:42 +0000)]
Add support for optimization reports.
Summary:
This patch adds backend support for -Rpass=, which indicates the name
of the optimization pass that should emit remarks stating when it
made a transformation to the code.
Pass names are taken from their DEBUG_NAME definitions.
When emitting an optimization report diagnostic, the lack of debug
information causes the diagnostic to use "<unknown>:0:0" as the
location string.
This is the back end counterpart for
http://llvm-reviews.chandlerc.com/D3226
Reviewers: qcolombet
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D3227
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205774
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NAKAMURA Takumi [Tue, 8 Apr 2014 15:28:50 +0000 (15:28 +0000)]
X86MCAsmInfoGNUCOFF: Set PointerSize as 8 for targeting x64. It caused DW_LNE_set_address was misemitted on x64.
FIXME: I haven't investigate whether CalleeSaveStackSlotSize should be 8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205772
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Tim Northover [Tue, 8 Apr 2014 12:23:51 +0000 (12:23 +0000)]
ARM64: fix fmsub patterns which assumed accum operand was first
Confusingly, the NEON fmla instructions put the accumulator first but the
scalar versions put it at the end (like the fma lib function & LLVM's
intrinsic).
This should fix PR19345, assuming there's only one issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205758
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Richard Smith [Tue, 8 Apr 2014 10:47:04 +0000 (10:47 +0000)]
The LLVM C API shouldn't be including a file from the C++ API. Especially not a
file that it doesn't use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205755
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Elena Demikhovsky [Tue, 8 Apr 2014 07:24:02 +0000 (07:24 +0000)]
AVX-512: Added fp_to_uint and uint_to_fp patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205754
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Andrew Trick [Tue, 8 Apr 2014 03:40:34 +0000 (03:40 +0000)]
Fix a (legacy) PassManager crash that occurs when a ModulePass
indirectly requires a function analysis.
This bug was reported by Jason Kim. He included a test case here:
http://reviews.llvm.org/D3312
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205753
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David Majnemer [Tue, 8 Apr 2014 02:15:13 +0000 (02:15 +0000)]
X86: Split the relocation selection up
Before, we would have conditional operators where one side of the
operator would be of type RelocationTypeAMD64 and the other is of type
RelocationTypeI386. GCC would noisly warn with -Wenum-compare
diagnostic.
Instead, refactor the code so it is more like the X86 ELF object writer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205752
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Jim Grosbach [Mon, 7 Apr 2014 23:47:23 +0000 (23:47 +0000)]
Tidy up comments a bit.
Punctuation, grammar, formatting, etc..
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205749
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Jim Grosbach [Mon, 7 Apr 2014 23:47:21 +0000 (23:47 +0000)]
ARM64: Range based for loop in ARM64PromoteConstant pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205748
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Jim Grosbach [Mon, 7 Apr 2014 23:14:38 +0000 (23:14 +0000)]
ARM64: Clean up file header comment a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205747
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David Majnemer [Mon, 7 Apr 2014 23:12:20 +0000 (23:12 +0000)]
obj2yaml: Use the correct relocation type for different machine types
The IO normalizer would essentially lump I386 and AMD64 relocations
together. Relocation types with the same numeric value would then get
mapped in appropriately.
For example:
IMAGE_REL_AMD64_ADDR64 and IMAGE_REL_I386_DIR16 both have a numeric
value of one. We would see IMAGE_REL_I386_DIR16 in obj2yaml conversions
of object files with a machine type of IMAGE_FILE_MACHINE_AMD64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205746
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Sean Silva [Mon, 7 Apr 2014 22:46:40 +0000 (22:46 +0000)]
[docs] Fix some links
The TableGen docs have changed structure
Patch by Tay Ray Chuan!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205744
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Sean Silva [Mon, 7 Apr 2014 22:42:53 +0000 (22:42 +0000)]
[docs] Update link title
docs/TableGen/ is not really just "fundamentals" anymore, but rather
more of a portal for all things TableGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205743
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Sean Silva [Mon, 7 Apr 2014 22:29:53 +0000 (22:29 +0000)]
[docs] Fix some Sphinx warnings that have crept in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205742
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Reed Kotler [Mon, 7 Apr 2014 22:11:40 +0000 (22:11 +0000)]
Reverting commit r205628 due to mips64 issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205741
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Andrew Trick [Mon, 7 Apr 2014 21:29:22 +0000 (21:29 +0000)]
Put a limit on ScheduleDAGSDNodes::ClusterNeighboringLoads to avoid blowing up compile time.
Fixes PR16365 - Extremely slow compilation in -O1 and -O2.
The SD scheduler has a quadratic implementation of load clustering
which absolutely blows up compile time for large blocks with constant
pool loads. The MI scheduler has a better implementation of load
clustering. However, we have not done the work yet to completely
eliminate the SD scheduler. Some benchmarks still seem to benefit from
early load clustering, although maybe by chance.
As an intermediate term fix, I just put a nice limit on the number of
DAG users to search before finding a match. With this limit there are no
binary differences in the LLVM test suite, and the PR16365 test case
does not suffer any compile time impact from this routine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205738
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Tom Stellard [Mon, 7 Apr 2014 19:45:45 +0000 (19:45 +0000)]
R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205732
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Tom Stellard [Mon, 7 Apr 2014 19:45:41 +0000 (19:45 +0000)]
R600: Match 24-bit arithmetic patterns in a Target DAGCombine
Moving these patterns from TableGen files to PerformDAGCombine()
should allow us to generate better code by eliminating unnecessary
shifts and extensions earlier.
This also fixes a bug where the MAD pattern was calling
SimplifyDemandedBits with a 24-bit mask on the first operand
even when the full pattern wasn't being matched. This occasionally
resulted in some instructions being incorrectly deleted from the
program.
v2:
- Fix bug with 64-bit mul
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205731
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Tom Stellard [Mon, 7 Apr 2014 19:31:13 +0000 (19:31 +0000)]
R600: Replace dyn_cast + assert with cast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205730
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Richard Smith [Mon, 7 Apr 2014 17:17:00 +0000 (17:17 +0000)]
Remove an unused file.
Using this file would result in an odr violation: it defines an llvm::Interval
class that conflicts with the one in Analysis/Interval.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205726
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Richard Smith [Mon, 7 Apr 2014 17:09:53 +0000 (17:09 +0000)]
When a CHECK-NEXT fails because there was no match on the next line, include
the non-matching next line in the diagnostic to make the problem more obvious.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205725
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Matt Arsenault [Mon, 7 Apr 2014 16:44:26 +0000 (16:44 +0000)]
Use std::swap
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205723
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Matt Arsenault [Mon, 7 Apr 2014 16:44:24 +0000 (16:44 +0000)]
Use .data() instead of &x[0]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205722
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Eric Christopher [Mon, 7 Apr 2014 13:55:21 +0000 (13:55 +0000)]
Invert the option to enable debug info verification. No functional
change outside of the command line to enable it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205713
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Eric Christopher [Mon, 7 Apr 2014 13:36:26 +0000 (13:36 +0000)]
Revert the last couple of patches here and go back to something
that at least failed reliably.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205711
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Eric Christopher [Mon, 7 Apr 2014 13:36:21 +0000 (13:36 +0000)]
Handle vlas during inline cost computation if they'll be turned
into a constant size alloca by inlining.
Ran a run over the testsuite, no results out of the noise, fixes
the testcase in the PR.
PR19115.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205710
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Eric Christopher [Mon, 7 Apr 2014 13:10:27 +0000 (13:10 +0000)]
XFAIL this completely at the moment:
cygwin has llvm-dwarfdump problems and isn't paying attention to the
specific xfail there.
s390x isn't matching for an unknown reason.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205708
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Simon Atanasyan [Mon, 7 Apr 2014 12:59:36 +0000 (12:59 +0000)]
Fix a typo in the comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205707
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Eric Christopher [Mon, 7 Apr 2014 12:46:30 +0000 (12:46 +0000)]
Add NDEBUG markers around debug only function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205706
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Eric Christopher [Mon, 7 Apr 2014 12:32:17 +0000 (12:32 +0000)]
Add debug location information to the vectorizer debug statements.
Patch by Zinovy Nis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205705
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Eric Christopher [Mon, 7 Apr 2014 12:32:12 +0000 (12:32 +0000)]
Make test run on most platforms and only fail on cygwin/mingw while
it's being investigated for those.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205704
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Manuel Klimek [Mon, 7 Apr 2014 10:21:33 +0000 (10:21 +0000)]
Make docs point to new domain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205701
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Craig Topper [Mon, 7 Apr 2014 06:59:39 +0000 (06:59 +0000)]
Use 'false' for a bool instead of '0'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205699
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Craig Topper [Mon, 7 Apr 2014 04:17:22 +0000 (04:17 +0000)]
[C++11] Make use of 'nullptr' in the Support library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205697
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Serge Pavlov [Mon, 7 Apr 2014 03:57:04 +0000 (03:57 +0000)]
Updated phabricator server.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205696
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Elena Demikhovsky [Sun, 6 Apr 2014 11:08:33 +0000 (11:08 +0000)]
Changes in IntelJITEventListener - By Arch Robinson
- take->release: LLVM has moved to C++11. MockWrapper became an instance of unique_ptr.
- method symbol_iterator::increment disappeared recently, in this revision:
r200442 | rafael | 2014-01-29 20:49:50 -0600 (Wed, 29 Jan 2014) | 9 lines
Simplify the handling of iterators in ObjectFile.
None of the object file formats reported error on iterator increment. In
retrospect, that is not too surprising: no object format stores symbols or
sections in a linked list or other structure that requires chasing pointers.
As a consequence, all error checking can be done on begin() and end().
This reduces the text segment of bin/llvm-readobj in my machine from 521233 to
518526 bytes.
My change mimics the change that the revision made to lib/DebugInfo/DWARFContext.cpp .
- const_cast: Shut up a warning from gcc.
I ran unittests/ExecutionEngine/JIT/Debug+Asserts/JITTests to make sure it worked.
- Arch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205689
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NAKAMURA Takumi [Sun, 6 Apr 2014 10:01:23 +0000 (10:01 +0000)]
Quick fix: Triple::isOSMSVCRT() should be false for targeting cygwin.
It affected callee's stack pop in x86. It is one of devergences between cygwin and mingw since mingw-gcc-4.6.
Added testcases to llvm/test/CodeGen/X86/win32_sret.ll for cygwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205688
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Simon Atanasyan [Sun, 6 Apr 2014 09:02:55 +0000 (09:02 +0000)]
[yaml2obj][ELF] Rename class SectionNameToIdxMap => NameToIdxMap. It can
be used for indexing not only section's names.
No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205687
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