Add a case we were missing that was causing us to fail CodeGen/PowerPC/rlwinm.ll:test3

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23755 91177308-0d34-0410-b5e6-96231b3b80d8

Remove some dead code now that the dag combiner exists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23754 91177308-0d34-0410-b5e6-96231b3b80d8

Remove some dead code: the ORI/ORIS cases are autogen'd.  This makes
SelectIntImmediateExpr dead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23753 91177308-0d34-0410-b5e6-96231b3b80d8

prune #includes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23752 91177308-0d34-0410-b5e6-96231b3b80d8

These instructions are now autogenerated

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23751 91177308-0d34-0410-b5e6-96231b3b80d8

Add a pattern for FSQRTS

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23750 91177308-0d34-0410-b5e6-96231b3b80d8

remove dead code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23749 91177308-0d34-0410-b5e6-96231b3b80d8

Implement the last major missing piece in the DAG isel generator: when emitting
a pattern match, make sure to emit the (minimal number of) type checks that
verify the pattern matches this specific instruction.  This allows FMA32
patterns to not match double expressions for example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23748 91177308-0d34-0410-b5e6-96231b3b80d8

Use getExtLoad here instead of getNode, as extloads produce two values.  This
fixes a legalize failure on SPASS for itanium.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23747 91177308-0d34-0410-b5e6-96231b3b80d8

remove broken SRA/rlwimi case

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23746 91177308-0d34-0410-b5e6-96231b3b80d8

Rename PPC32*.h to PPC*.h

This completes the grand PPC file renaming

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23745 91177308-0d34-0410-b5e6-96231b3b80d8

Merge PPCJITInfo.h and PPC32JITInfo.h.  Note that the PowerPCJITInfo
and PPC32JITInfo classes should be merged.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23744 91177308-0d34-0410-b5e6-96231b3b80d8

Rename PowerPC*.h to PPC*.h

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23743 91177308-0d34-0410-b5e6-96231b3b80d8

Rename PowerPCInstrBuilder.h -> PPC*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23742 91177308-0d34-0410-b5e6-96231b3b80d8

Nuke the PowerPCTargetMachine.h header.  Note that the PowerPCTargetMachine
still should be merged into the PPC32TargetMachine class

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23741 91177308-0d34-0410-b5e6-96231b3b80d8

Rename PowerPC*.td -> PPC*.td

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23740 91177308-0d34-0410-b5e6-96231b3b80d8

These are dead

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23739 91177308-0d34-0410-b5e6-96231b3b80d8

Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23738 91177308-0d34-0410-b5e6-96231b3b80d8

Like the comment says...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23737 91177308-0d34-0410-b5e6-96231b3b80d8

Nuke PowerPCInstrFormats.h, its contents are dead.  Remove the definitions
from the .td file that correspond to it

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23736 91177308-0d34-0410-b5e6-96231b3b80d8

Properly split f32 and f64 into separate register classes for scalar sse fp
fixing a bunch of nasty hackery

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23735 91177308-0d34-0410-b5e6-96231b3b80d8

Remove an unnecsesary file.  PPC32 and PPC64 share architected registers.
We will decide with subtarget support whether we ever use an i64 register
class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23734 91177308-0d34-0410-b5e6-96231b3b80d8

add the integer truncate/extension operations

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23733 91177308-0d34-0410-b5e6-96231b3b80d8

Make sure targets depend on TargetSelectionDAG.td

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23732 91177308-0d34-0410-b5e6-96231b3b80d8

These are now autogenerated

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23731 91177308-0d34-0410-b5e6-96231b3b80d8

Now that we have int/fp lattice values, implement the SDTCisOpSmallerThanOp
type constraint.  This lets tblgen realize that it doesn't need any dynamic
type checks for fextend/fround on PPC (and many other targets), because there
are only two fp types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23730 91177308-0d34-0410-b5e6-96231b3b80d8

Fairly serious rework of the typing code to add new int/fp lattice values.
Overall, no functionality change yet though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23729 91177308-0d34-0410-b5e6-96231b3b80d8

simplify the code a bit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23728 91177308-0d34-0410-b5e6-96231b3b80d8

Add patterns for FP round/extend

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23727 91177308-0d34-0410-b5e6-96231b3b80d8

add a new SDTCisOpSmallerThanOp type constraint, and implement fround/fextend in terms of it

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23726 91177308-0d34-0410-b5e6-96231b3b80d8

Add basic support for recognizing a new SDTCisOpSmallerThanOp type constraint

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23725 91177308-0d34-0410-b5e6-96231b3b80d8

Implement a couple of new (important) features.

1. If an operation has to be int or fp and the target only supports one
   int or fp type, relize that the op has to have that type.
2. If a target has operations on multiple types, do not emit matching code
   for patterns involving those operators, since we do not emit the code to
   check for them yet.  This prevents PPC from generating FP ops currently.

Also move some code around into more logical places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23724 91177308-0d34-0410-b5e6-96231b3b80d8

Do not let getLegalValueTypes return a list with duplicates in it

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23723 91177308-0d34-0410-b5e6-96231b3b80d8

fold sext_in_reg, sext_in_reg where both have the same VT.  This was
popping up in Fourinarow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23722 91177308-0d34-0410-b5e6-96231b3b80d8

Allow $

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23721 91177308-0d34-0410-b5e6-96231b3b80d8

Relax the checking on zextload generation a bit, since as sabre pointed out
you could be AND'ing with the result of a shift that shifts out all the
bits you care about, in addition to a constant.

Also, move over an add/sub_parts fold from legalize to the dag combiner,
where it works for things other than constants.  Woot!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23720 91177308-0d34-0410-b5e6-96231b3b80d8

Fix errors when compiling with -pedantic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23719 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the trunc(load) case, finally allowing crafty and povray to pass

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23718 91177308-0d34-0410-b5e6-96231b3b80d8

Fix some bugs in (sext (load x))

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23717 91177308-0d34-0410-b5e6-96231b3b80d8

When ExpandOp'ing a [SZ]EXTLOAD, make sure to remember that the chain
is also legal.  Add support for ExpandOp'ing raw EXTLOADs too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23716 91177308-0d34-0410-b5e6-96231b3b80d8

Implement PromoteOp for *EXTLOAD, allowing MallocBench/gs to Legalize

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23715 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the remaining DAGCombiner issues pointed out by sabre.  This should fix
the remainder of the failures introduced by my patch last night.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23714 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a minor bug in the dag combiner that broke pcompress2 and some other
tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23713 91177308-0d34-0410-b5e6-96231b3b80d8

Updated to be less restrictive on what is matched

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23712 91177308-0d34-0410-b5e6-96231b3b80d8

Add support to Legalize for expanding i64 sextload/zextload into hi and lo
parts. This should fix the crafty and signed long long unit test failure
on x86 last night.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23711 91177308-0d34-0410-b5e6-96231b3b80d8

Inhibit instructions from being pushed before function calls.  This will
minimize unnecessary spilling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23710 91177308-0d34-0410-b5e6-96231b3b80d8

apparently one of the makefile changes changed libprofile.so to profile.so

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23709 91177308-0d34-0410-b5e6-96231b3b80d8

This script is used to remove nodes with the label %tmp(.#)* and all
edges associated with said node from the dot files produced by
DSA.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23708 91177308-0d34-0410-b5e6-96231b3b80d8

Nate implemented this :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23707 91177308-0d34-0410-b5e6-96231b3b80d8

Move some Legalize functionality over to the DAGCombiner where it belongs.
Kill some dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23706 91177308-0d34-0410-b5e6-96231b3b80d8

SimplifySelectCC is dead

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23705 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a potential bug with two combine-to's back to back that chris pointed
out, where after the first CombineTo() call, the node the second CombineTo
wishes to replace may no longer exist.

Fix a very real bug with the truncated load optimization on little endian
targets, which do not need a byte offset added to the load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23704 91177308-0d34-0410-b5e6-96231b3b80d8

More cool stuff for the dag combiner.  We can now finally handle things
like turning:

_foo:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        rlwinm r3, r2, 0, 16, 31
        blr

into
_foo:
        fctiwz f0,f1
        stfd f0,-8(r1)
        lhz r3,-2(r1)
        blr

Also removed an unncessary constraint from sra -> srl conversion, which
should take care of hte only reason we would ever need to handle sra in
MaskedValueIsZero, AFAIK.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23703 91177308-0d34-0410-b5e6-96231b3b80d8

Finally committing to the new scheduler.  Still -sched=none by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23702 91177308-0d34-0410-b5e6-96231b3b80d8

Added graphviz/gv support for MF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23700 91177308-0d34-0410-b5e6-96231b3b80d8

this passes with the change in predicate

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23699 91177308-0d34-0410-b5e6-96231b3b80d8

Fix (hopefully the last) issue where LSR is nondeterminstic.  When pulling
out CSE's of base expressions it could build a result whose order was
nondet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23698 91177308-0d34-0410-b5e6-96231b3b80d8

Fix another problem where LSR was being nondeterminstic.  Also remove elements
from the end of a vector instead of the beginning

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23697 91177308-0d34-0410-b5e6-96231b3b80d8

lsr doesn't emit gep instructions anymore

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23696 91177308-0d34-0410-b5e6-96231b3b80d8

Fix another lsr-is-nondeterministic case

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23695 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a powerpc crash on CodeGen/Generic/llvm-ct-intrinsics.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23694 91177308-0d34-0410-b5e6-96231b3b80d8

Add a canonicalization that got lost, fixing PowerPC/fold-li.ll:SUB

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23693 91177308-0d34-0410-b5e6-96231b3b80d8

clean up some corner cases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23692 91177308-0d34-0410-b5e6-96231b3b80d8

Implement trivial DSE.  If two stores are neighbors and store to the same
location, replace them with a new store of the last value.  This occurs
in the same neighborhood in 197.parser, speeding it up about 1.5%

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23691 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for CombineTo, allowing the dag combiner to replace nodes with
multiple results.

Use this support to implement trivial store->load forwarding, implementing
CodeGen/PowerPC/store-load-fwd.ll.  Though this is the most simple case and
can be extended in the future, it is still useful.  For example, it speeds
up 197.parser by 6.2% by avoiding an LSU reject in xalloc:

        stw r6, lo16(l5_end_of_array)(r2)
        addi r2, r5, -4
        stwx r5, r4, r2
-       lwzx r5, r4, r2
-       rlwinm r5, r5, 0, 0, 30
        stwx r5, r4, r2
        lwz r2, -4(r4)
        ori r2, r2, 1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23690 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23689 91177308-0d34-0410-b5e6-96231b3b80d8

Teach the DAGCombiner several new tricks, teaching it how to turn
sext_inreg into zext_inreg based on the signbit (fires a lot), srem into
urem, etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23688 91177308-0d34-0410-b5e6-96231b3b80d8

A testcase sitting in my tree

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23687 91177308-0d34-0410-b5e6-96231b3b80d8

Fix comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23686 91177308-0d34-0410-b5e6-96231b3b80d8

Add ISD::ADD to MaskedValueIsZero

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23685 91177308-0d34-0410-b5e6-96231b3b80d8

This function is now dead

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23684 91177308-0d34-0410-b5e6-96231b3b80d8

Enable Nate's excellent DAG combiner work by default.  This allows the
removal of a bunch of ad-hoc and crufty code from SelectionDAG.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23682 91177308-0d34-0410-b5e6-96231b3b80d8

These definitions have been moved to common code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23681 91177308-0d34-0410-b5e6-96231b3b80d8

Pull DAG ISel generation nodes out of the PowerPC backend to where they
can be used by other targets.  For those targets that want to use it,
have at.  :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23680 91177308-0d34-0410-b5e6-96231b3b80d8

add a todo for something I noticed

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23679 91177308-0d34-0410-b5e6-96231b3b80d8

(X & Y) & C == 0 if either X&C or Y&C are zero

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23678 91177308-0d34-0410-b5e6-96231b3b80d8

Make MaskedValueIsZero a bit more aggressive

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23677 91177308-0d34-0410-b5e6-96231b3b80d8

This seems useful from the original patch that added the function.  If there is a reason it is not useful on a RISC type target, let me know and I will pull it out

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23676 91177308-0d34-0410-b5e6-96231b3b80d8

Fix funky xcode indentation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23674 91177308-0d34-0410-b5e6-96231b3b80d8

Hrm, you didn't see this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23673 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a source of non-determinism in the backend: the order of processing
IV strides dependend on the pointer order of the strides in memory.
Non-determinism is bad.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23672 91177308-0d34-0410-b5e6-96231b3b80d8

When emiting a CopyFromReg and the source is already a vreg, do not bother
creating a new vreg and inserting a copy: just use the input vreg directly.

This speeds up the compile (e.g. about 5% on mesa with a debug build of llc)
by not adding a bunch of copies and vregs to be coallesced away.  On mesa,
for example, this reduces the number of intervals from 168601 to 129040
going into the coallescer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23671 91177308-0d34-0410-b5e6-96231b3b80d8

Disable formation of rlwinm instructions from SRA bases.  This fixes
the 177.mesa failure from last night, and fixes the
CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll regression test I added.
If this code cannot be fixed, it should be removed for good, but I'll leave
it to Nate to decide its fate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23670 91177308-0d34-0410-b5e6-96231b3b80d8

Testcase that is miscompiled by the ppc backend

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23669 91177308-0d34-0410-b5e6-96231b3b80d8

Remove another unused file.  Preparing for the great "enable i64 on ppc32"
merge, and using subtarget info for ptr size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23668 91177308-0d34-0410-b5e6-96231b3b80d8

remove a comma to compile with pedantic gcc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23667 91177308-0d34-0410-b5e6-96231b3b80d8

Remove a file that is no longer used

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23666 91177308-0d34-0410-b5e6-96231b3b80d8

Lo and behold, the last bits of SelectionDAG.cpp have been moved over.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23665 91177308-0d34-0410-b5e6-96231b3b80d8

When preselecting, favor things that have low depth to select first.  This
is faster and uses less stack space.  This reduces our stack requirement
enough to compile sixtrack, and though it's a hack, should be enough until
we switch to iterative isel

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23664 91177308-0d34-0410-b5e6-96231b3b80d8

remove debugging code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23663 91177308-0d34-0410-b5e6-96231b3b80d8

implement CodeGen/PowerPC/div-2.ll:test2-4 by propagating zero bits through
C-X's

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23662 91177308-0d34-0410-b5e6-96231b3b80d8

These don't need to be sdivs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23661 91177308-0d34-0410-b5e6-96231b3b80d8

fix indentation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23660 91177308-0d34-0410-b5e6-96231b3b80d8

Turn sdivs into udivs when we can prove the sign bits are clear.  This
implements CodeGen/PowerPC/div-2.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23659 91177308-0d34-0410-b5e6-96231b3b80d8

New testcase, should turn into a ushr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23658 91177308-0d34-0410-b5e6-96231b3b80d8

Remove prolific source of VC++ truncation warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23657 91177308-0d34-0410-b5e6-96231b3b80d8

Remove useless variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23656 91177308-0d34-0410-b5e6-96231b3b80d8

add a hack to work around broken VC++ scoping rules.  Thx to JeffC for pointing
this out to me

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23655 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a CQ regression from my patch to split F32/F64 into seperate register
classes on PPC.  We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced.  This fixes Regression/CodeGen/PowerPC/fpcopy.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23654 91177308-0d34-0410-b5e6-96231b3b80d8

double to float casts should nto result in an fmr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23653 91177308-0d34-0410-b5e6-96231b3b80d8