Added a tester for the enhanced disassembler,
integrated into the llvm-mc testing tool.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100842 91177308-0d34-0410-b5e6-96231b3b80d8

Add several more lint checks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100841 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a bug in IVUsers which was permitting non-affine addrecs to
be sent to LSR, which it isn't prepared to handle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100839 91177308-0d34-0410-b5e6-96231b3b80d8

Don't use reserved identifiers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100838 91177308-0d34-0410-b5e6-96231b3b80d8

fix a SCCP miscompilation that could happen when a
forced constant is changed to a constant, we would end
up adding the instruction to the wrong worklist,
preventing it from being properly revisited.  This fixes
rdar://7832370

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100837 91177308-0d34-0410-b5e6-96231b3b80d8

Bugfixes for edis.  Code to initialize instruction
state was being executed too lazily, and the LLVM
assembly syntax for the disassembler was not being
written into the proper disassembler state variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100830 91177308-0d34-0410-b5e6-96231b3b80d8

Avoid allocating a value of zero in a register if the initial formula
inputs happen to negate each other.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100828 91177308-0d34-0410-b5e6-96231b3b80d8

Add a few more lint checks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100825 91177308-0d34-0410-b5e6-96231b3b80d8

Add variants of ult, ule, etc. which take a uint64_t RHS, for convenience.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100824 91177308-0d34-0410-b5e6-96231b3b80d8

delete a forwarding function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100815 91177308-0d34-0410-b5e6-96231b3b80d8

move elf section uniquing to MCContext.  Along the way
merge XCore's section into MCSectionELF

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100812 91177308-0d34-0410-b5e6-96231b3b80d8

Now that Evan Cheng has fixed the coalescer bug (r100804), the workaround code
to avoid memcpy() call is no longer necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100811 91177308-0d34-0410-b5e6-96231b3b80d8

remove the TargetLoweringObjectFileMachO::getMachoSection
api and update clients to use MCContext instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100808 91177308-0d34-0410-b5e6-96231b3b80d8

move macho section uniquing from MCParser and TLOF to MCContext where
the compiler and asmparser now unique to the same sections.  This fixes
rdar://7835021.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100807 91177308-0d34-0410-b5e6-96231b3b80d8

Coalescer should not delete copy instructions whose defs are partially dead. e.g.
%RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100804 91177308-0d34-0410-b5e6-96231b3b80d8

Update CMake build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100802 91177308-0d34-0410-b5e6-96231b3b80d8

Fix -Wsign-compare warning (issued by clang++).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100799 91177308-0d34-0410-b5e6-96231b3b80d8

Add a -lint pass which checks for common sources of undefined or likely
unintended behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100798 91177308-0d34-0410-b5e6-96231b3b80d8

Rename a function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100797 91177308-0d34-0410-b5e6-96231b3b80d8

implicit defs get added to the end of machine instrs sometimes.  Scan the whole instruction for the metadata operand instead of assuming it will be at the end of the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100792 91177308-0d34-0410-b5e6-96231b3b80d8

Pointers to zero-sized objects don't point to overlapping objects.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100789 91177308-0d34-0410-b5e6-96231b3b80d8

Print empty structs as {} rather than { }.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100787 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100783 91177308-0d34-0410-b5e6-96231b3b80d8

Touch configure so it regenerates Disassemblers.def to include ARM so
people stop seeing a broken build in EDDisassembler.cpp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100782 91177308-0d34-0410-b5e6-96231b3b80d8

One instruction may start (or end) multiple lexical scopes.
There is no need to remember labels identifying regions marked by such instructions in each scope.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100781 91177308-0d34-0410-b5e6-96231b3b80d8

clean up algorithm and remove operand order assumptions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100780 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100774 91177308-0d34-0410-b5e6-96231b3b80d8

Remove dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100771 91177308-0d34-0410-b5e6-96231b3b80d8

Delete out of date comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100769 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100768 91177308-0d34-0410-b5e6-96231b3b80d8

Various MSVC warning fixes about truncated 64 bit shifts and const pointers passed to free.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100767 91177308-0d34-0410-b5e6-96231b3b80d8

Provide operator delete for BumpPtrAllocator and RecyclingAllocator. They will
never be called but msvc complains that they're missing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100766 91177308-0d34-0410-b5e6-96231b3b80d8

use abstract interface in two more places

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100762 91177308-0d34-0410-b5e6-96231b3b80d8

fix compile

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100760 91177308-0d34-0410-b5e6-96231b3b80d8

use abstract interface

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100758 91177308-0d34-0410-b5e6-96231b3b80d8

Use twines to simplify calls to report_fatal_error. For code size and readability.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100756 91177308-0d34-0410-b5e6-96231b3b80d8

Use errs instead of fprintf.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100754 91177308-0d34-0410-b5e6-96231b3b80d8

Avoid using f64 to lower memcpy from constant string. It's cheaper to use i32 store of immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100751 91177308-0d34-0410-b5e6-96231b3b80d8

Revert this change from a while ago; ScalarEvolution shouldn't analyze
undef as 0, since it can't force other analyses to intepret the undef
in the same way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100749 91177308-0d34-0410-b5e6-96231b3b80d8

When expanding expressions which are using post-inc mode for multiple loops,
ensure that the expansion is dominated by the increments of those loops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100748 91177308-0d34-0410-b5e6-96231b3b80d8

Make post regalloc machine licm functional. It now passes all of MultiSource.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100742 91177308-0d34-0410-b5e6-96231b3b80d8

typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100738 91177308-0d34-0410-b5e6-96231b3b80d8

document isvolatile etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100737 91177308-0d34-0410-b5e6-96231b3b80d8

mpsadbw is not commutative.

Fixes PR3440.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100736 91177308-0d34-0410-b5e6-96231b3b80d8

Added support for ARM disassembly to edis.

I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.

I will add the test harness for all this stuff in
a separate commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100735 91177308-0d34-0410-b5e6-96231b3b80d8

convert a report_fatal_error that I was able to trigger into a nice error
so the user at least knows what inline asm is a problem.  For example:

error: inline asm not supported yet: don't know how to handle tied indirect register inputs
pr8788-1.c:14:10: note: generated from here
    asm ("\n" : "+r" (stack->regs)
         ^

Instead of:
fatal error: error in backend: Don't know how to handle tied indirect register inputs yet!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100731 91177308-0d34-0410-b5e6-96231b3b80d8

Fix typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100726 91177308-0d34-0410-b5e6-96231b3b80d8

minor tidying.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100725 91177308-0d34-0410-b5e6-96231b3b80d8

use assertions instead of unreachable for logic errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100724 91177308-0d34-0410-b5e6-96231b3b80d8

introduce a new recoverable error handling API to LLVMContext
and use it in one place in inline asm handling stuff.  Before
we'd generate this for an invalid modifier letter:

$ clang asm.c -c -o t.o
fatal error: error in backend: Invalid operand found in inline asm: 'abc incl    ${0:Z}'
INLINEASM <es:abc incl    ${0:Z}>, 10, %EAX<def>, 2147483657, %EAX, 14, %EFLAGS<earlyclobber,def,dead>, <!-1>

Now we generate this:

$ clang asm.c -c -o t.o
error: invalid operand in inline asm: 'incl    ${0:Z}'
asm.c:3:12: note: generated from here
  __asm__ ("incl    %Z0" : "+r" (X));
           ^
1 error generated.

This is much better but still admittedly not great ("why" is the operand
invalid??), codegen should try harder with its diagnostics :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100723 91177308-0d34-0410-b5e6-96231b3b80d8

Say bitcast instead of bitconvert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100720 91177308-0d34-0410-b5e6-96231b3b80d8

Add svn:ignore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100719 91177308-0d34-0410-b5e6-96231b3b80d8

rename llvm_install_error_handler -> install_fatal_error_handler
and friends.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100717 91177308-0d34-0410-b5e6-96231b3b80d8

Update CMake build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100714 91177308-0d34-0410-b5e6-96231b3b80d8

Update cmake build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100713 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for stpncpy_chk.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100710 91177308-0d34-0410-b5e6-96231b3b80d8

rename llvm::llvm_report_error -> llvm::report_fatal_error

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100709 91177308-0d34-0410-b5e6-96231b3b80d8

add newlines at end of files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100706 91177308-0d34-0410-b5e6-96231b3b80d8

add newlines at the end of files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100705 91177308-0d34-0410-b5e6-96231b3b80d8

remove some unneeded errorhandling stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100703 91177308-0d34-0410-b5e6-96231b3b80d8

minor tidying up

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100702 91177308-0d34-0410-b5e6-96231b3b80d8

tidy up

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100700 91177308-0d34-0410-b5e6-96231b3b80d8

Generalize IVUsers to track arbitrary expressions rather than expressions
explicitly split into stride-and-offset pairs. Also, add the
ability to track multiple post-increment loops on the same expression.

This refines the concept of "normalizing" SCEV expressions used for
to post-increment uses, and introduces a dedicated utility routine for
normalizing and denormalizing expressions.

This fixes the expansion of expressions which are post-increment users
of more than one loop at a time. More broadly, this takes LSR another
step closer to being able to reason about more than one loop at a time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100699 91177308-0d34-0410-b5e6-96231b3b80d8

Missed this one line for the previous checkin to fix build warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100697 91177308-0d34-0410-b5e6-96231b3b80d8

Fixed warnings pointed out by clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100696 91177308-0d34-0410-b5e6-96231b3b80d8

Fixed warnings pointed out by clang.
Next to work on is ARMDisassemblerCore.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100695 91177308-0d34-0410-b5e6-96231b3b80d8

Fixed a bug where the disassembler would allow an immediate
argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter.  Now, the
disassembler rejects instructions with out-of-range values
for that immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100694 91177308-0d34-0410-b5e6-96231b3b80d8

Fixed 3 warnings pointed out by clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100693 91177308-0d34-0410-b5e6-96231b3b80d8

unXFAIL, arm disassembler was reenabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100692 91177308-0d34-0410-b5e6-96231b3b80d8

Fix typo and correct comment somewhat.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100691 91177308-0d34-0410-b5e6-96231b3b80d8

Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in
ARMDecoderEmitter.cpp, with FIXME comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100690 91177308-0d34-0410-b5e6-96231b3b80d8

Split big test into multiple directories to cater to
those who don't build all targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100688 91177308-0d34-0410-b5e6-96231b3b80d8

Added an AsmLexer for the ARM target, which uses
a simple mapping of register names to IDs to
identify register tokens.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100685 91177308-0d34-0410-b5e6-96231b3b80d8

Test that DEBUG_VALUE comments come out on a variety of targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100682 91177308-0d34-0410-b5e6-96231b3b80d8

Educate GetInstrSizeInBytes implementations that
DBG_VALUE does not generate code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100681 91177308-0d34-0410-b5e6-96231b3b80d8

fix 80-col violations

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100677 91177308-0d34-0410-b5e6-96231b3b80d8

Remove late ARM codegen optimization pass committed by accident.
It is not ready for public yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100673 91177308-0d34-0410-b5e6-96231b3b80d8

Split A8/A9 itins - they already were too big.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100672 91177308-0d34-0410-b5e6-96231b3b80d8

Add some crude itin approximation for VFP load / stores on A9

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100671 91177308-0d34-0410-b5e6-96231b3b80d8

Add some crude approximation for neon load/store instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100670 91177308-0d34-0410-b5e6-96231b3b80d8

Add some A8-based approximation for instructions with unknown cycle times

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100669 91177308-0d34-0410-b5e6-96231b3b80d8

Move NEON-VFP domain fixer upper, so post-RA scheduler would benefit from it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100668 91177308-0d34-0410-b5e6-96231b3b80d8

Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100667 91177308-0d34-0410-b5e6-96231b3b80d8

Fix A8 FP NEON MAC itins

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100666 91177308-0d34-0410-b5e6-96231b3b80d8

A9 NEON FP itins

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100665 91177308-0d34-0410-b5e6-96231b3b80d8

Some permute goodness for A9

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100664 91177308-0d34-0410-b5e6-96231b3b80d8

More shift itins for A9

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100663 91177308-0d34-0410-b5e6-96231b3b80d8

More fixes for itins

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100662 91177308-0d34-0410-b5e6-96231b3b80d8

Fix invalid itins for 32-bit varians of VMLAL and friends

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100661 91177308-0d34-0410-b5e6-96231b3b80d8

Add MAC stuff for A9

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100660 91177308-0d34-0410-b5e6-96231b3b80d8

Fix invalid NEON MAC itins on A8

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100659 91177308-0d34-0410-b5e6-96231b3b80d8

Fix itins for VPAL

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100658 91177308-0d34-0410-b5e6-96231b3b80d8

Fix itins for VABA

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100657 91177308-0d34-0410-b5e6-96231b3b80d8

Correct VMVN itinerary: operand is read in the second cycle, not in the first.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100656 91177308-0d34-0410-b5e6-96231b3b80d8

More A9 itineraries

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100655 91177308-0d34-0410-b5e6-96231b3b80d8

Correct itinerary class for VPADD

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100654 91177308-0d34-0410-b5e6-96231b3b80d8

VP{MAX, MIN} are of IIC_VSUBi4D itin class as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100653 91177308-0d34-0410-b5e6-96231b3b80d8

VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100652 91177308-0d34-0410-b5e6-96231b3b80d8

Some easy NEON scheduling goodness for A9

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100651 91177308-0d34-0410-b5e6-96231b3b80d8

Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100650 91177308-0d34-0410-b5e6-96231b3b80d8