Remove unnecessary and unused data member.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140786 91177308-0d34-0410-b5e6-96231b3b80d8

Cosmetic changes, as per Nick's review.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140785 91177308-0d34-0410-b5e6-96231b3b80d8

Place this bracket according to the LLVM style.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140784 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Fix broken shared library build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140783 91177308-0d34-0410-b5e6-96231b3b80d8

Expand the x86 V_SET0* pseudos right after register allocation.

This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140776 91177308-0d34-0410-b5e6-96231b3b80d8

Target/ARM: Unbreak! CMake! Build!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140774 91177308-0d34-0410-b5e6-96231b3b80d8

Delete NEONMoveFix, now unused.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140773 91177308-0d34-0410-b5e6-96231b3b80d8

Use ExecutionDepsFix instead of NEONMoveFix.

This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140772 91177308-0d34-0410-b5e6-96231b3b80d8

typo + pasto

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140769 91177308-0d34-0410-b5e6-96231b3b80d8

Remove NumImplicitOps which is now unused.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140767 91177308-0d34-0410-b5e6-96231b3b80d8

LSR: rewrite inner loops only.

Rewriting the entire loop nest now requires -enable-lsr-nested.
See PR11035 for some performance data.
A few unit tests specifically test nested LSR, and are now under a flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140762 91177308-0d34-0410-b5e6-96231b3b80d8

whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140761 91177308-0d34-0410-b5e6-96231b3b80d8

Fix build failures better.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140758 91177308-0d34-0410-b5e6-96231b3b80d8

Fix build failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140755 91177308-0d34-0410-b5e6-96231b3b80d8

Move to ISelLowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140754 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Add new patterns for bitconvert and any_extend

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140753 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-size: Apply Chris's code review fixes.

This doesn't use formated_raw_ostream because it doesn't support the
functionality needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140751 91177308-0d34-0410-b5e6-96231b3b80d8

Use the local we already set up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140745 91177308-0d34-0410-b5e6-96231b3b80d8

Rewrite MachineInstr::addOperand() to avoid NumImplicitOps.

The function needs to scan the implicit operands anyway, so no
performance is won by caching the number of implicit operands added to
an instruction.

This also fixes a bug when adding operands after an implicit operand has
been added manually.  The NumImplicitOps count wasn't kept up to date.

MachineInstr::addOperand() will now consistently place all explicit
operands before all the implicit operands, regardless of the order they
are added.  It is possible to change an MI opcode and add additional
explicit operands.  They will be inserted before any existing implicit
operands.

The only exception is inline asm instructions where operands are never
reordered.  This is because of a hack that marks explicit clobber regs
on inline asm as <implicit-def> to please the fast register allocator.
This hack can go away when InstrEmitter and FastIsel can add exact
<dead> flags to physreg defs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140744 91177308-0d34-0410-b5e6-96231b3b80d8

tblgen/ClangDiagnostics: Add support for split default warning "no-werror" and
"show-in-system-header" bits, which I will be adding in Clang shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140741 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r140731, "Define classes for unary and binary FP instructions and use them to define"

It broke the unit tests.  Please reapply with tests fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140735 91177308-0d34-0410-b5e6-96231b3b80d8

Tighten a ARM dag combine condition to avoid an identity transformation, which
ends up introducing a cycle in the DAG.

rdar://10196296

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140733 91177308-0d34-0410-b5e6-96231b3b80d8

Define classes for unary and binary FP instructions and use them to define
multiclasses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140731 91177308-0d34-0410-b5e6-96231b3b80d8

Have the SjLjEHPrepare pass do some more heavy lifting.

Upon further review, most of the EH code should remain written at the IR
level. The part which breaks SSA form is the dispatch table, so that part will
be moved to the back-end.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140730 91177308-0d34-0410-b5e6-96231b3b80d8

Fix cast.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140726 91177308-0d34-0410-b5e6-96231b3b80d8

PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140723 91177308-0d34-0410-b5e6-96231b3b80d8

Add llvm-size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140722 91177308-0d34-0410-b5e6-96231b3b80d8

Object: Add isSection{Data,BSS}.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140721 91177308-0d34-0410-b5e6-96231b3b80d8

NULL cannot be portably used as the last argument to a function with __attribute((sentinel)), even though it usually works.  Use (void*)0 instead.  PR11002.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140720 91177308-0d34-0410-b5e6-96231b3b80d8

Perform the lowering only if there are invokes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140719 91177308-0d34-0410-b5e6-96231b3b80d8

Ahem...actually *add* the ARMSjLjLowering pass to the pass manager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140718 91177308-0d34-0410-b5e6-96231b3b80d8

Add a note on removing LLVMC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140715 91177308-0d34-0410-b5e6-96231b3b80d8

Introduce llvm-cov.

Add llvm-cov skeleton. It has initial support to read coverage info generated by GCOVProfiling.cpp.
Today, you can do
prompt> clang a.c -ftest-coverage -fprofile-arcs -o a
prompt> ./a
prompt> llvm-cov -gcno a.gcno -gcda a.gcda
a.c
 : #include "a.h"
 :
 : int main() {
 : int i = 0;
 : if (i) {
1: int j = 0;
1: j = 1;
1: } else {
 : int k = 1;
 : k = 2;
 : }
1: return 0;
 : }
 :
 :

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140712 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Fix alignment logic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140709 91177308-0d34-0410-b5e6-96231b3b80d8

Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140705 91177308-0d34-0410-b5e6-96231b3b80d8

Remove definitions of branch-on-FP-likely instructions. They are deprecated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140704 91177308-0d34-0410-b5e6-96231b3b80d8

Mips64 predicate definitions. Patch by Liu.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140703 91177308-0d34-0410-b5e6-96231b3b80d8

indvars: generalize SCEV getPreStartForSignExtend.

Handle general Add expressions to avoid leaving around redundant
32-bit IVs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140701 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: MC-ize the PTX backend (patch 2 of N)

Get rid of some of the no-longer-needed parts of PTXAsmPrinter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140698 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: MC-ize the PTX back-end (patch 1 of N)

Lay some groundwork for converting to MC-based asm printer. This is the first
of probably many patches to bring the back-end back up-to-date with all of the
recent MC changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140697 91177308-0d34-0410-b5e6-96231b3b80d8

Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.

Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8

Changed comments on foreign C++ exceptions (generated with type info 7),
handling with references to
http://sourcery.mentor.com/public/cxx-abi/abi-eh.html (r 1.22).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140695 91177308-0d34-0410-b5e6-96231b3b80d8

A typeid of zero means a cleanup, not a catch.  This case occurs
when there is both a catch and a cleanup.  Correct the comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140686 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Simplify code. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140680 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Pass param name strings per const reference.

The copies caused use-after-free bugs on std::string implementations without COW (i.e. anything but libstdc++)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140679 91177308-0d34-0410-b5e6-96231b3b80d8

Strip off pointer casts when looking at the eh.sjlj.functioncontext's argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140678 91177308-0d34-0410-b5e6-96231b3b80d8

Bitcast the alloca to an i8* to match the intrinsic's signature.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140677 91177308-0d34-0410-b5e6-96231b3b80d8

Create and use an llvm.eh.sjlj.functioncontext intrinsic.

This intrinsic is used to pass the index of the function context to the back-end
for further processing. The back-end is in charge of filling in the rest of the
entries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140676 91177308-0d34-0410-b5e6-96231b3b80d8

In the new EH model, setup the function context and the call site info.

The DWARF exception pass uses the call site information, which is set up here. A
pre-RA pass is too late for it to use this information. So create and setup the
function context here, and then insert the call site values here (and map the
call sites for the DWARF EH pass). This is simpler than the original pass, and
doesn't make the CFG lose its SSA-ness.

It's a win-win-win-win-lose-win-win situation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140675 91177308-0d34-0410-b5e6-96231b3b80d8

Don't conditionalize execution of the SjLj EH prepare pass.

We may need an SjLj EH preparation pass for some call site information, at least
in the short term.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140674 91177308-0d34-0410-b5e6-96231b3b80d8

Test case for r140670: indvars should hoist sext.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140671 91177308-0d34-0410-b5e6-96231b3b80d8

indvars should hoist [sz]ext because licm is not rerun.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140670 91177308-0d34-0410-b5e6-96231b3b80d8

PR10628: Fix getModRefInfo so it queries the underlying alias() implementation correctly while checking nocapture calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140666 91177308-0d34-0410-b5e6-96231b3b80d8

Rename class and clean up source.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140664 91177308-0d34-0410-b5e6-96231b3b80d8

Rename SSEDomainFix -> lib/CodeGen/ExecutionDepsFix.

I'll clean up the source in the next commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140663 91177308-0d34-0410-b5e6-96231b3b80d8

Remove MipsFPRound. Mips1 is no longer supported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140661 91177308-0d34-0410-b5e6-96231b3b80d8

Remove X86-dependent stuff from SSEDomainFix.

This also enables domain swizzling for AVX code which required a few
trivial test changes.

The pass will be moved to lib/CodeGen shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140659 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak CMake build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140655 91177308-0d34-0410-b5e6-96231b3b80d8

Implement TII::get/setExecutionDomain() for ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140653 91177308-0d34-0410-b5e6-96231b3b80d8

Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo.

I am going to unify the SSEDomainFix and NEONMoveFix passes into a
single target independent pass.  They are essentially doing the same
thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140652 91177308-0d34-0410-b5e6-96231b3b80d8

ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.

Add inst alias to handle these assembly forms. Add tests, too.

rdar://10178799

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140647 91177308-0d34-0410-b5e6-96231b3b80d8

This is the start of the new SjLj EH preparation pass, which will replace the
current IR-level pass.

The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).

Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140646 91177308-0d34-0410-b5e6-96231b3b80d8

Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside
of the instruction definitions using Pat<>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140644 91177308-0d34-0410-b5e6-96231b3b80d8

Remove an invalid assert that is really just asserting when the scheduler emits
a suboptimal schedule.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140643 91177308-0d34-0410-b5e6-96231b3b80d8

test/CMakeLists.txt: Depend on llvm-objdump. "make check" is expected to resolve test-dependent targets on CMake build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140641 91177308-0d34-0410-b5e6-96231b3b80d8

Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().

Naming conventions consistency. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140636 91177308-0d34-0410-b5e6-96231b3b80d8

Stop emitting instructions with the name "tmp" they eat up memory and have to be uniqued, without any benefit.

If someone prefers %tmp42 to %42, run instnamer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140634 91177308-0d34-0410-b5e6-96231b3b80d8

Remove incorrect passage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140631 91177308-0d34-0410-b5e6-96231b3b80d8

These symbols appear to be visible by SearchForAddressOfSymbol and no longer
require special case handling.
rdar://10117377

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140629 91177308-0d34-0410-b5e6-96231b3b80d8

Add binary archive support to llvm-nm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140627 91177308-0d34-0410-b5e6-96231b3b80d8

Object: Add archive support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140626 91177308-0d34-0410-b5e6-96231b3b80d8

Check that catch clauses have pointer type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140625 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Fix case where printed alignment could be 0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140624 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140622 91177308-0d34-0410-b5e6-96231b3b80d8

Add FCA to the lexicon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140619 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Use external symbols to keep track of params and locals. This also fixes
a couple of outstanding issues with frame objects occuring as instruction
operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140616 91177308-0d34-0410-b5e6-96231b3b80d8

Use existing function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140615 91177308-0d34-0410-b5e6-96231b3b80d8

Fix function MipsRegisterInfo::getRegisterNumbering.
Return numbers of 64-bit registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140609 91177308-0d34-0410-b5e6-96231b3b80d8

Do not add the pass that restores $gp if target is Mips64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140607 91177308-0d34-0410-b5e6-96231b3b80d8

Have the verifier check that all landingpad operands are constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140606 91177308-0d34-0410-b5e6-96231b3b80d8

Cleanup PromoteIntOp_EXTRACT_VECTOR_ELT and PromoteIntRes_SETCC.
Add a new method: getAnyExtOrTrunc and use it to replace the manual check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140603 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r140463; The patch assumes that <4 x i1> is saved to memory as 4 x i8,
while the decision is to bit-pack small values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140601 91177308-0d34-0410-b5e6-96231b3b80d8

Remove some not-really-correct wording.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140600 91177308-0d34-0410-b5e6-96231b3b80d8

Mark MipsPseudo isPseudo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140598 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Add support for sitofp in backend

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140593 91177308-0d34-0410-b5e6-96231b3b80d8

Split the landing pad basic block with the correct function. Also merge the
split landingpad instructions into a PHI node.
PR11016

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140592 91177308-0d34-0410-b5e6-96231b3b80d8

Disable LSR retry by default.

Disabling aggressive LSR saves compilation time, and with the new
indvars behavior usually improves performance.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140590 91177308-0d34-0410-b5e6-96231b3b80d8

Last batch of test conversions to new atomic instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140585 91177308-0d34-0410-b5e6-96231b3b80d8

LSR, one of the new Cost::isLoser() checks did not get merged in the previous checkin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140583 91177308-0d34-0410-b5e6-96231b3b80d8

Convert a bunch more tests over to the new atomic instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140582 91177308-0d34-0410-b5e6-96231b3b80d8

Remove extraneous commit garbage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140581 91177308-0d34-0410-b5e6-96231b3b80d8

LSR cost metric minor fix and verification.

The minor bug heuristic was noticed by inspection. I added the
isLoser/isValid helpers because they will become more
important with subsequent checkins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140580 91177308-0d34-0410-b5e6-96231b3b80d8

Fix an incorrect decoder test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140579 91177308-0d34-0410-b5e6-96231b3b80d8

Remove old hack for compiling with gcc-4.0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140573 91177308-0d34-0410-b5e6-96231b3b80d8

Remove incorrect testcases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140572 91177308-0d34-0410-b5e6-96231b3b80d8

Set register class of a register according to value of HasMips64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140570 91177308-0d34-0410-b5e6-96231b3b80d8

Define variable HasMips64 in MipsTargetLowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140569 91177308-0d34-0410-b5e6-96231b3b80d8

In single float mode, double precision FP arguments are passed in integer
registers, so there is no need to check here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140568 91177308-0d34-0410-b5e6-96231b3b80d8

Convert more tests to new atomic instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140567 91177308-0d34-0410-b5e6-96231b3b80d8

Convert more tests over to the new atomic instructions.

I did not convert Atomics-32.ll and Atomics-64.ll by hand; the diff is autoupgrade output.

The wmb test is gone because there isn't any way to express wmb with the new atomic instructions; if someone really needs a non-asm way to write a wmb on Alpha, a platform-specific intrisic could be added.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140566 91177308-0d34-0410-b5e6-96231b3b80d8