Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo.

I am going to unify the SSEDomainFix and NEONMoveFix passes into a
single target independent pass.  They are essentially doing the same
thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140652 91177308-0d34-0410-b5e6-96231b3b80d8

ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.

Add inst alias to handle these assembly forms. Add tests, too.

rdar://10178799

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140647 91177308-0d34-0410-b5e6-96231b3b80d8

This is the start of the new SjLj EH preparation pass, which will replace the
current IR-level pass.

The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).

Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140646 91177308-0d34-0410-b5e6-96231b3b80d8

Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside
of the instruction definitions using Pat<>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140644 91177308-0d34-0410-b5e6-96231b3b80d8

Remove an invalid assert that is really just asserting when the scheduler emits
a suboptimal schedule.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140643 91177308-0d34-0410-b5e6-96231b3b80d8

test/CMakeLists.txt: Depend on llvm-objdump. "make check" is expected to resolve test-dependent targets on CMake build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140641 91177308-0d34-0410-b5e6-96231b3b80d8

Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().

Naming conventions consistency. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140636 91177308-0d34-0410-b5e6-96231b3b80d8

Stop emitting instructions with the name "tmp" they eat up memory and have to be uniqued, without any benefit.

If someone prefers %tmp42 to %42, run instnamer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140634 91177308-0d34-0410-b5e6-96231b3b80d8

Remove incorrect passage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140631 91177308-0d34-0410-b5e6-96231b3b80d8

These symbols appear to be visible by SearchForAddressOfSymbol and no longer
require special case handling.
rdar://10117377

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140629 91177308-0d34-0410-b5e6-96231b3b80d8

Add binary archive support to llvm-nm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140627 91177308-0d34-0410-b5e6-96231b3b80d8

Object: Add archive support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140626 91177308-0d34-0410-b5e6-96231b3b80d8

Check that catch clauses have pointer type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140625 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Fix case where printed alignment could be 0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140624 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140622 91177308-0d34-0410-b5e6-96231b3b80d8

Add FCA to the lexicon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140619 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Use external symbols to keep track of params and locals. This also fixes
a couple of outstanding issues with frame objects occuring as instruction
operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140616 91177308-0d34-0410-b5e6-96231b3b80d8

Use existing function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140615 91177308-0d34-0410-b5e6-96231b3b80d8

Fix function MipsRegisterInfo::getRegisterNumbering.
Return numbers of 64-bit registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140609 91177308-0d34-0410-b5e6-96231b3b80d8

Do not add the pass that restores $gp if target is Mips64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140607 91177308-0d34-0410-b5e6-96231b3b80d8

Have the verifier check that all landingpad operands are constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140606 91177308-0d34-0410-b5e6-96231b3b80d8

Cleanup PromoteIntOp_EXTRACT_VECTOR_ELT and PromoteIntRes_SETCC.
Add a new method: getAnyExtOrTrunc and use it to replace the manual check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140603 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r140463; The patch assumes that <4 x i1> is saved to memory as 4 x i8,
while the decision is to bit-pack small values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140601 91177308-0d34-0410-b5e6-96231b3b80d8

Remove some not-really-correct wording.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140600 91177308-0d34-0410-b5e6-96231b3b80d8

Mark MipsPseudo isPseudo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140598 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Add support for sitofp in backend

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140593 91177308-0d34-0410-b5e6-96231b3b80d8

Split the landing pad basic block with the correct function. Also merge the
split landingpad instructions into a PHI node.
PR11016

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140592 91177308-0d34-0410-b5e6-96231b3b80d8

Disable LSR retry by default.

Disabling aggressive LSR saves compilation time, and with the new
indvars behavior usually improves performance.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140590 91177308-0d34-0410-b5e6-96231b3b80d8

Last batch of test conversions to new atomic instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140585 91177308-0d34-0410-b5e6-96231b3b80d8

LSR, one of the new Cost::isLoser() checks did not get merged in the previous checkin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140583 91177308-0d34-0410-b5e6-96231b3b80d8

Convert a bunch more tests over to the new atomic instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140582 91177308-0d34-0410-b5e6-96231b3b80d8

Remove extraneous commit garbage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140581 91177308-0d34-0410-b5e6-96231b3b80d8

LSR cost metric minor fix and verification.

The minor bug heuristic was noticed by inspection. I added the
isLoser/isValid helpers because they will become more
important with subsequent checkins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140580 91177308-0d34-0410-b5e6-96231b3b80d8

Fix an incorrect decoder test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140579 91177308-0d34-0410-b5e6-96231b3b80d8

Remove old hack for compiling with gcc-4.0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140573 91177308-0d34-0410-b5e6-96231b3b80d8

Remove incorrect testcases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140572 91177308-0d34-0410-b5e6-96231b3b80d8

Set register class of a register according to value of HasMips64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140570 91177308-0d34-0410-b5e6-96231b3b80d8

Define variable HasMips64 in MipsTargetLowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140569 91177308-0d34-0410-b5e6-96231b3b80d8

In single float mode, double precision FP arguments are passed in integer
registers, so there is no need to check here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140568 91177308-0d34-0410-b5e6-96231b3b80d8

Convert more tests to new atomic instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140567 91177308-0d34-0410-b5e6-96231b3b80d8

Convert more tests over to the new atomic instructions.

I did not convert Atomics-32.ll and Atomics-64.ll by hand; the diff is autoupgrade output.

The wmb test is gone because there isn't any way to express wmb with the new atomic instructions; if someone really needs a non-asm way to write a wmb on Alpha, a platform-specific intrisic could be added.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140566 91177308-0d34-0410-b5e6-96231b3b80d8

Fix grammar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140564 91177308-0d34-0410-b5e6-96231b3b80d8

Remove dead table entry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140563 91177308-0d34-0410-b5e6-96231b3b80d8

Some minor (and more involved) cleanups. No real context changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140561 91177308-0d34-0410-b5e6-96231b3b80d8

ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8

Convert more tests over to the new atomic instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140559 91177308-0d34-0410-b5e6-96231b3b80d8

Upgrade a couple more tests to the new atomic instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140558 91177308-0d34-0410-b5e6-96231b3b80d8

Enhance alias analysis for atomic instructions a bit.  Upgrade a couple alias-analysis tests to the new atomic instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140557 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Fix memcpy intrinsic to handle 64-bit pointers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140556 91177308-0d34-0410-b5e6-96231b3b80d8

Fix this test so it doesn't fail on Mac.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140553 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Implement PTXSelectionDAGInfo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140549 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Implement ISD::ANY_EXTEND

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140548 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Fix detection of stack load/store vs. global load/store, as well as fix the
printing of local offsets

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140547 91177308-0d34-0410-b5e6-96231b3b80d8

Fix emission of debug data for global variables. getContext() on DIGlobalVariables is not valid any more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140539 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Add .align tests to stack object test file

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140537 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: SM > 2.0 implies +double

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140536 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Fix some lingering issues with stack allocation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140535 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Split up the TableGen instruction definitions into logical units

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140534 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Unify handling of loads/stores

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140533 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Handle FrameIndex nodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140532 91177308-0d34-0410-b5e6-96231b3b80d8

Only run tests in test/CodeGen/CBackend/X86 when both X86 and CBackend are supported

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140517 91177308-0d34-0410-b5e6-96231b3b80d8

PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140516 91177308-0d34-0410-b5e6-96231b3b80d8

Fix VEX decoding in i386 mode. Fixes PR11008.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140515 91177308-0d34-0410-b5e6-96231b3b80d8

Add target hook for pseudo instruction expansion.

Many targets use pseudo instructions to help register allocation.  Like
the COPY instruction, these pseudos can be expanded after register
allocation.  The early expansion can make life easier for PEI and the
post-ra scheduler.

This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140472 91177308-0d34-0410-b5e6-96231b3b80d8

[vector-select] Address one of the issues in pr10902. EXTRACT_VECTOR_ELEMENT
SDNodes may return values which are wider than the incoming element types. In
this patch we fix the integer promotion of these nodes.

Fixes spill-q.ll when running -promote-elements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140471 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up code after renaming LowerSubregs -> ExpandPostRAPseudos.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140470 91177308-0d34-0410-b5e6-96231b3b80d8

Rename LowerSubregs to ExpandPostRAPseudos.

I'll fix the file contents in the next commit.

This pass is currently expanding the COPY and SUBREG_TO_REG pseudos. I
am going to add a hook so targets can expand more pseudo-instructions
after register allocation.

Many targets have pseudo-instructions that assist the register
allocator.  They can be expanded after register allocation, before PEI
and PostRA scheduling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140469 91177308-0d34-0410-b5e6-96231b3b80d8

Sort CMakeLists.txt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140465 91177308-0d34-0410-b5e6-96231b3b80d8

Implement Duncan's suggestion to use the result of getSetCCResultType if it is legal
(this is always the case for scalars), otherwise use the promoted result type.

Fix test/CodeGen/X86/vsplit-and.ll when promote-elements is enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140464 91177308-0d34-0410-b5e6-96231b3b80d8

[Vector-Select] Address one of the problems in 10902.

When generating the trunc-store of i1's, we need to use the vector type and not
the scalar type.

This patch fixes the assertion in CodeGen/Generic/bool-vector.ll when
running with -promote-elements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140463 91177308-0d34-0410-b5e6-96231b3b80d8

Add .td file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140446 91177308-0d34-0410-b5e6-96231b3b80d8

Revert change made in .gitignore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140445 91177308-0d34-0410-b5e6-96231b3b80d8

Preparation for adding simple Mips64 instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140443 91177308-0d34-0410-b5e6-96231b3b80d8

Only run MF.verify() with EXPENSIVE_CHECKS=1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140441 91177308-0d34-0410-b5e6-96231b3b80d8

sys::Process: Add a SetWorkingDirectory method.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140433 91177308-0d34-0410-b5e6-96231b3b80d8

LSR minor bug fix in RateRegister.

No test case. Noticed by inspection and I doubt it ever affects the
outcome of the overall heuristic, let alone final codegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140431 91177308-0d34-0410-b5e6-96231b3b80d8

Duncan owns dragonegg too, it's all his fault :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140430 91177308-0d34-0410-b5e6-96231b3b80d8

Verify that terminators follow non-terminators.

This exposes a -segmented-stacks bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140429 91177308-0d34-0410-b5e6-96231b3b80d8

PR10998: It is not legal to sink an instruction past the terminator of a block; make sure we don't do that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140428 91177308-0d34-0410-b5e6-96231b3b80d8

Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140426 91177308-0d34-0410-b5e6-96231b3b80d8

Also match negative offsets for addrmode3 and addrmode5.

Math is hard, and isScaledConstantInRange() always returned false for
negative constants.  It was doing unsigned division of negative numbers
before casting back to signed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140425 91177308-0d34-0410-b5e6-96231b3b80d8

Fix incorrect disassembly test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140423 91177308-0d34-0410-b5e6-96231b3b80d8

Add more fixed bits to USAT16 encoding to filter out incorrect decodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140422 91177308-0d34-0410-b5e6-96231b3b80d8

Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140420 91177308-0d34-0410-b5e6-96231b3b80d8

Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r140412.  This affects more instructions than intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140413 91177308-0d34-0410-b5e6-96231b3b80d8

Thumb2 register-shifted-register loads cannot target the PC or the SP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140412 91177308-0d34-0410-b5e6-96231b3b80d8

Add getTreeFactory() to ImmutableSet to allow construction of ImmutableSetRef from an ImmutableSet object.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140402 91177308-0d34-0410-b5e6-96231b3b80d8

Implement N32/64 calling convention. Patch by Liu.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140401 91177308-0d34-0410-b5e6-96231b3b80d8

Make FGR64RegisterClass available if target is Mips64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140397 91177308-0d34-0410-b5e6-96231b3b80d8

Add definitions of 64-bit register files. Add code for returning Mips64's sets of
callee-saved registers and reserved registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140395 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Fix parameter order bug

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140394 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a couple of 80 column violations.
patch contributed by Jia Liu!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140391 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Cleanup unused code in PTXMachineFunctionInfo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140390 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Fix another 80-column violation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140387 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Handle function call return values

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140386 91177308-0d34-0410-b5e6-96231b3b80d8

Fix 80 column violations.

Original patch by Liu.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140385 91177308-0d34-0410-b5e6-96231b3b80d8

Implement Chris's suggestion of legalizing the various SSE and AVX
hadd/hsub intrinsics into the new fhadd/fhsub X86 node.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140383 91177308-0d34-0410-b5e6-96231b3b80d8

Modified demo to use 3.0 resume instruction vs calling _Unwine_Resume.

Also conducted some reformatting. As the LLVM coding standard doc does not
seem to touch on how to align function arguments, and format code longer than
80 cols in general, the confusion persists. There is the golden rule, but as
this code has gone through several styles to deal with this, the golden rule
seems to be ignored. The latest reformatting effort tries to match the other
source files as much as possible.

Tested on OS X 10.7.1 with, and without the OLD_EXC_SYSTEM defined. Have NOT
tested on LINUX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140379 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Start fixing function calls

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140378 91177308-0d34-0410-b5e6-96231b3b80d8