Benjamin Kramer [Wed, 11 Jul 2012 09:39:04 +0000 (09:39 +0000)]
Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160040
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Nadav Rotem [Wed, 11 Jul 2012 08:52:09 +0000 (08:52 +0000)]
Refactor the DAG Legalizer by extracting the legalization of
Load and Store nodes into their own functions.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160037
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Owen Anderson [Wed, 11 Jul 2012 06:38:55 +0000 (06:38 +0000)]
Only apply the SETCC+SITOFP -> SELECTCC optimization when the SETCC returns an MVT::i1, i.e. before type legalization.
This is a speculative fix for a problem on Mips reported by Akira Hatanaka.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160036
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Akira Hatanaka [Wed, 11 Jul 2012 00:53:32 +0000 (00:53 +0000)]
Lower RETURNADDR node in Mips backend.
Patch by Sasa Stankovic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160031
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Jack Carter [Tue, 10 Jul 2012 22:41:20 +0000 (22:41 +0000)]
Mips specific inline asm operand modifier 'L'.
Low order register of a double word register operand. Operands
are defined by the name of the variable they are marked with in
the inline assembler code. This is a way to specify that the
operand just refers to the low order register for that variable.
It is the opposite of modifier 'D' which specifies the high order
register.
Example:
main()
{
long long ll_input = 0x1111222233334444LL;
long long ll_val = 3;
int i_result = 0;
__asm__ __volatile__(
"or %0, %L1, %2"
: "=r" (i_result)
: "r" (ll_input), "r" (ll_val));
}
Which results in:
lui $2, %hi(_gp_disp)
addiu $2, $2, %lo(_gp_disp)
addiu $sp, $sp, -8
addu $2, $2, $25
sw $2, 0($sp)
lui $2, 13107
ori $3, $2, 17476 <-- Low 32 bits of ll_input
lui $2, 4369
ori $4, $2, 8738 <-- High 32 bits of ll_input
addiu $5, $zero, 3 <-- Low 32 bits of ll_val
addiu $2, $zero, 0 <-- High 32 bits of ll_val
#APP
or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val
#NO_APP
addiu $sp, $sp, 8
jr $ra
If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.
There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028
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Jakob Stoklund Olesen [Tue, 10 Jul 2012 22:39:56 +0000 (22:39 +0000)]
Require and preserve LoopInfo for early if-conversion.
It will surely be needed by heuristics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160027
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Chandler Carruth [Tue, 10 Jul 2012 22:25:21 +0000 (22:25 +0000)]
Teach the LiveInterval::join function to use the fast merge algorithm,
generalizing its implementation sufficiently to support this value
number scenario as well.
This cuts out another significant performance hit in large functions
(over 10k basic blocks, etc), especially those with "natural" CFG
structures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160026
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Jakob Stoklund Olesen [Tue, 10 Jul 2012 22:18:23 +0000 (22:18 +0000)]
Run early if-conversion in domtree post-order.
This ordering allows nested if-conversion without using a work list, and
it makes it possible to update the dominator tree on the fly as well.
Any erased basic blocks will always be dominated by the current
post-order position, so the domtree can be pruned without invalidating
the iterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160025
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Chad Rosier [Tue, 10 Jul 2012 18:27:15 +0000 (18:27 +0000)]
Move [get|set]BasePtrStackAdjustment() from MachineFrameInfo to
X86MachineFunctionInfo as this is currently only used by X86. If this ever
becomes an issue on another arch (e.g., ARM) then we can hoist it back out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160009
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Chad Rosier [Tue, 10 Jul 2012 17:57:00 +0000 (17:57 +0000)]
Add newline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160006
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Chad Rosier [Tue, 10 Jul 2012 17:49:39 +0000 (17:49 +0000)]
Add test case accidentally omitted from r160002.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160004
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Chad Rosier [Tue, 10 Jul 2012 17:45:53 +0000 (17:45 +0000)]
Add support for dynamic stack realignment in the presence of dynamic allocas on
X86. Basically, this is a reapplication of r158087 with a few fixes.
Specifically, (1) the stack pointer is restored from the base pointer before
popping callee-saved registers and (2) in obscure cases (see comments in patch)
we must cache the value of the original stack adjustment in the prologue and
apply it in the epilogue.
rdar://
11496434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160002
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Chandler Carruth [Tue, 10 Jul 2012 15:41:33 +0000 (15:41 +0000)]
Fix a bug where I didn't test for an empty range before inspecting the
back of it.
I don't have anything even remotely close to a test case for this. It
only broke two build bots, both of them doing bootstrap builds, one of
them a dragonegg bootstrap. It doesn't break for me when I bootstrap
either. It doesn't reproduce every time or on many machines during the
bootstrap. Many thanks to Duncan Sands who got the exact command (and
stage of the bootstrap) which failed on the dragonegg bootstrap and
managed to get it to trigger under valgrind with debug symbols. The fix
was then found by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159993
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Nadav Rotem [Tue, 10 Jul 2012 13:25:08 +0000 (13:25 +0000)]
Improve the loading of load-anyext vectors by allowing the codegen to load
multiple scalars and insert them into a vector. Next, we shuffle the elements
into the correct places, as before.
Also fix a small dagcombine bug in SimplifyBinOpWithSameOpcodeHands, when the
migration of bitcasts happened too late in the SelectionDAG process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159991
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Richard Barton [Tue, 10 Jul 2012 12:51:09 +0000 (12:51 +0000)]
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989
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Craig Topper [Tue, 10 Jul 2012 06:38:33 +0000 (06:38 +0000)]
Reverse assembler/disassembler operand order for gather instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159983
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Chandler Carruth [Tue, 10 Jul 2012 05:16:17 +0000 (05:16 +0000)]
Add an efficient merge operation to LiveInterval and use it to avoid
quadratic behavior when performing pathological merges. Fixes the core
element of PR12652.
There is only one user of addRangeFrom left: join. I'm hoping to
refactor further in a future patch and have join use this merge
operation as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159982
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Chandler Carruth [Tue, 10 Jul 2012 05:06:03 +0000 (05:06 +0000)]
Teach LiveIntervals how to verify themselves and start using it in some
of the trick merge routines. This adds a layer of testing that was
necessary when implementing more efficient (and complex) merge logic for
this datastructure.
No functionality changed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159981
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Jim Grosbach [Tue, 10 Jul 2012 00:51:13 +0000 (00:51 +0000)]
ARM: Allow more flexible patterns in NEON formats.
Some NEON instructions want to match against normal SDNodes for some
operand types and Intrinsics for others. For example, CTLZ. To enable this,
switch from explicitly requiring Intrinsic on the class templates to using
SDPatternOperator instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159974
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Jim Grosbach [Tue, 10 Jul 2012 00:51:11 +0000 (00:51 +0000)]
Allow intrinsics to be used in place of node matchables.
TableGen has support for using an intrinics name directly in a DAG,
but this breaks down when referring to just a node, as that's
handled initializer list stuff entirely via subclassing in the
parser. That is, using an instrinsic like "(int_my_intrinsic ...)"
works fine. Using it standalone for parameterizing the operator
in such a DAG does not.
Fixing this is simple enough, as we simply declare Intrinsic
as deriving from SDPatternOperator, which is the class name
intended for exactly this purpose in TargetSelectionDAG.td.
When the intrinsic is actually used in the DAG pattern, it will
be recognized and expanded to an intrinsic_wo_chain (et. al.)
just like when it's used directly.
Incoming ARM NEON cleanup based on this and a bit of functionality
improvement after that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159973
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Akira Hatanaka [Tue, 10 Jul 2012 00:19:06 +0000 (00:19 +0000)]
Make register Mips::RA allocatable if not in mips16 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159971
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Dan Gohman [Mon, 9 Jul 2012 23:51:20 +0000 (23:51 +0000)]
Delete code for folding undefs in ScalarEvolution. It's invalid in
obscure ways, and it isn't actually important in the real world.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159969
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Chad Rosier [Mon, 9 Jul 2012 20:43:34 +0000 (20:43 +0000)]
Revert r159938 (and r159945) to appease the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960
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Andrew Trick [Mon, 9 Jul 2012 20:43:03 +0000 (20:43 +0000)]
Machine model: allow itineraries to be shared by different processor models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159959
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Andrew Trick [Mon, 9 Jul 2012 20:43:01 +0000 (20:43 +0000)]
indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159958
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Owen Anderson [Mon, 9 Jul 2012 20:31:12 +0000 (20:31 +0000)]
Teach the DAG combiner to turn sitofp/uitofp from i1 into a conditional move, since there are only two possible values.
Previously, this would become an integer extension operation, followed by a real integer->float conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159957
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Manman Ren [Mon, 9 Jul 2012 18:57:12 +0000 (18:57 +0000)]
X86: implement functions to analyze & synthesize CMOV|SET|Jcc
getCondFromSETOpc, getCondFromCMovOpc, getSETFromCond, getCMovFromCond
No functional change intended.
If we want to update the condition code of CMOV|SET|Jcc, we first analyze the
opcode to get the condition code, then update the condition code, finally
synthesize the new opcode form the new condition code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159955
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Akira Hatanaka [Mon, 9 Jul 2012 18:46:47 +0000 (18:46 +0000)]
Reapply r158846.
Access mips register classes via MCRegisterInfo's functions instead of via the
TargetRegisterClasses defined in MipsGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953
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Nuno Lopes [Mon, 9 Jul 2012 18:38:20 +0000 (18:38 +0000)]
instcombine: merge the functions that remove dead allocas and dead mallocs/callocs/...
This patch removes ~70 lines in InstCombineLoadStoreAlloca.cpp and makes both functions a bit more aggressive than before :)
In theory, we can be more aggressive when removing an alloca than a malloc, because an alloca pointer should never escape, but we are not taking advantage of this anyway
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159952
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Richard Barton [Mon, 9 Jul 2012 18:30:56 +0000 (18:30 +0000)]
Some formatting to keep Clang happy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159948
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Richard Barton [Mon, 9 Jul 2012 18:20:02 +0000 (18:20 +0000)]
Oops - correct broken disassembly for VMOV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159945
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Richard Barton [Mon, 9 Jul 2012 16:41:33 +0000 (16:41 +0000)]
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938
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Richard Barton [Mon, 9 Jul 2012 16:31:14 +0000 (16:31 +0000)]
Prevent ARM assembler from losing a right shift by #32 applied to a register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159937
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Richard Barton [Mon, 9 Jul 2012 16:14:28 +0000 (16:14 +0000)]
Spelling!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159936
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Richard Barton [Mon, 9 Jul 2012 16:12:24 +0000 (16:12 +0000)]
Teach the assembler to use the narrow thumb encodings of various three-register dp instructions where permissable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159935
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Benjamin Kramer [Sun, 8 Jul 2012 19:47:51 +0000 (19:47 +0000)]
Remove some trivial copy ctors so the classes become trivially copyable and get the optimized SmallVector implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159916
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Benjamin Kramer [Sun, 8 Jul 2012 12:06:35 +0000 (12:06 +0000)]
SmallVector: Make use of move semantics to speed up moving objects in erase() and insert()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159914
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Andrew Trick [Sat, 7 Jul 2012 04:00:00 +0000 (04:00 +0000)]
I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.
MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.
These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.
This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891
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Andrew Trick [Sat, 7 Jul 2012 03:59:51 +0000 (03:59 +0000)]
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159890
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Andrew Trick [Sat, 7 Jul 2012 03:59:48 +0000 (03:59 +0000)]
Tweak spelling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159889
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Manman Ren [Sat, 7 Jul 2012 03:34:46 +0000 (03:34 +0000)]
X86: Fix optimizeCompare to correctly check safe condition.
It is safe if EFLAGS is killed or re-defined.
When we are done with the basic block, check whether EFLAGS is live-out.
Do not optimize away cmp if EFLAGS is live-out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159888
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NAKAMURA Takumi [Sat, 7 Jul 2012 03:12:28 +0000 (03:12 +0000)]
LLVMConfig.cmake.in: Quote around @LLVM_INSTALL_PREFIX@, or it would not accept whitespace paths.
Thanks to Kai.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159887
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Bill Wendling [Sat, 7 Jul 2012 00:52:35 +0000 (00:52 +0000)]
Use the DebugInfo wrappers instead of mucking about with the MDNode directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159881
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Bill Wendling [Fri, 6 Jul 2012 23:43:12 +0000 (23:43 +0000)]
Print the name last.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159879
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Chad Rosier [Fri, 6 Jul 2012 23:13:38 +0000 (23:13 +0000)]
Fix the naming of ensureAlignment. Per the coding standard function names
should be camel case, and start with a lower case letter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159877
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Nuno Lopes [Fri, 6 Jul 2012 23:09:25 +0000 (23:09 +0000)]
teach instcombine to remove allocated buffers even if there are stores, memcpy/memmove/memset, and objectsize users.
This means we can do cheap DSE for heap memory.
Nothing is done if the pointer excapes or has a load.
The churn in the tests is mostly due to objectsize, since we want to make sure we
don't delete the malloc call before evaluating the objectsize (otherwise it becomes -1/0)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159876
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Dmitri Gribenko [Fri, 6 Jul 2012 23:06:47 +0000 (23:06 +0000)]
Since SmallMap was removed in r158644, remove documentation in ProgrammersManual.html.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159874
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Bill Wendling [Fri, 6 Jul 2012 23:06:16 +0000 (23:06 +0000)]
Check if it's a scope last, because several things are scopes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159873
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Jim Grosbach [Fri, 6 Jul 2012 21:52:04 +0000 (21:52 +0000)]
ARM: Add test cleanup entry to the README.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159864
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Akira Hatanaka [Fri, 6 Jul 2012 20:16:48 +0000 (20:16 +0000)]
revert r159851.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159854
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Akira Hatanaka [Fri, 6 Jul 2012 19:29:11 +0000 (19:29 +0000)]
Reapply r158846.
Include file MipsGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159851
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Bill Wendling [Fri, 6 Jul 2012 19:12:31 +0000 (19:12 +0000)]
Add a print method to the ObjC property object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159848
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Bill Wendling [Fri, 6 Jul 2012 17:49:19 +0000 (17:49 +0000)]
Remove trailing comma in array initialization list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159843
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Bill Wendling [Fri, 6 Jul 2012 17:47:36 +0000 (17:47 +0000)]
Remove unnecessary 'llvm::'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159842
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Bill Wendling [Fri, 6 Jul 2012 17:46:28 +0000 (17:46 +0000)]
Remove unnecessary 'llvm::'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159841
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Chad Rosier [Fri, 6 Jul 2012 17:44:22 +0000 (17:44 +0000)]
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159839
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Manman Ren [Fri, 6 Jul 2012 17:36:20 +0000 (17:36 +0000)]
X86: peephole optimization to remove cmp instruction
For each Cmp, we check whether there is an earlier Sub which make Cmp
redundant. We handle the case where SUB operates on the same source operands as
Cmp, including the case where the two source operands are swapped.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159838
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Chad Rosier [Fri, 6 Jul 2012 17:33:39 +0000 (17:33 +0000)]
[fast-isel] Tell fast-isel to do nothing with the new donothing intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159837
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Chad Rosier [Fri, 6 Jul 2012 17:15:03 +0000 (17:15 +0000)]
Update getFunction parameter documentation. Fixes PR13268.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159835
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Dmitri Gribenko [Fri, 6 Jul 2012 16:42:25 +0000 (16:42 +0000)]
Revert r159789.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159834
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NAKAMURA Takumi [Fri, 6 Jul 2012 15:55:39 +0000 (15:55 +0000)]
llvm/include/llvm/CMakeLists.txt: Cut dependency to intrinsics_gen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159831
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Duncan Sands [Fri, 6 Jul 2012 14:43:16 +0000 (14:43 +0000)]
Attempt to fix windows buildbots. Patch by James Benton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159826
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NAKAMURA Takumi [Fri, 6 Jul 2012 12:12:39 +0000 (12:12 +0000)]
test/CodeGen/X86/sext-setcc-self.ll: Mark it as XFAIL: cygwin,mingw32,win32. Investigating.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159820
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NAKAMURA Takumi [Fri, 6 Jul 2012 11:12:44 +0000 (11:12 +0000)]
Revert r159804, "[arm-fast-isel] Add support for vararg function calls."
It broke LLVM :: CodeGen/Thumb2/large-call.ll on several hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159817
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Alexey Samsonov [Fri, 6 Jul 2012 08:45:08 +0000 (08:45 +0000)]
Fix PR13202 and a regtest.
DwarfDebug class could generate the same (inlined) DIVariable twice:
1) when trying to find abstract debug variable for a concrete inlined instance.
2) when explicitly collecting info for variables that were optimized out.
This change makes sure that this duplication won't happen and makes
Clang pass "gdb.opt/inline-locals" test from gdb testsuite.
Reviewed by Eric Christopher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159811
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Bill Wendling [Fri, 6 Jul 2012 05:51:50 +0000 (05:51 +0000)]
Sphinxify the CMake document.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159806
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Jush Lu [Fri, 6 Jul 2012 03:02:37 +0000 (03:02 +0000)]
[arm-fast-isel] Add support for vararg function calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159804
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Jack Carter [Fri, 6 Jul 2012 02:44:22 +0000 (02:44 +0000)]
Changes per review of commit 159787
Mips specific inline asm operand modifier D.
Comment changes and predicate change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159802
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Eric Christopher [Fri, 6 Jul 2012 02:35:57 +0000 (02:35 +0000)]
Untabify and move a function near similar functions dealing with struct
types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159801
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Jakob Stoklund Olesen [Fri, 6 Jul 2012 02:31:22 +0000 (02:31 +0000)]
Add some comments suggested in code review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159800
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Dmitri Gribenko [Fri, 6 Jul 2012 00:25:39 +0000 (00:25 +0000)]
Enable new[] on llvm::BumpPtrAllocator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159789
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Jack Carter [Thu, 5 Jul 2012 23:58:21 +0000 (23:58 +0000)]
Mips specific inline asm operand modifier D.
Print the second half of a double word operand.
The include list was cleaned up a bit as well.
Also the test case was modified to test for both
big and little patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159787
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Owen Anderson [Thu, 5 Jul 2012 22:30:42 +0000 (22:30 +0000)]
Fix an overzealous assertion. It is legitimate for a target to have multiple fixups on a single instruction that target the same byte, so long as their bit-offsets are coordinates appropriately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159785
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Akira Hatanaka [Thu, 5 Jul 2012 19:29:31 +0000 (19:29 +0000)]
test case for r159770.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159771
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Akira Hatanaka [Thu, 5 Jul 2012 19:26:38 +0000 (19:26 +0000)]
Enclose instruction rdhwr with directives, which are needed when target is
mips32 rev1 (the directives are emitted when target is mips32r2 too).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159770
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Akira Hatanaka [Thu, 5 Jul 2012 19:09:33 +0000 (19:09 +0000)]
Enable target dependent directive parsing to hook before standard parser in
AsmParser::ParseStatement.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159768
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Nuno Lopes [Thu, 5 Jul 2012 17:37:07 +0000 (17:37 +0000)]
add @llvm.donothing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159758
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Chandler Carruth [Thu, 5 Jul 2012 12:40:45 +0000 (12:40 +0000)]
Optimize extendIntervalEndTo a tiny bit by saving one call through the
vector erase. No functionality changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159746
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Chandler Carruth [Thu, 5 Jul 2012 11:40:23 +0000 (11:40 +0000)]
Remove dead infrastructure for building DenseMaps with a SlotIndex as
the key -- they are now stored in an IntervalMap.
I noticed this while looking into PR12652.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159745
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Chandler Carruth [Thu, 5 Jul 2012 11:06:22 +0000 (11:06 +0000)]
Finish fixing the MachineOperand hashing, providing a nice modern
hash_value overload for MachineOperands. This addresses a FIXME
sufficient for me to remove it, and cleans up the code nicely too.
The important changes to the hashing logic:
- TargetFlags are now included in all of the hashes. These were complete
missed.
- Register operands have their subregisters and whether they are a def
included in the hash.
- We now actually hash all of the operand types. Previously, many
operand types were simply *dropped on the floor*. For example:
- Floating point immediates
- Large integer immediates (>64-bit)
- External globals!
- Register masks
- Metadata operands
- It removes the offset from the block-address hash; I'm a bit
suspicious of this, but isIdenticalTo doesn't consider the offset for
black addresses.
Any patterns involving these entities could have triggered extreme
slowdowns in MachineCSE or PHIElimination. Let me know if there are PRs
you think might be closed now... I'm looking myself, but I may miss
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159743
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Duncan Sands [Thu, 5 Jul 2012 10:14:33 +0000 (10:14 +0000)]
All cases are covered, no need for a default. This deals with the
corresponding clang warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159742
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Chandler Carruth [Thu, 5 Jul 2012 10:03:57 +0000 (10:03 +0000)]
The hash function for MI expressions, used by MachineCSE, is really
broken. This patch fixes the superficial problems which lead to the
intractably slow compile times reported in PR13225.
The specific issue is that we were failing to include the *offset* of
a global variable in the hash code. Oops. This would in turn cause all
MIs which were only distinguishable due to operating on different
offsets of a global variable to produce identical hash functions. In
some of the test cases attached to the PR I saw hash table activity
where there were O(1000) probes-per-lookup *on average*. A very few
entries were responsible for most of these probes.
There is still quite a bit more to do here. The ad-hoc layering of data
in MachineOperands makes them *extremely* brittle to hash correctly.
We're missing quite a few other cases, the only ones I've fixed here are
the specific MO types which were allowed through the assert() in
getOffset().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159741
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Duncan Sands [Thu, 5 Jul 2012 09:32:46 +0000 (09:32 +0000)]
Use the right kind of booleans: we were emitting 0/1 booleans, instead of 0/-1
booleans. Patch by James Benton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159739
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Kostya Serebryany [Thu, 5 Jul 2012 09:07:31 +0000 (09:07 +0000)]
[tsan] fix compile-time falilure found while building Chromium with tsan (tsan issue #3). A unit test will follow separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159736
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Nick Lewycky [Thu, 5 Jul 2012 06:19:21 +0000 (06:19 +0000)]
Remove ParentMap. You can just ask the domnode for its parent. No functionality
change.
Move the "Not profitable, avoid CSE!" debug message next to where we fail the
check for profitability and use a different message for avoiding CSE due to
being in different register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159729
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Jakob Stoklund Olesen [Wed, 4 Jul 2012 23:53:27 +0000 (23:53 +0000)]
Make X86 call and return instructions non-variadic.
Function argument and return value registers aren't part of the
encoding, so they should be implicit operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159728
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Jakob Stoklund Olesen [Wed, 4 Jul 2012 23:53:23 +0000 (23:53 +0000)]
Allow trailing physreg RegisterSDNode operands on non-variadic instructions.
Also allow trailing register mask operands on non-variadic both
MachineSDNodes and MachineInstrs.
The extra physreg RegisterSDNode operands are added to the MI as
<imp-use> operands. This makes it possible to have non-variadic call
instructions.
Call and return instructions really are non-variadic, the argument
registers should only be used implicitly - they are not part of the
encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159727
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Jakob Stoklund Olesen [Wed, 4 Jul 2012 23:53:19 +0000 (23:53 +0000)]
Print SlotIndexes when available for -print-machineinstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159726
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Jakob Stoklund Olesen [Wed, 4 Jul 2012 19:52:05 +0000 (19:52 +0000)]
Allow multiple terminators to read virtual registers.
Find the kill as the last terminator to read SrcReg.
Patch by Philipp Brüschweiler!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159722
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Jakob Stoklund Olesen [Wed, 4 Jul 2012 19:28:31 +0000 (19:28 +0000)]
Ensure CopyToReg nodes are always glued to the call instruction.
The CopyToReg nodes that set up the argument registers before a call
must be glued to the call instruction. Otherwise, the scheduler may emit
the physreg copies long before the call, causing long live ranges for
the fixed registers.
Besides disabling good register allocation, that can also expose
problems when EmitInstrWithCustomInserter() splits a basic block during
the live range of a physreg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159721
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Jakob Stoklund Olesen [Wed, 4 Jul 2012 19:28:27 +0000 (19:28 +0000)]
Make sure -print-machineinstrs applies to the first pass as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159720
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Rafael Espindola [Wed, 4 Jul 2012 16:06:00 +0000 (16:06 +0000)]
Add a testcase for pr13209. It is not a great test, but it still fails if
159509 and 159479 are reverted. It would be really nice to be able to run
just the coalescer :-(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159715
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Alexey Samsonov [Wed, 4 Jul 2012 09:42:54 +0000 (09:42 +0000)]
Fix a bug in DebugInfo lib, extend a comment for one of the methods
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159707
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Stepan Dyatkovskiy [Wed, 4 Jul 2012 06:07:06 +0000 (06:07 +0000)]
Reverted r159658:
Optimized diff operation: implemented the case when LHS and RHS subsets contains single numbers only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159704
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Stepan Dyatkovskiy [Wed, 4 Jul 2012 05:53:05 +0000 (05:53 +0000)]
Reverted r156659, due to probable performance regressions, DenseMap should be used here:
IntegersSubsetMapping
- Replaced type of Items field from std::list with std::map. In neares future I'll test it with DenseMap and do the correspond replacement
if possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159703
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Eric Christopher [Wed, 4 Jul 2012 02:02:18 +0000 (02:02 +0000)]
Reduce some code duplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159701
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Matt Beaumont-Gay [Wed, 4 Jul 2012 01:09:45 +0000 (01:09 +0000)]
Fix some ascii art in a comment to not have trailing backslashes (inspiration
from IfConversion.cc), and fix some spelling and grammar in the surrounding
prose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159699
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Jakob Stoklund Olesen [Wed, 4 Jul 2012 00:09:58 +0000 (00:09 +0000)]
Add early if-conversion support to X86.
Implement the TII hooks needed by EarlyIfConversion to create cmov
instructions and estimate their latency.
Early if-conversion is still not enabled by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159695
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Jakob Stoklund Olesen [Wed, 4 Jul 2012 00:09:54 +0000 (00:09 +0000)]
Add an experimental early if-conversion pass, off by default.
This pass performs if-conversion on SSA form machine code by
speculatively executing both sides of the branch and using a cmov
instruction to select the result. This can help lower the number of
branch mispredictions on architectures like x86 that don't have
predicable instructions.
The current implementation is very aggressive, and causes regressions on
mosts tests. It needs good heuristics that have yet to be implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159694
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Nuno Lopes [Tue, 3 Jul 2012 21:15:40 +0000 (21:15 +0000)]
PHINode::hasConstantValue(): return undef if the PHI is fully recursive.
Thanks Duncan for the idea
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159687
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