Jakob Stoklund Olesen [Mon, 11 Jun 2012 21:14:28 +0000 (21:14 +0000)]
Fix test that depends on register allocation.
The test is really checking the prolog/epilog load/store multiple
formation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158328
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Hal Finkel [Mon, 11 Jun 2012 19:57:04 +0000 (19:57 +0000)]
Enable MFOCRF generation on the PPC A2 core.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158324
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Hal Finkel [Mon, 11 Jun 2012 19:57:01 +0000 (19:57 +0000)]
Rename the PPC target feature gpul to mfocrf.
The PPC target feature gpul (IsGigaProcessor) was only used for one thing:
To enable the generation of the MFOCRF instruction. Furthermore, this
instruction is available on other PPC cores outside of the G5 line. This
feature now corresponds to the HasMFOCRF flag.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158323
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Hal Finkel [Mon, 11 Jun 2012 19:56:57 +0000 (19:56 +0000)]
Add A2 to the list of PPC CPUs recognized by Linux host CPU-type detection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158322
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Jakob Stoklund Olesen [Mon, 11 Jun 2012 16:01:14 +0000 (16:01 +0000)]
Fix test case to work on ARM.
Patch by James Benton!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158316
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Hal Finkel [Mon, 11 Jun 2012 15:43:15 +0000 (15:43 +0000)]
Emit the two-operand form of the PPC mfcr instruction as mfocrf.
This is necessary on Linux and supported on Darwin, see PR2604.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158315
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Hal Finkel [Mon, 11 Jun 2012 15:43:13 +0000 (15:43 +0000)]
Add local CPU detection for Linux PPC.
This functionality mirrors that available on PPC/Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158314
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Hal Finkel [Mon, 11 Jun 2012 15:43:08 +0000 (15:43 +0000)]
Add POWER6 and POWER7 CPU types to the PPC backend.
No functional change; these will be used by upcoming scheduler enhancements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158313
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Jakob Stoklund Olesen [Mon, 11 Jun 2012 15:37:55 +0000 (15:37 +0000)]
Write llvm-tblgen backends as functions instead of sub-classes.
The TableGenBackend base class doesn't do much, and will be removed
completely soon.
Patch by Sean Silva!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158311
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Jakob Stoklund Olesen [Mon, 11 Jun 2012 15:11:12 +0000 (15:11 +0000)]
Fix a problem with the reverse bundle iterators.
This showed up the first time rend() was called on a bundled instruction
in the Mips backend.
Also avoid dereferencing end() in bundle_iterator::operator++().
We still don't have a place to put unit tests for this stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158310
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Benjamin Kramer [Mon, 11 Jun 2012 09:40:10 +0000 (09:40 +0000)]
Object file output from llc isn't experimental anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158305
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Bill Wendling [Mon, 11 Jun 2012 08:07:26 +0000 (08:07 +0000)]
Re-enable the CMN instruction.
We turned off the CMN instruction because it had semantics which we weren't
getting correct. If we are comparing with an immediate, then it's okay to use
the CMN instruction.
<rdar://problem/
7569620>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158302
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Benjamin Kramer [Mon, 11 Jun 2012 08:01:25 +0000 (08:01 +0000)]
InstCombine: factor code better.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158301
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Benjamin Kramer [Sun, 10 Jun 2012 20:35:00 +0000 (20:35 +0000)]
InstCombine: Turn (zext A) == (B & (1<<X)-1) into A == (trunc B), narrowing the compare.
This saves a cast, and zext is more expensive on platforms with subreg support
than trunc is. This occurs in the BSD implementation of memchr(3), see PR12750.
On the synthetic benchmark from that bug stupid_memchr and bsd_memchr have the
same performance now when not inlining either function.
stupid_memchr: 323.0us
bsd_memchr: 321.0us
memchr: 479.0us
where memchr is the llvm-gcc compiled bsd_memchr from osx lion's libc. When
inlining is enabled bsd_memchr still regresses down to llvm-gcc memchr time,
I haven't fully understood the issue yet, something is grossly mangling the
loop after inlining.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158297
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Hal Finkel [Sun, 10 Jun 2012 19:32:29 +0000 (19:32 +0000)]
Enable ILP scheduling for all nodes by default on PPC.
Over the entire test-suite, this has an insignificantly negative average
performance impact, but reduces some of the worst slowdowns from the
anti-dep. change (r158294).
Largest speedups:
SingleSource/Benchmarks/Stanford/Quicksort - 28%
SingleSource/Benchmarks/Stanford/Towers - 24%
SingleSource/Benchmarks/Shootout-C++/matrix - 23%
MultiSource/Benchmarks/SciMark2-C/scimark2 - 19%
MultiSource/Benchmarks/MiBench/automotive-bitcount/automotive-bitcount - 15%
(matrix and automotive-bitcount were both in the top-5 slowdown list from the
anti-dep. change)
Largest slowdowns:
MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 28%
MultiSource/Benchmarks/mediabench/gsm/toast/toast - 26%
MultiSource/Benchmarks/MiBench/automotive-susan/automotive-susan - 21%
SingleSource/Benchmarks/CoyoteBench/lpbench - 20%
MultiSource/Applications/d/make_dparser - 16%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158296
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Nadav Rotem [Sun, 10 Jun 2012 18:42:51 +0000 (18:42 +0000)]
Add AutoUpgrade support for the SSE4 ptest intrinsics.
Patch by Michael Kuperstein.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158295
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Hal Finkel [Sun, 10 Jun 2012 11:15:36 +0000 (11:15 +0000)]
Use critical anti-dep. breaking on all PPC targets, but also add other register classes.
Using 'all' instead of 'critical' would be better because it would make it easier to
satisfy the bundling constraints, but, as noted in the FIXME, that is currently not
possible with the crs.
This yields an average 1% speedup over the entire test suite (on Power 7). Largest speedups:
SingleSource/Benchmarks/Shootout-C++/moments - 40%
MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 28%
SingleSource/Benchmarks/BenchmarkGame/nsieve-bits - 26%
SingleSource/Benchmarks/McGill/misr - 23%
MultiSource/Applications/JM/ldecod/ldecod - 22%
Largest slowdowns:
SingleSource/Benchmarks/Shootout-C++/matrix - -29%
SingleSource/Benchmarks/Shootout-C++/ary3 - -22%
MultiSource/Benchmarks/BitBench/uuencode/uuencode - -18%
SingleSource/Benchmarks/Shootout-C++/ary - -17%
MultiSource/Benchmarks/MiBench/automotive-bitcount/automotive-bitcount - -15%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158294
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Craig Topper [Sun, 10 Jun 2012 07:31:56 +0000 (07:31 +0000)]
Add intrinsics for immediate form of XOP vprot instructions. Use i128mem instead of f128mem for integer XOP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158291
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Hal Finkel [Sat, 9 Jun 2012 22:10:19 +0000 (22:10 +0000)]
Improve ext/trunc patterns on PPC64.
The PPC64 backend had patterns for i32 <-> i64 extensions and truncations that
would leave self-moves in the final assembly. Replacing those patterns with ones
based on the SUBREG builtins yields better-looking code.
Thanks to Jakob and Owen for their suggestions in this matter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158283
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Craig Topper [Sat, 9 Jun 2012 17:02:24 +0000 (17:02 +0000)]
Use XOP vpcom intrinsics in patterns instead of a target specific SDNode type. Remove the custom lowering code that selected the SDNode type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158279
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Craig Topper [Sat, 9 Jun 2012 16:46:13 +0000 (16:46 +0000)]
Replace XOP vpcom intrinsics with fewer intrinsics that take the immediate as an argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158278
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Benjamin Kramer [Sat, 9 Jun 2012 15:33:28 +0000 (15:33 +0000)]
Hashing: Remove outdated comment. Support for reserved hash values was removed in r151865.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158276
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Aaron Ballman [Sat, 9 Jun 2012 13:59:29 +0000 (13:59 +0000)]
Disabling a spurious deprecation warning about using PathV1 from within the PathV1 implementation file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158274
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Aaron Ballman [Sat, 9 Jun 2012 13:46:36 +0000 (13:46 +0000)]
Fixing a typo in the comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158273
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Benjamin Kramer [Sat, 9 Jun 2012 10:34:15 +0000 (10:34 +0000)]
Allocate the contents of DwarfDebug's StringMaps in a single big BumpPtrAllocator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158265
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Duncan Sands [Sat, 9 Jun 2012 10:04:03 +0000 (10:04 +0000)]
Silence a gcc-4.6 warning: GCC fails to understand that secondReg and cmpOp2 are
correlated, and thinks that cmpOp2 may be used uninitialized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158263
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Hal Finkel [Sat, 9 Jun 2012 03:14:50 +0000 (03:14 +0000)]
Enable tail merging on PPC.
Tail merging had been disabled on PPC because it would disturb bundling decisions
made during pre-RA scheduling on the 970 cores. Now, however, all bundling decisions
are made during post-RA scheduling, and tail merging is generally beneficial (the
average test-suite speedup is insignificantly positive).
Largest test-suite speedups:
MultiSource/Benchmarks/mediabench/gsm/toast/toast - 30%
MultiSource/Benchmarks/BitBench/uuencode/uuencode - 23%
SingleSource/Benchmarks/Shootout-C++/ary - 21%
SingleSource/Benchmarks/Stanford/Queens - 17%
Largest slowdowns:
MultiSource/Benchmarks/MiBench/security-sha/security-sha - 24%
MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 22%
MultiSource/Applications/JM/ldecod/ldecod - 14%
MultiSource/Benchmarks/mediabench/g721/g721encode/encode - 9%
This is improved by using full (instead of just critical) anti-dependency breaking,
but doing so still causes miscompiles and so cannot yet be enabled by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158259
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Andrew Trick [Sat, 9 Jun 2012 02:16:58 +0000 (02:16 +0000)]
Register pressure: added getPressureAfterInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158256
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Jakob Stoklund Olesen [Sat, 9 Jun 2012 02:13:10 +0000 (02:13 +0000)]
Sketch a LiveRegMatrix analysis pass.
The LiveRegMatrix represents the live range of assigned virtual
registers in a Live interval union per register unit. This is not
fundamentally different from the interference tracking in RegAllocBase
that both RABasic and RAGreedy use.
The important differences are:
- LiveRegMatrix tracks interference per register unit instead of per
physical register. This makes interference checks cheaper and
assignments slightly more expensive. For example, the ARM D7 reigster
has 24 aliases, so we would check 24 physregs before assigning to one.
With unit-based interference, we check 2 units before assigning to 2
units.
- LiveRegMatrix caches regmask interference checks. That is currently
duplicated functionality in RABasic and RAGreedy.
- LiveRegMatrix is a pass which makes it possible to insert
target-dependent passes between register allocation and rewriting.
Such passes could tweak the register assignments with interference
checking support from LiveRegMatrix.
Eventually, RABasic and RAGreedy will be switched to LiveRegMatrix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158255
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Jack Carter [Sat, 9 Jun 2012 00:27:55 +0000 (00:27 +0000)]
Test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158250
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Jakob Stoklund Olesen [Sat, 9 Jun 2012 00:14:47 +0000 (00:14 +0000)]
Also compute MBB live-in lists in the new rewriter pass.
This deduplicates some code from the optimizing register allocators, and
it means that it is now possible to change the register allocators'
solutions simply by editing the VirtRegMap between the register
allocator pass and the rewriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158249
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Dmitri Gribenko [Sat, 9 Jun 2012 00:01:45 +0000 (00:01 +0000)]
Convert comments to proper Doxygen comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158248
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Andrew Trick [Fri, 8 Jun 2012 23:56:26 +0000 (23:56 +0000)]
Removing strange "using" declarations form TargetInstrInfo.
I can't imagine why these were added. Trial and error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158247
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Jakob Stoklund Olesen [Fri, 8 Jun 2012 23:44:45 +0000 (23:44 +0000)]
Reintroduce VirtRegRewriter.
OK, not really. We don't want to reintroduce the old rewriter hacks.
This patch extracts virtual register rewriting as a separate pass that
runs after the register allocator. This is possible now that
CodeGen/Passes.cpp can configure the full optimizing register allocator
pipeline.
The rewriter pass uses register assignments in VirtRegMap to rewrite
virtual registers to physical registers, and it inserts kill flags based
on live intervals.
These finalization steps are the same for the optimizing register
allocators: RABasic, RAGreedy, and PBQP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158244
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Jakob Stoklund Olesen [Fri, 8 Jun 2012 23:15:12 +0000 (23:15 +0000)]
Don't run RAFast in the optimizing regalloc pipeline.
The fast register allocator is not supposed to work in the optimizing
pipeline. It doesn't make sense to compute live intervals, run full copy
coalescing, and then run RAFast.
Fast register allocation in the optimizing pipeline is better done by
RABasic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158242
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Nuno Lopes [Fri, 8 Jun 2012 22:30:05 +0000 (22:30 +0000)]
canonicalize:
-%a + 42
into
42 - %a
previously we were emitting:
-(%a + 42)
This fixes the infinite loop in PR12338. The generated code is still not perfect, though.
Will work on that next
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158237
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Evan Cheng [Fri, 8 Jun 2012 21:53:50 +0000 (21:53 +0000)]
Start implementing pre-ra if-converter: using speculation and selects to eliminate branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158234
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Andrew Trick [Fri, 8 Jun 2012 21:52:38 +0000 (21:52 +0000)]
TargetInstrInfo hooks implemented in codegen should be declared pure virtual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158233
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Duncan Sands [Fri, 8 Jun 2012 20:15:33 +0000 (20:15 +0000)]
Reapply commit 158073 with a fix (the testcase was already committed). The
problem was that by moving instructions around inside the function, the pass
could accidentally move the iterator being used to advance over the function
too. Fix this by only processing the instruction equal to the iterator, and
leaving processing of instructions that might not be equal to the iterator
to later (later = after traversing the basic block; it could also wait until
after traversing the entire function, but this might make the sets quite big).
Original commit message:
Grab-bag of reassociate tweaks. Unify handling of dead instructions and
instructions to reoptimize. Exploit this to more systematically eliminate
dead instructions (this isn't very useful in practice but is convenient for
analysing some testcase I am working on). No need for WeakVH any more: use
an AssertingVH instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158226
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Hal Finkel [Fri, 8 Jun 2012 20:02:09 +0000 (20:02 +0000)]
Remove the TODO statement in the PPC README re: CTR loops
As Chris points out, this can now be removed!
TODO: check if the associated section on viterbi's inner loop can also be removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158224
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Hal Finkel [Fri, 8 Jun 2012 19:19:53 +0000 (19:19 +0000)]
Enable PPC CTR loop formation by default.
Thanks to Jakob's help, this now causes no new test suite failures!
Over the entire test suite, this gives an average 1% speedup. The largest speedups are:
SingleSource/Benchmarks/Misc/pi - 108%
SingleSource/Benchmarks/CoyoteBench/lpbench - 54%
MultiSource/Benchmarks/Prolangs-C/unix-smail/unix-smail - 50%
SingleSource/Benchmarks/Shootout/ary3 - 32%
SingleSource/Benchmarks/Shootout-C++/matrix - 30%
The largest slowdowns are:
MultiSource/Benchmarks/mediabench/gsm/toast/toast - -30%
MultiSource/Benchmarks/Prolangs-C/bison/mybison - -25%
MultiSource/Benchmarks/BitBench/uuencode/uuencode - -22%
MultiSource/Applications/d/make_dparser - -14%
SingleSource/Benchmarks/Shootout-C++/ary - -13%
In light of these slowdowns, additional profiling work is obviously needed!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158223
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Hal Finkel [Fri, 8 Jun 2012 19:02:08 +0000 (19:02 +0000)]
Mark the PPC CTRRC and CTRRC8 register classes as non-allocatable.
Marking these classes as non-alocatable allows CTR loop generation to
work correctly with the block placement passes, etc. These register
classes are currently used only by some unused TCRETURN patterns.
In future cleanup, these will be removed.
Thanks again to Jakob for suggesting this fix to the CTR loop problem!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158221
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Manman Ren [Fri, 8 Jun 2012 18:58:26 +0000 (18:58 +0000)]
Enable optimization for integer ABS on X86 if Subtarget has CMOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158220
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Manman Ren [Fri, 8 Jun 2012 18:42:37 +0000 (18:42 +0000)]
Test case for r158160
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158218
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Andrew Trick [Fri, 8 Jun 2012 18:25:47 +0000 (18:25 +0000)]
Sched itinerary fix: Avoid static initializers.
This fixes an accidental dependence on static initialization order that I introduced yesterday.
Thank you Lang!!!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158215
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Chad Rosier [Fri, 8 Jun 2012 18:04:52 +0000 (18:04 +0000)]
Fix a crash in APInt::lshr when shiftAmt > BitWidth.
Patch by James Benton <jbenton@vmware.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158213
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Andrew Trick [Fri, 8 Jun 2012 17:23:27 +0000 (17:23 +0000)]
Fix Target->Codegen dependence.
Bulk move of TargetInstrInfo implementation into
TargetInstrInfoImpl. This is dirty because the code isn't part of
TargetInstrInfoImpl class, nor should it be, because the methods are
not target hooks. However, it's the current mechanism for keeping
libTarget useful outside the backend. You'll get a not-so-nice link
error if you invoke a TargetInstrInfo method that depends on CodeGen.
The TargetInstrInfoImpl class should probably be removed since it
doesn't really solve this problem.
To really fix this, we probably need separate interfaces for the
CodeGen/nonCodeGen sides of TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158212
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Nuno Lopes [Fri, 8 Jun 2012 16:31:42 +0000 (16:31 +0000)]
BoundsChecking: add support for ConstantPointerNull. fixes a bunch of instrumentation failures in loops with reallocs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158210
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NAKAMURA Takumi [Fri, 8 Jun 2012 16:28:06 +0000 (16:28 +0000)]
test/CodeGen/Generic/APIntLoadStore.ll: Mark as XFAIL:ppc since r157911.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158209
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Hal Finkel [Fri, 8 Jun 2012 15:38:25 +0000 (15:38 +0000)]
Disable the PPC CTR-Loops pass by default.
The pass itself works well, but the something in the Machine* infrastructure
does not understand terminators which define registers. Without the ability
to use the block-placement pass, etc. this causes performance regressions (and
so is turned off by default). Turning off the analysis turns off the problems
with the Machine* infrastructure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158206
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Hal Finkel [Fri, 8 Jun 2012 15:38:23 +0000 (15:38 +0000)]
Fix a bug in the new PPC CTR-Loops pass.
The code which tests for an induction operation cannot assume that any
ADDI instruction will have a register operand because the operand could
also be a frame index; for example:
%vreg16<def> = ADDI8 <fi#0>, 0; G8RC:%vreg16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158205
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Hal Finkel [Fri, 8 Jun 2012 15:38:21 +0000 (15:38 +0000)]
Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form CTR-based loop branching code.
This pass is derived from the Hexagon HardwareLoops pass. The only significant enhancement over the Hexagon
pass is that PPCCTRLoops will also attempt to delete the replaced add and compare operations if they are
no longer otherwise used. Also, invalid preheader DebugLoc is not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158204
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Duncan Sands [Fri, 8 Jun 2012 13:37:30 +0000 (13:37 +0000)]
Revert commit 158073 while waiting for a fix. The issue is that reassociate
can move instructions within the instruction list. If the instruction just
happens to be the one the basic block iterator is pointing to, and it is
moved to a different basic block, then we get into an infinite loop due to
the iterator running off the end of the basic block (for some reason this
doesn't fire any assertions). Original commit message:
Grab-bag of reassociate tweaks. Unify handling of dead instructions and
instructions to reoptimize. Exploit this to more systematically eliminate
dead instructions (this isn't very useful in practice but is convenient for
analysing some testcase I am working on). No need for WeakVH any more: use
an AssertingVH instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158199
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Tobias Grosser [Fri, 8 Jun 2012 09:41:23 +0000 (09:41 +0000)]
cmake: Pass the -m32 flag to modules if LLVM_BUILD_32_BITS is enabled
This was previously only done for executables and shared libraries, but not
for modules. As modules are essentially shared libraries (that need to be
dlopened explicitly), threating them the same as shared libraries seems
reasonable. This fixes the LLVM_BUILD_32_BITS build of Polly.
Contributed by: Ondra Hosek <ondra.hosek@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158195
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Owen Anderson [Fri, 8 Jun 2012 00:25:03 +0000 (00:25 +0000)]
Teach the AsmMatcherEmitter to allow InstAlias' where the suboperands of a complex operand are called out explicitly in the asm string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158183
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Michael J. Spencer [Thu, 7 Jun 2012 23:33:56 +0000 (23:33 +0000)]
[CMake] Promote extension warnings to errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158176
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Manman Ren [Thu, 7 Jun 2012 22:39:10 +0000 (22:39 +0000)]
X86: optimize generated code for integer ABS
This patch will generate the following for integer ABS:
movl %edi, %eax
negl %eax
cmovll %edi, %eax
INSTEAD OF
movl %edi, %ecx
sarl $31, %ecx
leal (%rdi,%rcx), %eax
xorl %ecx, %eax
There exists a target-independent DAG combine for integer ABS, which converts
integer ABS to sar+add+xor. For X86, we match this pattern back to neg+cmov.
This is implemented in PerformXorCombine.
rdar://
10695237
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158175
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Michael J. Spencer [Thu, 7 Jun 2012 21:34:31 +0000 (21:34 +0000)]
[CMake] Order MSVC warnings numerically.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158171
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Michael J. Spencer [Thu, 7 Jun 2012 21:34:15 +0000 (21:34 +0000)]
[CMake] Adjust MSVC warnings.
Remove /Wall from LLVM_ENABLE_WARNINGS (it's useless) and promote 4239
to a level 1 warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158170
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Nadav Rotem [Thu, 7 Jun 2012 20:53:48 +0000 (20:53 +0000)]
Do not optimize the used bits of the x86 vselect condition operand, when the condition operand is a vector of 1-bit predicates.
This may happen on MIC devices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158168
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Nadav Rotem [Thu, 7 Jun 2012 20:28:57 +0000 (20:28 +0000)]
Fix a bug in FoldSelectOpOp. Bitcast ops may change the number of vector elements, which may disagree with the select condition type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158166
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Andrew Trick [Thu, 7 Jun 2012 19:42:04 +0000 (19:42 +0000)]
Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158164
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Andrew Trick [Thu, 7 Jun 2012 19:42:00 +0000 (19:42 +0000)]
ARM getOperandLatency rewrite.
Match expectations of the new latency API. Cleanup and make the logic consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158163
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Andrew Trick [Thu, 7 Jun 2012 19:41:58 +0000 (19:41 +0000)]
ARM getOperandLatency should return -1 for unknown, consistent with API
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158162
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Andrew Trick [Thu, 7 Jun 2012 19:41:55 +0000 (19:41 +0000)]
Fix ARM getInstrLatency logic to work with the current API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158161
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Manman Ren [Thu, 7 Jun 2012 19:27:33 +0000 (19:27 +0000)]
PR13046: we can't replace usage of SUB with CMP in the lowering phase.
It will cause assertion failure later on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158160
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Rafael Espindola [Thu, 7 Jun 2012 18:39:19 +0000 (18:39 +0000)]
Use a base register instead of an index register with the local dynamic model.
Fixes pr13048.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158158
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Pete Cooper [Thu, 7 Jun 2012 17:41:39 +0000 (17:41 +0000)]
Move terminator machine verification to check MachineBasicBlock::instr_iterator instead of MBB::iterator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158154
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Pete Cooper [Thu, 7 Jun 2012 04:43:52 +0000 (04:43 +0000)]
Add internal read flags to MachineInstrBuilder and hook them into the MachineOperand flag of the same name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158137
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Meador Inge [Thu, 7 Jun 2012 01:02:13 +0000 (01:02 +0000)]
Adding a missing -S to the opt invocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158128
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Manman Ren [Thu, 7 Jun 2012 00:42:47 +0000 (00:42 +0000)]
X86: replace SUB with CMP if possible
This patch will optimize the following
movq %rdi, %rax
subq %rsi, %rax
cmovsq %rsi, %rdi
movq %rdi, %rax
to
cmpq %rsi, %rdi
cmovsq %rsi, %rdi
movq %rdi, %rax
Perform this optimization if the actual result of SUB is not used.
rdar:
11540023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158126
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Bill Wendling [Wed, 6 Jun 2012 23:53:23 +0000 (23:53 +0000)]
Spell optimization name correclty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158123
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Manman Ren [Wed, 6 Jun 2012 23:53:03 +0000 (23:53 +0000)]
Revert r157755.
The commit is intended to fix rdar://
11540023.
It is implemented as part of peephole optimization. We can actually implement
this in the SelectionDAG lowering phase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158122
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Bill Wendling [Wed, 6 Jun 2012 23:36:22 +0000 (23:36 +0000)]
Another testcase for r156548.
<rdar://problem/
10889741>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158121
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Michael J. Spencer [Wed, 6 Jun 2012 23:34:10 +0000 (23:34 +0000)]
[llvm-nm] Update documentation to cover object file support and arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158120
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Jakob Stoklund Olesen [Wed, 6 Jun 2012 22:34:30 +0000 (22:34 +0000)]
Properly verify liveness with bundled machine instructions.
Bundles should be treated as one atomic transaction when checking
liveness. That is how the register allocator (and VLIW targets) treats
bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158116
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Benjamin Kramer [Wed, 6 Jun 2012 20:45:10 +0000 (20:45 +0000)]
Add accessors for all private members of DisasmContext.
LLVM should be -Wunused-private-field clean now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158103
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Andrew Trick [Wed, 6 Jun 2012 20:29:31 +0000 (20:29 +0000)]
Move RegisterClassInfo.h.
Allow targets to access this API. It's required for RegisterPressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158102
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Benjamin Kramer [Wed, 6 Jun 2012 20:23:00 +0000 (20:23 +0000)]
Remove dead private member variables from gtest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158101
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Andrew Trick [Wed, 6 Jun 2012 19:47:35 +0000 (19:47 +0000)]
Move RegisterPressure.h.
Make it a general utility for use by Targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158097
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Benjamin Kramer [Wed, 6 Jun 2012 19:47:08 +0000 (19:47 +0000)]
Round 2 of dead private variable removal.
LLVM is now -Wunused-private-field clean except for
- lib/MC/MCDisassembler/Disassembler.h. Not sure why it keeps all those unaccessible fields.
- gtest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158096
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Benjamin Kramer [Wed, 6 Jun 2012 18:25:08 +0000 (18:25 +0000)]
Remove unused private fields found by clang's new -Wunused-private-field.
There are some that I didn't remove this round because they looked like
obvious stubs. There are dead variables in gtest too, they should be
fixed upstream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090
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Chad Rosier [Wed, 6 Jun 2012 17:37:40 +0000 (17:37 +0000)]
Add support for dynamic stack realignment in the presence of dynamic allocas on
X86.
rdar://
11496434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158087
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Chad Rosier [Wed, 6 Jun 2012 17:22:40 +0000 (17:22 +0000)]
Fix combine of uno && ord -> false so that the ordering of the fcmps doesn't
matter.
rdar://
11579835
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158084
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Jakob Stoklund Olesen [Wed, 6 Jun 2012 16:22:41 +0000 (16:22 +0000)]
Remove dead debug option -disable-rematerialization.
Remat has been stable for years, and it isn't done by
LiveIntervalAnalysis any longer. (See LiveRangeEdit).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158079
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Duncan Sands [Wed, 6 Jun 2012 14:53:10 +0000 (14:53 +0000)]
Grab-bag of reassociate tweaks. Unify handling of dead instructions and
instructions to reoptimize. Exploit this to more systematically eliminate
dead instructions (this isn't very useful in practice but is convenient for
analysing some testcase I am working on). No need for WeakVH any more: use
an AssertingVH instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158073
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Wed, 6 Jun 2012 13:53:41 +0000 (13:53 +0000)]
Stop leaking RegScavengers from TailDuplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158069
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Richard Barton [Wed, 6 Jun 2012 09:12:53 +0000 (09:12 +0000)]
Correct decoder for T1 conditional B encoding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158055
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Duncan Sands [Wed, 6 Jun 2012 07:39:39 +0000 (07:39 +0000)]
Add a new broken compiler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158053
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Craig Topper [Wed, 6 Jun 2012 06:45:27 +0000 (06:45 +0000)]
Mark several instructions SSE2 instead of SSE3 as they should be.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158049
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Justin Holewinski [Wed, 6 Jun 2012 03:11:20 +0000 (03:11 +0000)]
Fix gtest build issue on Visual Studio 2012 RC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158046
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Chad Rosier [Wed, 6 Jun 2012 02:12:17 +0000 (02:12 +0000)]
Remove extraneous CHECK-NOTs from previous commit and add a new test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158045
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Chad Rosier [Wed, 6 Jun 2012 01:38:32 +0000 (01:38 +0000)]
FileCheckize this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158044
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Jakob Stoklund Olesen [Tue, 5 Jun 2012 23:57:30 +0000 (23:57 +0000)]
Move LiveUnionArray into LiveIntervalUnion.h
It is useful outside RegAllocBase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158041
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Jakob Stoklund Olesen [Tue, 5 Jun 2012 23:07:19 +0000 (23:07 +0000)]
Don't print register names in LiveIntervalUnion::print().
Soon we'll be making LiveIntervalUnions for register units as well.
This was the only place using the RepReg member, so just remove it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158038
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Matt Beaumont-Gay [Tue, 5 Jun 2012 23:00:03 +0000 (23:00 +0000)]
Suppress -Wunused-variable in -Asserts build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158037
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Jakob Stoklund Olesen [Tue, 5 Jun 2012 22:51:54 +0000 (22:51 +0000)]
Simplify LiveInterval::print().
Don't print out the register number and spill weight, making the TRI
argument unnecessary.
This allows callers to interpret the reg field. It can currently be a
virtual register, a physical register, a spill slot, or a register unit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158031
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Jakob Stoklund Olesen [Tue, 5 Jun 2012 22:02:15 +0000 (22:02 +0000)]
Add experimental support for register unit liveness.
Instead of computing a live interval per physreg, LiveIntervals can
compute live intervals per register unit. This makes impossible the
confusing situation where aliasing registers could have overlapping live
intervals. It should also make fixed interferernce checking cheaper
since registers have fewer register units than aliases.
Live intervals for regunits are computed on demand, using MRI use-def
chains and the new LiveRangeCalc class. Only regunits live in to ABI
blocks are precomputed during LiveIntervals::runOnMachineFunction().
The regunit liveness computations don't depend on LiveVariables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158029
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Jakob Stoklund Olesen [Tue, 5 Jun 2012 21:54:09 +0000 (21:54 +0000)]
Implement LiveRangeCalc::extendToUses() and createDeadDefs().
These LiveRangeCalc methods are to be used when computing a live range
from scratch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158027
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Andrew Trick [Tue, 5 Jun 2012 21:44:23 +0000 (21:44 +0000)]
MachineInstr::eraseFromParent fix for removing bundled instrs.
Patch by Ivan Llopard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158025
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