Simon Pilgrim [Tue, 3 Feb 2015 22:39:28 +0000 (22:39 +0000)]
Fixed unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228054
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Colin LeMahieu [Tue, 3 Feb 2015 22:09:51 +0000 (22:09 +0000)]
[Hexagon] Marking a bunch of non-encoded instructions with isCodeGenOnly = 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228050
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Hans Wennborg [Tue, 3 Feb 2015 22:08:20 +0000 (22:08 +0000)]
[CMake] add_llvm_library: don't use .imp suffix for import libraries on Windows (PR22334)
This was added in r188351 to fix a naming conflict between the
profile_rt-static and profile_rt-shared who both ended up in
lib/profile_rt.lib.
The change also affected other libraries (like libclang), and
users are reporting that they find it surprising that there's
no longer a libclang.lib. Since the profile_rt naming conflict
doesn't seem to exist any more, I think we can remove this.
Differential Revision: http://reviews.llvm.org/D7391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228049
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Arnaud A. de Grandmaison [Tue, 3 Feb 2015 22:02:45 +0000 (22:02 +0000)]
[PBQP] Constify Graph::getEdgeNode1Id and Graph::getEdgeNode2Id
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228048
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Simon Pilgrim [Tue, 3 Feb 2015 21:58:29 +0000 (21:58 +0000)]
[X86][SSE] psrl(w/d/q) and psll(w/d/q) bit shifts for SSE2
Patch to match cases where shuffle masks can be reduced to bit shifts. Similar to byte shift shuffle matching from D5699.
Differential Revision: http://reviews.llvm.org/D6649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228047
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Bill Schmidt [Tue, 3 Feb 2015 21:58:23 +0000 (21:58 +0000)]
[PowerPC] Implement the vpopcnt instructions for POWER8
Patch by Kit Barton.
Add the vector population count instructions for byte, halfword, word,
and doubleword sizes. There are two major changes here:
PPCISelLowering.cpp: Make CTPOP legal for vector types.
PPCRegisterInfo.td: Added v2i64 to the VRRC register
definition. This is needed for the doubleword variations of the
integer ops that were added in P8.
Test Plan
Test the instruction vpcnt* encoding/decoding in ppc64-encoding-vmx.s
Test the generation of the vpopcnt instructions for various vector
data types. When adding the v2i64 type to the Vector Register set, I
also needed to add the appropriate bit conversion patterns between
v2i64 and the existing vector types. Testing for these conversions
were also added in the test case by passing a different vector type as
a parameter into the test functions. There is also a run step that
will ensure the vpopcnt instructions are generated when the vsx
feature is disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228046
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Kostya Serebryany [Tue, 3 Feb 2015 21:57:32 +0000 (21:57 +0000)]
[fuzzer] Add proper dependensices to the fuzzer tests
Summary: Make sure that FileCheck is built when running check-fuzzer
Test Plan:
run on bot:
lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fuzzer
Reviewers: samsonov
Reviewed By: samsonov
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228045
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Chandler Carruth [Tue, 3 Feb 2015 21:56:28 +0000 (21:56 +0000)]
[x86] Add two truly horrific test cases for the new vector shuffle
lowering. I'm prepping patches to improve these, and this will let the
delta of those patches show the improvement. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228044
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Chandler Carruth [Tue, 3 Feb 2015 21:56:24 +0000 (21:56 +0000)]
[x86] Update the indent and layout of some tests in this file. NFC
This is just to remove voise from using the update_llc_test_checks
script.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228043
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Duncan P. N. Exon Smith [Tue, 3 Feb 2015 21:56:01 +0000 (21:56 +0000)]
AsmParser: Recognize DW_TAG_* constants
Recognize `DW_TAG_` constants in assembly, and output it by default for
`GenericDebugNode`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228042
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Duncan P. N. Exon Smith [Tue, 3 Feb 2015 21:54:14 +0000 (21:54 +0000)]
IR: Assembly and bitcode for GenericDebugNode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228041
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Marek Olsak [Tue, 3 Feb 2015 21:53:27 +0000 (21:53 +0000)]
R600/SI: Remove the -CHECK suffix from all FileCheck prefixes in LIT tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228040
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Marek Olsak [Tue, 3 Feb 2015 21:53:08 +0000 (21:53 +0000)]
R600/SI: Remove useless patterns in VALU which are already covered by SALU
Also remove hasPostISelHook=1 from V_LSHL_B32. It's defined by InstSI already.
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228039
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Marek Olsak [Tue, 3 Feb 2015 21:53:05 +0000 (21:53 +0000)]
R600/SI: Rewrite VOP1InstSI to contain a pseudo and _si opcode
What this does is that if you accidentally select these instructions on VI,
the code generation will fail, because the pseudo -> _vi mapping will be
undefined.
The idea is to be able to catch possible future bugs easily.
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228038
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Marek Olsak [Tue, 3 Feb 2015 21:53:01 +0000 (21:53 +0000)]
R600/SI: Fix B64 VALU shifts on VI
SI only has standard versions. VI only has REV versions.
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228037
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Justin Bogner [Tue, 3 Feb 2015 21:35:36 +0000 (21:35 +0000)]
InstrProf: Remove CoverageMapping::HasCodeBefore, it isn't used
It's not entirely clear to me what this field was meant for, but it's
always false. Remove it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228034
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Chandler Carruth [Tue, 3 Feb 2015 21:26:45 +0000 (21:26 +0000)]
[x86] Tweak my update script to use test case function names starting
with 'stress' to indicate that the specific output isn't interesting and
relax them to only check the last instruction (a ret).
I've updated the one test case that really uses this to name the one
'stress_test' which was actually producing output we can directly check.
With this, the script doesn't introduce noise when run over the v16 test
file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228033
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Duncan P. N. Exon Smith [Tue, 3 Feb 2015 21:16:49 +0000 (21:16 +0000)]
Support: Add string => unsigned mapping for DW_TAG
Add `dwarf::getTag()` to translate from `StringRef` to `unsigned`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228031
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Duncan P. N. Exon Smith [Tue, 3 Feb 2015 21:13:16 +0000 (21:13 +0000)]
Support: Re-implement dwarf::TagString() using a .def file, NFC
Also re-implements the `dwarf::Tag` enumerator. I've moved the mock
tags into the enumerator since there's no other way to do this. Really
they shouldn't be used at all (they're just a hack to identify
`MDNode`s, but we have a class hierarchy for that now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228030
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Duncan P. N. Exon Smith [Tue, 3 Feb 2015 21:08:33 +0000 (21:08 +0000)]
Support: Stop stringifying DW_TAG_{lo,hi}_user
`dwarf::TagString()` shouldn't stringify `DW_TAG_lo_user` or
`DW_TAG_hi_user`. These aren't actual tags; they're markers for the
edge of vendor-specific tag regions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228029
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Simon Pilgrim [Tue, 3 Feb 2015 20:54:01 +0000 (20:54 +0000)]
Fixed signed/unsigned comparison warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228027
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Colin LeMahieu [Tue, 3 Feb 2015 20:40:52 +0000 (20:40 +0000)]
[Hexagon] Converting XTYPE/SHIFT intrinsics. Cleaning out old intrinsic patterns and updating tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228026
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 3 Feb 2015 20:38:52 +0000 (20:38 +0000)]
Fixed unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228025
91177308-0d34-0410-b5e6-
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Daniel Berlin [Tue, 3 Feb 2015 20:37:08 +0000 (20:37 +0000)]
Allow PRE to insert no-cost phi nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228024
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Simon Pilgrim [Tue, 3 Feb 2015 20:09:18 +0000 (20:09 +0000)]
[X86][SSE] Added general integer shuffle matching for MOVQ instruction
This patch adds general shuffle pattern matching for the MOVQ zero-extend instruction (copy lower 64bits, zero upper) for all 128-bit integer vectors, it is added as a fallback test in lowerVectorShuffleAsZeroOrAnyExtend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228022
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Colin LeMahieu [Tue, 3 Feb 2015 19:43:59 +0000 (19:43 +0000)]
[Hexagon] Updating XTYPE/PRED intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228019
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Kostya Serebryany [Tue, 3 Feb 2015 19:42:05 +0000 (19:42 +0000)]
[fuzzer] update the include line to use the new header name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228018
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Jingyue Wu [Tue, 3 Feb 2015 19:37:06 +0000 (19:37 +0000)]
Add straight-line strength reduction to LLVM
Summary:
Straight-line strength reduction (SLSR) is implemented in GCC but not yet in
LLVM. It has proven to effectively simplify statements derived from an unrolled
loop, and can potentially benefit many other cases too. For example,
LLVM unrolls
#pragma unroll
foo (int i = 0; i < 3; ++i) {
sum += foo((b + i) * s);
}
into
sum += foo(b * s);
sum += foo((b + 1) * s);
sum += foo((b + 2) * s);
However, no optimizations yet reduce the internal redundancy of the three
expressions:
b * s
(b + 1) * s
(b + 2) * s
With SLSR, LLVM can optimize these three expressions into:
t1 = b * s
t2 = t1 + s
t3 = t2 + s
This commit is only an initial step towards implementing a series of such
optimizations. I will implement more (see TODO in the file commentary) in the
near future. This optimization is enabled for the NVPTX backend for now.
However, I am more than happy to push it to the standard optimization pipeline
after more thorough performance tests.
Test Plan: test/StraightLineStrengthReduce/slsr.ll
Reviewers: eliben, HaoLiu, meheff, hfinkel, jholewinski, atrick
Reviewed By: jholewinski, atrick
Subscribers: karthikthecool, jholewinski, llvm-commits
Differential Revision: http://reviews.llvm.org/D7310
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228016
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Colin LeMahieu [Tue, 3 Feb 2015 19:36:59 +0000 (19:36 +0000)]
[Hexagon] Updating XTYPE/PERM intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228015
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Simon Pilgrim [Tue, 3 Feb 2015 19:34:09 +0000 (19:34 +0000)]
[X86][AVX2] Enabled shuffle matching for the AVX2 zero extension (128bit -> 256bit) vpmovzx* instructions.
Differential Revision: http://reviews.llvm.org/D7251
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228014
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Rafael Espindola [Tue, 3 Feb 2015 19:25:53 +0000 (19:25 +0000)]
Fix duplicated symbol error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228012
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Rafael Espindola [Tue, 3 Feb 2015 19:20:26 +0000 (19:20 +0000)]
Fix typo in test/CodeGen/X86/sibcall.ll (pr22331).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228011
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Colin LeMahieu [Tue, 3 Feb 2015 19:15:11 +0000 (19:15 +0000)]
[Hexagon] Adding missing vector multiply instruction encodings. Converting multiply intrinsics and updating tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228010
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Sanjay Patel [Tue, 3 Feb 2015 18:54:00 +0000 (18:54 +0000)]
Merge consecutive 16-byte loads into one 32-byte load (PR22329)
This patch detects consecutive vector loads using the existing
EltsFromConsecutiveLoads() logic. This fixes:
http://llvm.org/bugs/show_bug.cgi?id=22329
This patch effectively reverts the tablegen additions of D6492 /
http://reviews.llvm.org/rL224344 ...which in hindsight were a horrible hack.
The test cases that were added with that patch are simply modified to load
from varying offsets of a base pointer. These loads did not match the existing
tablegen patterns.
A happy side effect of doing this optimization earlier is that we can now fold
the load into a math op where possible; this is shown in some of the updated
checks in the test file.
Differential Revision: http://reviews.llvm.org/D7303
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228006
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Sanjay Patel [Tue, 3 Feb 2015 18:47:32 +0000 (18:47 +0000)]
remove variable names from comments; NFC
I didn't bother to fix the self-referential definitions and grammar
because my eyes started to bleed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228004
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Manman Ren [Tue, 3 Feb 2015 18:39:15 +0000 (18:39 +0000)]
[LTO API] split lto_codegen_compile to lto_codegen_optimize and
lto_codegen_compile_optimized. Also add lto_api_version.
Before this commit, we can only dump the optimized bitcode after running
lto_codegen_compile, but it includes some impacts of running codegen passes,
one example is StackProtector pass. We will get assertion failure when running
llc on the optimized bitcode, because StackProtector is effectively run twice.
After splitting lto_codegen_compile, the linker can choose to dump the bitcode
before running lto_codegen_compile_optimized.
lto_api_version is added so ld64 can check for runtime-availability of the new
API.
rdar://
19565500
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228000
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Hans Wennborg [Tue, 3 Feb 2015 18:31:29 +0000 (18:31 +0000)]
Fix ProgramFiles path for 64-bit Windows installer
If we are building an 64bit installer on Windows we have to adjust the
Program Files path otherwise it uses the wrong Program Files (x86)
directory. Related CMake bug report
http://public.kitware.com/Bug/view.php?id=14211
Patch by Ismail Dönmez!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227999
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Colin LeMahieu [Tue, 3 Feb 2015 18:16:28 +0000 (18:16 +0000)]
[Hexagon] Converting complex number intrinsics and adding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227995
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Colin LeMahieu [Tue, 3 Feb 2015 18:01:45 +0000 (18:01 +0000)]
[Hexagon] Adding vector intrinsics for alu32/alu and xtype/alu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227993
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Adam Nemet [Tue, 3 Feb 2015 17:59:53 +0000 (17:59 +0000)]
[LoopVectorize] Fix rebase glitch in r227751
LoopVectorizationLegality::{getNumLoads,getNumStores} should forward to
LoopAccessAnalysis now.
Thanks to Takumi for noticing this!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227992
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Jingyue Wu [Tue, 3 Feb 2015 17:57:38 +0000 (17:57 +0000)]
Remove usernames from TODOs, NFC
making the style consistent with the rest
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227991
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Marek Olsak [Tue, 3 Feb 2015 17:38:12 +0000 (17:38 +0000)]
R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VI
This can happen when a REV instruction is commuted.
The trick is not to define the _vi versions of instructions, which has these
consequences:
- code generation will always fail if a pseudo cannot be lowered
(very useful to catch bugs where an unsupported instruction somehow makes
it to the printer)
- ability to query if a pseudo can be lowered, which is done in commuteOpcode
to prevent REV from commuting to non-REV on VI
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227990
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Marek Olsak [Tue, 3 Feb 2015 17:38:05 +0000 (17:38 +0000)]
R600/SI: Remove VOP2_REV definitions from target-specific instructions
The getCommute* functions are only used with pseudos, so this commit doesn't
change anything.
The issue with missing non-rev versions of shift instructions on VI will fixed
separately.
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227989
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Marek Olsak [Tue, 3 Feb 2015 17:38:01 +0000 (17:38 +0000)]
R600/SI: Trivial instruction definition corrections for VI (v2)
- V_MAC_LEGACY_F32 exists on VI, but it's VOP3-only.
- Define CVT_PK opcodes which are different between SI and VI. These are
unused. The idea is to define all chip differences.
v2: keep V_MUL_LO_U32
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227988
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Marek Olsak [Tue, 3 Feb 2015 17:37:57 +0000 (17:37 +0000)]
R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2
These are VOP2 on SI and VOP3 on VI, and their pseudos are neither, which can
be a problem. In order to make isVOP2 and isVOP3 queries behave as expected,
the encoding must be determined first.
This doesn't fix any known issue, but better safe than sorry.
v2: add and use getMCOpcodeFromPseudo
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227987
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Marek Olsak [Tue, 3 Feb 2015 17:37:52 +0000 (17:37 +0000)]
R600/SI: Fix dependency between instruction writing M0 and S_SENDMSG on VI (v2)
This fixes a hang when using an empty geometry shader.
v2: - don't add s_nop when followed by s_waitcnt
- comestic changes
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227986
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Sanjay Patel [Tue, 3 Feb 2015 17:13:04 +0000 (17:13 +0000)]
Fix program crashes due to alignment exceptions generated for SSE memop instructions (PR22371).
r224330 introduced a bug by misinterpreting the "FeatureVectorUAMem" bit.
The commit log says that change did not affect anything, but that's not correct.
That change allowed SSE instructions to have unaligned mem operands folded into
math ops, and that's not allowed in the default specification for any SSE variant.
The bug is exposed when compiling for an AVX-capable CPU that had this feature
flag but without enabling AVX codegen. Another mistake in r224330 was not adding
the feature flag to all AVX CPUs; the AMD chips were excluded.
This is part of the fix for PR22371 ( http://llvm.org/bugs/show_bug.cgi?id=22371 ).
This feature bit is SSE-specific, so I've renamed it to "FeatureSSEUnalignedMem".
Changed the existing test case for the feature bit to reflect the new name and
renamed the test file itself to better reflect the feature.
Added runs to fold-vex.ll to check for the failing codegen.
Note that the feature bit is not set by default on any CPU because it may require a
configuration register setting to enable the enhanced unaligned behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227983
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Bill Schmidt [Tue, 3 Feb 2015 16:57:38 +0000 (16:57 +0000)]
Disable 32-bit tests in tls-pic.ll until they can be repaired
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227981
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Bill Schmidt [Tue, 3 Feb 2015 16:33:55 +0000 (16:33 +0000)]
Further revise too-restrictive test CodeGen/PowerPC/tls-pic.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227980
91177308-0d34-0410-b5e6-
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Bill Schmidt [Tue, 3 Feb 2015 16:29:52 +0000 (16:29 +0000)]
Further revise too-restrictive test CodeGen/PowerPC/tls-pic.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227978
91177308-0d34-0410-b5e6-
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Bill Schmidt [Tue, 3 Feb 2015 16:24:05 +0000 (16:24 +0000)]
Revise too-restrictive test CodeGen/PowerPC/tls-pic.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227977
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Bill Schmidt [Tue, 3 Feb 2015 16:16:01 +0000 (16:16 +0000)]
[PowerPC] Yet another approach to __tls_get_addr
This patch is a third attempt to properly handle the local-dynamic and
global-dynamic TLS models.
In my original implementation, calls to __tls_get_addr were hidden
from view until the asm-printer phase, at which point the underlying
branch-and-link instruction was created with proper relocations. This
mostly worked well, but I used some repellent techniques to ensure
that the TLS_GET_ADDR nodes at the SD and MI levels correctly received
input from GPR3 and produced output into GPR3. This proved to work
badly in the presence of multiple TLS variable accesses, with the
copies to and from GPR3 being scheduled incorrectly and generally
creating havoc.
In r221703, I addressed that problem by representing the calls to
__tls_get_addr as true calls during instruction lowering. This had
the advantage of removing all of the bad hacks and relying on the
existing call machinery to properly glue the copies in place. It
looked like this was going to be the right way to go.
However, as a side effect of the recent discovery of problems with
linker optimizations for TLS, we discovered cases of suboptimal code
generation with this strategy. The problem comes when tls_get_addr is
called for the same address, and there is a resulting CSE
opportunity. It turns out that in such cases MachineCSE will common
the addis/addi instructions that set up the input value to
tls_get_addr, but will not common the calls themselves. MachineCSE
does not have any machinery to common idempotent calls. This is
perfectly sensible, since presumably this would be done at the IR
level, and introducing calls in the back end isn't commonplace. In
any case, we end up with two calls to __tls_get_addr when one would
suffice, and that isn't good.
I presumed that the original design would have allowed commoning of
the machine-specific nodes that hid the __tls_get_addr calls, so as
suggested by Ulrich Weigand, I went back to that design and cleaned it
up so that the copies were properly held together by glue
nodes. However, it turned out that this didn't work either...the
presence of copies to physical registers kept the machine-specific
nodes from being commoned also.
All of which leads to the design presented here. This is a return to
the original design, except that no attempt is made to introduce
copies to and from GPR3 during instruction lowering. Virtual registers
are used until prior to register allocation. At that point, a special
pass is run that identifies the machine-specific nodes that hide the
tls_get_addr calls and introduces the copies to and from GPR3 around
them. The register allocator then coalesces these copies away. With
this design, MachineCSE succeeds in commoning tls_get_addr calls where
possible, and we get nice optimal code generation (better than GCC at
the moment, which does not common these calls).
One additional problem must be dealt with: After introducing the
mentions of the physical register GPR3, the aggressive anti-dependence
breaker sees opportunities to improve scheduling by selecting a
different register instead. Flags must be used on the instruction
descriptions to tell the anti-dependence breaker to keep its hands in
its pockets.
One thing missing from the original design was recording a definition
of the link register on the GET_TLS_ADDR nodes. Doing this was found
to be insufficient to force a stack frame to be created, which led to
looping behavior because two different LR values were stored at the
same address. This appears to have been an oversight in
PPCFrameLowering::determineFrameLayout(), which is repaired here.
Because MustSaveLR() returns true for calls to builtin_return_address,
this changed the expected behavior of
test/CodeGen/PowerPC/retaddr2.ll, which now stacks a frame but
formerly did not. I've fixed the test case to reflect this.
There are existing TLS tests to catch regressions; the checks in
test/CodeGen/PowerPC/tls-store2.ll proved to be too restrictive in the
face of instruction scheduling with these changes, so I fixed that
up.
I've added a new test case based on the PrettyStackTrace module that
demonstrated the original problem. This checks that we get correct
code generation and that CSE of the calls to __get_tls_addr has taken
place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227976
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Sanjay Patel [Tue, 3 Feb 2015 15:37:18 +0000 (15:37 +0000)]
Improve test to actually check for a folded load.
This test was checking for lack of a "movaps" (an aligned load)
rather than a "movups" (an unaligned load). It also included
a store which complicated the checking.
Add specific CPU runs to prevent subtarget feature flag overrides
from inhibiting this optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227972
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Bruno Cardoso Lopes [Tue, 3 Feb 2015 14:46:49 +0000 (14:46 +0000)]
[X86][MMX] Improve transfer from mmx to i32
Improve EXTRACT_VECTOR_ELT DAG combine to catch conversion patterns
between x86mmx and i32 with more layers of indirection.
Before:
movq2dq %mm0, %xmm0
movd %xmm0, %eax
After:
movd %mm0, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227969
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Renato Golin [Tue, 3 Feb 2015 11:20:45 +0000 (11:20 +0000)]
Adding AArch64 support to ASan instrumentation
For the time being, it is still hardcoded to support only the 39 VA bits
variant, I plan to work on supporting 42 and 48 VA bits variants, but I
don't have access to such hardware at the moment.
Patch by Chrystophe Lyon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227965
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Craig Topper [Tue, 3 Feb 2015 11:03:57 +0000 (11:03 +0000)]
[X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax. Also make them the default output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227963
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Craig Topper [Tue, 3 Feb 2015 11:03:43 +0000 (11:03 +0000)]
[X86] Add Requires[In64BitMode] around MOVSX64rr32/MOVSX64rm32. This makes it more strictly mutexed with the ARPL instruction 32-bit mode. Helps with some disassembler changes I'm experimenting with. Should be NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227962
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Eric Christopher [Tue, 3 Feb 2015 07:22:52 +0000 (07:22 +0000)]
Only access TLOF via the TargetMachine, not TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227949
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Eric Christopher [Tue, 3 Feb 2015 06:40:22 +0000 (06:40 +0000)]
Define a runOnMachineFunction for the Hexagon AsmPrinter and
use it to initialize the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227948
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Eric Christopher [Tue, 3 Feb 2015 06:40:19 +0000 (06:40 +0000)]
Migrate away from using a Subtarget except for the one place we want
to use it. Use the triple to determine OS format bits at the module
level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227947
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Lang Hames [Tue, 3 Feb 2015 06:14:06 +0000 (06:14 +0000)]
[PBQP Regalloc] Pre-spill vregs that have no legal physregs.
The PBQP::RegAlloc::MatrixMetadata class assumes that matrices have at least two
rows/columns (for the spill option plus at least one physreg). This patch
ensures that that invariant is met by pre-spilling vregs that have no physreg
options so that no node (and no corresponding edges) need be added to the PBQP
graph.
This fixes a bug in an out-of-tree target that was identified by Jonas Paulsson.
Thanks for tracking this down Jonas!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227942
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NAKAMURA Takumi [Tue, 3 Feb 2015 03:55:06 +0000 (03:55 +0000)]
Resurrect initializers for NumLoads and NumStores in LoopVectorizationLegality to suppress undefined behavior.
FIXME: Shall they be managed in LAA?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227940
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Andrew Kaylor [Tue, 3 Feb 2015 03:08:25 +0000 (03:08 +0000)]
Really, really, really don't build llvm-pdbdump on MSVC < 2013.
There was a typo in the last attempt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227937
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Rafael Espindola [Tue, 3 Feb 2015 01:53:03 +0000 (01:53 +0000)]
Propagate a better error message to the C api.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227934
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Rafael Espindola [Tue, 3 Feb 2015 00:49:57 +0000 (00:49 +0000)]
Use a non-fatal diag handler in the C API. FIxes PR22368.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227903
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Justin Bogner [Tue, 3 Feb 2015 00:20:11 +0000 (00:20 +0000)]
InstrProf: Simplify RawCoverageMappingReader's API slightly
This is still kind of a weird API, but dropping the (partial) update
of the passed in CoverageMappingRecord makes it a little easier to
understand and use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227900
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Justin Bogner [Tue, 3 Feb 2015 00:00:00 +0000 (00:00 +0000)]
InstrProf: Simplify some logic by using ArrayRef::slice (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227898
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Alex Rosenberg [Mon, 2 Feb 2015 23:58:54 +0000 (23:58 +0000)]
Revert part of r227437 as it was unnecessary. Thanks to echristo for
pointing this out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227897
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Eric Christopher [Mon, 2 Feb 2015 23:03:45 +0000 (23:03 +0000)]
Migrate to using the subtarget on the machine function and update
all uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227891
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Eric Christopher [Mon, 2 Feb 2015 23:03:43 +0000 (23:03 +0000)]
Use the function template getSubtarget off of the machine function,
and use it in all locations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227890
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Eric Christopher [Mon, 2 Feb 2015 22:40:56 +0000 (22:40 +0000)]
Use the cached subtarget on the MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227885
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Eric Christopher [Mon, 2 Feb 2015 22:40:54 +0000 (22:40 +0000)]
Remove dead header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227884
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Eric Christopher [Mon, 2 Feb 2015 22:40:53 +0000 (22:40 +0000)]
Remove dead code in the HexagonMCInst classes. This also fixes
a layering violation in the port and removes calls to getSubtargetImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227883
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Eric Christopher [Mon, 2 Feb 2015 22:40:51 +0000 (22:40 +0000)]
80-col fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227882
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Justin Bogner [Mon, 2 Feb 2015 22:38:39 +0000 (22:38 +0000)]
InstrProf: Remove an unused header (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227881
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Eric Christopher [Mon, 2 Feb 2015 22:28:48 +0000 (22:28 +0000)]
Remove dead code in the HexagonMCInst classes. This also fixes
a layering violation in the port and removes calls to getSubtargetImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227880
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Eric Christopher [Mon, 2 Feb 2015 22:28:46 +0000 (22:28 +0000)]
80-col fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227879
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Eric Christopher [Mon, 2 Feb 2015 22:28:44 +0000 (22:28 +0000)]
Remove unused class variables and update all callers/uses from
the HexagonSplitTFRCondSet pass. Use the subtarget off the machine
function at the same time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227878
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Eric Christopher [Mon, 2 Feb 2015 22:11:43 +0000 (22:11 +0000)]
Migrate the HexagonSplitConst32AndConst64 pass from TargetMachine
based getSubtarget to the one cached on the MachineFunction.
Remove unused class variables and update all callers/uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227874
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Eric Christopher [Mon, 2 Feb 2015 22:11:42 +0000 (22:11 +0000)]
Remove #if'd code and update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227873
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Eric Christopher [Mon, 2 Feb 2015 22:11:40 +0000 (22:11 +0000)]
Move HexagonMachineScheduler to use the subtarget off of the
MachineFunction and update all uses accordingly including
VLIWResourceModel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227872
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Eric Christopher [Mon, 2 Feb 2015 22:11:36 +0000 (22:11 +0000)]
Cache and use the subtarget that owns the target lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227871
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Bruno Cardoso Lopes [Mon, 2 Feb 2015 22:00:48 +0000 (22:00 +0000)]
[X86][MMX] Add tests for MMX extract element
LLVM ToT produces poor MMX code compared to 3.5. However, part of the previous
functionality can be achieved by using -x86-experimental-vector-widening-legalization.
Add tests to be sure we don't regress again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227869
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Bruno Cardoso Lopes [Mon, 2 Feb 2015 21:56:11 +0000 (21:56 +0000)]
[X86][MMX] Cleanup shuffle, bitcast and insert element tests
- Merge MMX arg passing test files
- Merge MMX bitcast, insert elt and shuffle tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227867
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Alexei Starovoitov [Mon, 2 Feb 2015 21:24:27 +0000 (21:24 +0000)]
bpf: Use the getSubtarget call off of the MachineFunction rather than the TargetMachine
Summary:
Hi Eric,
this patch cleans up the layering violation that you're fixing across backends.
Anything else I need to fix on bpf backend side?
Thanks
Reviewers: echristo
Reviewed By: echristo
Differential Revision: http://reviews.llvm.org/D7355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227865
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Jingyue Wu [Mon, 2 Feb 2015 20:41:11 +0000 (20:41 +0000)]
Resurrect the assertion removed by r227717
Summary: MSVC can compile "LoopID->getOperand(0) == LoopID" when LoopID is MDNode*.
Test Plan: no regression
Reviewers: mkuper
Subscribers: jholewinski, llvm-commits
Differential Revision: http://reviews.llvm.org/D7327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227853
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Duncan P. N. Exon Smith [Mon, 2 Feb 2015 20:20:56 +0000 (20:20 +0000)]
Fix the -Werror build, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227849
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Duncan P. N. Exon Smith [Mon, 2 Feb 2015 20:01:03 +0000 (20:01 +0000)]
IR: Allow GenericDebugNode construction from MDString
Allow `GenericDebugNode` construction directly from `MDString`, rather
than requiring `StringRef`s. I've refactored the `StringRef`
constructors to use these. There's no real functionality change here,
except for exposing the lower-level API.
The purpose of this is to simplify construction of string operands when
reading bitcode. It's unnecessarily indirect to parse an `MDString` ID,
lookup the `MDString` in the bitcode reader list, get the `StringRef`
out of that, and then have `GenericDebugNode::getImpl()` use
`MDString::get()` to acquire the original `MDString`. Instead, this
allows the bitcode reader to directly pass in the `MDString`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227848
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Duncan P. N. Exon Smith [Mon, 2 Feb 2015 19:55:21 +0000 (19:55 +0000)]
IR: Extract DEFINE_MDNODE_GET(), NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227847
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Duncan P. N. Exon Smith [Mon, 2 Feb 2015 19:54:05 +0000 (19:54 +0000)]
IR: Separate helpers for string operands, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227846
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Lang Hames [Mon, 2 Feb 2015 19:51:18 +0000 (19:51 +0000)]
[Orc] Make OrcMCJITReplacement::addObject calls transfer buffer ownership to the
ObjectLinkingLayer.
There are a two of overloads for addObject, one of which transfers ownership of
the underlying buffer to OrcMCJITReplacement. This commit makes the ownership
transfering version pass ownership down to the ObjectLinkingLayer in order to
prevent the issue described in r227778.
I think this commit will fix the sanitizer bot failures that necessitated the
removal of the load-object-a.ll regression test in r227785, so I'm reinstating
that test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227845
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Rafael Espindola [Mon, 2 Feb 2015 19:22:51 +0000 (19:22 +0000)]
Move simple case earlier and use a continue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227841
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Eric Christopher [Mon, 2 Feb 2015 19:22:03 +0000 (19:22 +0000)]
Migrate HexagonISelDAGToDAG to setting a subtarget pointer during
runOnMachineFunction. Update all uses of the Subtarget accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227840
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Eric Christopher [Mon, 2 Feb 2015 19:22:01 +0000 (19:22 +0000)]
Use the getSubtarget call off of the MachineFunction rather than
the TargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227839
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Eric Christopher [Mon, 2 Feb 2015 19:05:28 +0000 (19:05 +0000)]
Remove unused class variables and update calls to get the subtarget
off of the machine function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227837
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Eric Christopher [Mon, 2 Feb 2015 18:58:24 +0000 (18:58 +0000)]
Sink queries into asserts since the variable is unused otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227836
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Duncan P. N. Exon Smith [Mon, 2 Feb 2015 18:53:21 +0000 (18:53 +0000)]
IR: Split out DebugInfoMetadata.h, NFC
Move debug-info-centred `Metadata` subclasses into their own
header/source file. A couple of private template functions are needed
from both `Metadata.cpp` and `DebugInfoMetadata.cpp`, so I've moved them
to `lib/IR/MetadataImpl.h`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227835
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Eric Christopher [Mon, 2 Feb 2015 18:52:49 +0000 (18:52 +0000)]
Update CMake build for removed files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227834
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Eric Christopher [Mon, 2 Feb 2015 18:46:31 +0000 (18:46 +0000)]
Get TargetRegisterInfo and TargetInstrInfo off of the MachineFunction
and remove unnecessary class variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227832
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Eric Christopher [Mon, 2 Feb 2015 18:46:29 +0000 (18:46 +0000)]
Use the function template getSubtarget to remove an explicit cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227831
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