Manman Ren [Mon, 30 Sep 2013 18:17:35 +0000 (18:17 +0000)]
TBAA: remove !tbaa from testing cases when they are not needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191689
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Jack Carter [Mon, 30 Sep 2013 18:05:18 +0000 (18:05 +0000)]
[mips][msa] Direct Object Emission for I8 instructions.
This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191688
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Jack Carter [Mon, 30 Sep 2013 17:58:07 +0000 (17:58 +0000)]
[mips][msa] Direct Object Emission for I5 instructions.
This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191687
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Tilmann Scheller [Mon, 30 Sep 2013 17:57:30 +0000 (17:57 +0000)]
[ARM] Clean up ARMAsmParser::validateInstruction().
Fix some LLVM Coding Standards violations.
No changes in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191686
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Jack Carter [Mon, 30 Sep 2013 17:52:33 +0000 (17:52 +0000)]
[mips][msa] Direct Object Emission for 2R instructions.
This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191685
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Jack Carter [Mon, 30 Sep 2013 17:43:04 +0000 (17:43 +0000)]
[PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR
and not an MSA register
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191684
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Tilmann Scheller [Mon, 30 Sep 2013 17:31:26 +0000 (17:31 +0000)]
[ARM] Use FileCheck instead of grep for ARM LDRD negative tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191683
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Rafael Espindola [Mon, 30 Sep 2013 16:39:19 +0000 (16:39 +0000)]
Move command line options to the users of libLTO. Fixes --enable-shared build.
Patch by Richard Sandiford.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191680
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Rafael Espindola [Mon, 30 Sep 2013 16:32:51 +0000 (16:32 +0000)]
Revert "Enable building LTO on WIN32."
This reverts commit r191670.
It was causing build failures on the msvc bots:
http://bb.pgr.jp/builders/ninja-clang-i686-msc17-R/builds/5166/steps/compile/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191679
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Tilmann Scheller [Mon, 30 Sep 2013 16:11:48 +0000 (16:11 +0000)]
[ARM] Assembler: ARM LDRD with writeback requires the base register to be different from the destination registers.
See ARM ARM A8.8.72.
Violating this constraint results in unpredictable behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191678
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Arnold Schwaighofer [Mon, 30 Sep 2013 15:56:34 +0000 (15:56 +0000)]
Swift model: Fix uop description on some writes
Those writes really need two/three uops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191677
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Benjamin Kramer [Mon, 30 Sep 2013 15:52:50 +0000 (15:52 +0000)]
BoundsChecking: Fix refacto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191676
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Benjamin Kramer [Mon, 30 Sep 2013 15:40:17 +0000 (15:40 +0000)]
Convert manual insert point restores to the new RAII object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191675
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Benjamin Kramer [Mon, 30 Sep 2013 15:39:59 +0000 (15:39 +0000)]
InstCombine: Replace manual fast math flag copying with the new IRBuilder RAII helper.
Defines away the issue where cast<Instruction> would fail because constant
folding happened. Also slightly cleaner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191674
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Benjamin Kramer [Mon, 30 Sep 2013 15:39:48 +0000 (15:39 +0000)]
IRBuilder: Add RAII objects to reset insertion points or fast math flags.
Inspired by the object from the SLPVectorizer. This found a minor bug in the
debug loc restoration in the vectorizer where the location of a following
instruction was attached instead of the location from the original instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191673
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Benjamin Kramer [Mon, 30 Sep 2013 15:39:27 +0000 (15:39 +0000)]
IRBuilder: Move fast math flags to IRBuilderBase.
They don't depend on the templated stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191672
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Arnold Schwaighofer [Mon, 30 Sep 2013 15:28:56 +0000 (15:28 +0000)]
IfConverter: Use TargetSchedule for instruction latencies
For targets that have instruction itineraries this means no change. Targets
that move over to the new schedule model will use be able the new schedule
module for instruction latencies in the if-converter (the logic is such that if
there is no itineary we will use the new sched model for the latencies).
Before, we queried "TTI->getInstructionLatency()" for the instruction latency
and the extra prediction cost. Now, we query the TargetSchedule abstraction for
the instruction latency and TargetInstrInfo for the extra predictation cost. The
TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if
an itinerary exists, otherwise it will use the new schedule model.
ATTENTION: Out of tree targets!
(I will also send out an email later to LLVMDev)
This means, if your target implements
unsigned getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI,
unsigned *PredCost);
and returns a value for "PredCost", you now also need to implement
unsigned getPredictationCost(const MachineInstr *MI);
(if your target uses the IfConversion.cpp pass)
radar://
15077010
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191671
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Rafael Espindola [Mon, 30 Sep 2013 15:28:14 +0000 (15:28 +0000)]
Enable building LTO on WIN32.
Enable building the LTO library (.lib and.dll) and llvm-lto.exe on Windows with
MSVC and Mingw as well as re-enabling the associated test.
Patch by Greg Bedwell!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191670
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Joey Gouly [Mon, 30 Sep 2013 14:18:35 +0000 (14:18 +0000)]
Fix a bug in InstCombine where it attempted to cast a Value* to an Instruction*
when it was actually a Constant*.
There are quite a few other casts to Instruction that might have the same problem,
but this is the only one I have a test case for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191668
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Tilmann Scheller [Mon, 30 Sep 2013 13:04:22 +0000 (13:04 +0000)]
[ARM] Assembler: Add more negative tests for ARM LDRD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191664
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Richard Sandiford [Mon, 30 Sep 2013 12:01:35 +0000 (12:01 +0000)]
[SystemZ] Revert r191661: Add definitions of LFH and STFH
For some reason, adding definitions for these load and store
instructions changed whether some of the build bots matched
comparisons as signed or unsigned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191663
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Richard Sandiford [Mon, 30 Sep 2013 10:50:33 +0000 (10:50 +0000)]
[SystemZ] Add definitions of LFH and STFH
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191661
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Richard Sandiford [Mon, 30 Sep 2013 10:45:16 +0000 (10:45 +0000)]
[SystemZ] Add GRH32 for the high word of a GR64
The only thing this does on its own is make the definitions of RISB[HL]G
a bit more precise. Those instructions are only used by the MC layer at
the moment, so no behavioral change is intended. The class is needed by
later patches though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191660
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Richard Sandiford [Mon, 30 Sep 2013 10:28:35 +0000 (10:28 +0000)]
[SystemZ] Rename subregs and add subreg_h32
Use subreg_hNN and subreg_lNN for the high and low NN bits of a register.
List the low registers first, so that subreg_l32 also means the low 32
bits of a 128-bit register.
Floats are stored in the upper 32 bits of a 64-bit register, so they
should use subreg_h32 rather than subreg_l32.
No behavioral change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191659
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Daniel Sanders [Mon, 30 Sep 2013 09:35:37 +0000 (09:35 +0000)]
[mips] Fix a broken link to mips.com in the documentation.
It now points to the equivalent page on imgtec.com
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191658
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Richard Sandiford [Mon, 30 Sep 2013 08:54:17 +0000 (08:54 +0000)]
[SystemZ] Add change missing from previous commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191656
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Richard Sandiford [Mon, 30 Sep 2013 08:48:38 +0000 (08:48 +0000)]
[SystemZ] Rename 32-bit GPR registers
I'm about to add support for high-word operations, so it seemed better
for the low-word registers to have names like R0L rather than R0W.
No behavioral change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191655
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Craig Topper [Mon, 30 Sep 2013 06:23:19 +0000 (06:23 +0000)]
Filter out repeated sections from the X86 disassembler modRMTable. Saves about ~43K from a released build. Unfortunately the disassembler tables are still upwards of 800K.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191652
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Craig Topper [Mon, 30 Sep 2013 02:50:51 +0000 (02:50 +0000)]
Add a few more FMA4 disassembler test cases to match the scalar set with regards to combinations of L and W-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191650
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Craig Topper [Mon, 30 Sep 2013 02:46:36 +0000 (02:46 +0000)]
Various x86 disassembler fixes.
Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191649
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Benjamin Kramer [Sun, 29 Sep 2013 19:39:13 +0000 (19:39 +0000)]
ObjectSizeOffsetEvaluator: Don't run into infinite recursion if we have a cyclic GEP.
Those can occur in dead code. PR17402.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191644
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Benjamin Kramer [Sun, 29 Sep 2013 19:39:02 +0000 (19:39 +0000)]
Remove an old workaround for a compiler that EOL'd years ago.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191643
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Benjamin Kramer [Sun, 29 Sep 2013 11:29:20 +0000 (11:29 +0000)]
Plug a memory leak in a unit test. Stack allocation is sufficient here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191638
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Benjamin Kramer [Sun, 29 Sep 2013 11:24:02 +0000 (11:24 +0000)]
Deallocate type units when destroying a DWARFContext.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191637
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Benjamin Kramer [Sun, 29 Sep 2013 11:18:56 +0000 (11:18 +0000)]
Allocate AtomicSDNode operands in SelectionDAG's allocator to stop leakage.
SDNode destructors are never called. As an optimization use AtomicSDNode's
internal storage if we have a small number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191636
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Craig Topper [Sun, 29 Sep 2013 08:35:51 +0000 (08:35 +0000)]
Revert accidental commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191633
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Craig Topper [Sun, 29 Sep 2013 08:33:34 +0000 (08:33 +0000)]
Change type of XOP flag in code emitters to a bool. Remove a some unneeded cases from switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191632
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Craig Topper [Sun, 29 Sep 2013 06:31:18 +0000 (06:31 +0000)]
Add comments for XOPA map introduced with TBM instructions.a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191630
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Benjamin Kramer [Sat, 28 Sep 2013 21:27:49 +0000 (21:27 +0000)]
Add a test that large offsets on GEPs on 32 bits targets are handled correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191628
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Chandler Carruth [Sat, 28 Sep 2013 18:17:10 +0000 (18:17 +0000)]
Enable libcxx as part of the top level CMake build when it is checked
out in projects. This appears to be working on my system, and I will be
watching build bots to see if there are any issues on other platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191624
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Robert Wilhelm [Sat, 28 Sep 2013 13:42:22 +0000 (13:42 +0000)]
Even more spelling fixes for "instruction".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191611
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Robert Wilhelm [Sat, 28 Sep 2013 11:46:15 +0000 (11:46 +0000)]
Fix spelling intruction -> instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191610
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Tom Stellard [Sat, 28 Sep 2013 03:10:17 +0000 (03:10 +0000)]
SelectionDAG: Silence unused variable warning on release builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191604
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Tom Stellard [Sat, 28 Sep 2013 02:50:50 +0000 (02:50 +0000)]
R600: Fix handling of NAN in comparison instructions
We were completely ignoring the unorder/ordered attributes of condition
codes and also incorrectly lowering seto and setuo.
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191603
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Tom Stellard [Sat, 28 Sep 2013 02:50:43 +0000 (02:50 +0000)]
SelectionDAG: Improve legalization of SELECT_CC with illegal condition codes
SelectionDAG will now attempt to inverse an illegal conditon in order to
find a legal one and if that doesn't work, it will attempt to swap the
operands using the inverted condition.
There are no new test cases for this, but a nubmer of the existing R600
tests hit this path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191602
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Tom Stellard [Sat, 28 Sep 2013 02:50:38 +0000 (02:50 +0000)]
SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()
This is useful for targets like R600, which only support GT, GE, NE, and EQ
condition codes as it removes the need to handle unsupported condition
codes in target specific code.
There are no tests with this commit, but R600 has been updated to take
advantage of this new feature, so its existing selectcc tests are now
testing the swapped operands path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191601
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Tom Stellard [Sat, 28 Sep 2013 02:50:32 +0000 (02:50 +0000)]
SelectionDAG: Clean up LegalizeSetCCCondCode() function
Interpreting the results of this function is not very intuitive, so I
cleaned it up to make it more clear whether or not a SETCC op was
legalized and how it was legalized (either by swapping LHS and RHS or
replacing with AND/OR).
This patch does change functionality in the LHS and RHS swapping case,
but unfortunately there are no in-tree tests for this. However, this
patch is a prerequisite for R600 to take advantage of the LHS and RHS
swapping, so tests will be added in subsequent commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191600
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NAKAMURA Takumi [Sat, 28 Sep 2013 01:35:07 +0000 (01:35 +0000)]
MipsMachineFunction.cpp: Add missing #include <raw_ostream.h>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191597
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Matt Arsenault [Sat, 28 Sep 2013 01:08:00 +0000 (01:08 +0000)]
Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191595
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Manman Ren [Sat, 28 Sep 2013 00:22:27 +0000 (00:22 +0000)]
AutoUpgrade: upgrade from scalar TBAA format to struct-path aware TBAA format.
We treat TBAA tags as struct-path aware TBAA format when the first operand
is a MDNode and the tag has 3 or more operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191593
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Akira Hatanaka [Sat, 28 Sep 2013 00:12:32 +0000 (00:12 +0000)]
[mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out
of loops.
Previously, two consecutive calls to function "func" would result in the
following sequence of instructions:
1. load $16, %got(func)($gp) // load address of lazy-binding stub.
2. move $25, $16
3. jalr $25 // jump to lazy-binding stub.
4. nop
5. move $25, $16
6. jalr $25 // jump to lazy-binding stub again.
With this patch, the second call directly jumps to func's address, bypassing
the lazy-binding resolution routine:
1. load $25, %got(func)($gp) // load address of lazy-binding stub.
2. jalr $25 // jump to lazy-binding stub.
3. nop
4. load $25, %got(func)($gp) // load resolved address of func.
5. jalr $25 // directly jump to func.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191591
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Manman Ren [Fri, 27 Sep 2013 22:59:21 +0000 (22:59 +0000)]
TBAA: try to fix the dragonegg bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191585
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Eric Christopher [Fri, 27 Sep 2013 22:50:48 +0000 (22:50 +0000)]
Unify conditionals and reformat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191582
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Matt Arsenault [Fri, 27 Sep 2013 22:38:23 +0000 (22:38 +0000)]
Minor code simplification
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191579
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Akira Hatanaka [Fri, 27 Sep 2013 22:30:36 +0000 (22:30 +0000)]
[mips] Define a derived class of PseudoSourceValue that represents a GOT entry
resolved by lazy-binding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191578
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Matt Arsenault [Fri, 27 Sep 2013 22:26:25 +0000 (22:26 +0000)]
Use right pointer type in DebugIR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191576
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Matt Arsenault [Fri, 27 Sep 2013 22:18:51 +0000 (22:18 +0000)]
Use type helper functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191574
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Eric Christopher [Fri, 27 Sep 2013 22:10:10 +0000 (22:10 +0000)]
Rework conditional for printing out pub sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191571
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Josh Magee [Fri, 27 Sep 2013 21:58:43 +0000 (21:58 +0000)]
[stackprotector] Refactor the StackProtector pass from a single .cpp file into StackProtector.h and StackProtector.cpp.
No functionality change. Future patches will add analysis which will be used
in other passes (PEI, StackSlot). The end goal is to support ssp-strong stack
layout rules.
WIP.
Differential Revision: http://llvm-reviews.chandlerc.com/D1521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191570
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Rui Ueyama [Fri, 27 Sep 2013 21:47:05 +0000 (21:47 +0000)]
Object/COFF: Rename getXXX{Begin,End} -> xxx_{begin,end}.
It is mentioned in the LLVM coding standard that _begin() and _end() suffixes
should be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191569
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Rui Ueyama [Fri, 27 Sep 2013 21:26:38 +0000 (21:26 +0000)]
Resurrect lit.local.cfg to un-break hexagon buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191565
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Matt Arsenault [Fri, 27 Sep 2013 21:24:57 +0000 (21:24 +0000)]
Fix SLPVectorizer using wrong address space for load/store
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191564
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Dmitri Gribenko [Fri, 27 Sep 2013 21:24:36 +0000 (21:24 +0000)]
SourceMgr diagnotics printing: fix a bug where printing a fixit for a source
range that includes a tab character will cause out-of-bounds access to the
fixit string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191563
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Renato Golin [Fri, 27 Sep 2013 21:14:54 +0000 (21:14 +0000)]
Clarifying doc about cross-compiling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191561
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Dmitri Gribenko [Fri, 27 Sep 2013 21:09:25 +0000 (21:09 +0000)]
Make SourceMgr::PrintMessage() testable and add unit tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191558
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Rui Ueyama [Fri, 27 Sep 2013 21:04:00 +0000 (21:04 +0000)]
Re-submit r191472 with a fix for big endian.
llvm-objdump: Dump COFF import table if -private-headers option is given.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191557
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Bill Wendling [Fri, 27 Sep 2013 20:40:40 +0000 (20:40 +0000)]
Update.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191553
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Justin Bogner [Fri, 27 Sep 2013 20:35:39 +0000 (20:35 +0000)]
InstCombine: Only foldSelectICmpAndOr for integer types
Currently foldSelectICmpAndOr asserts if the "or" involves a vector
containing several of the same power of two. We can easily avoid this by
only performing the fold on integer types, like foldSelectICmpAnd does.
Fixes <rdar://problem/
15012516>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191552
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Akira Hatanaka [Fri, 27 Sep 2013 19:51:35 +0000 (19:51 +0000)]
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191546
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Yunzhong Gao [Fri, 27 Sep 2013 18:38:42 +0000 (18:38 +0000)]
Adding intrinsics to the llvm backend for TBM instruction set.
Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539
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Manman Ren [Fri, 27 Sep 2013 18:34:27 +0000 (18:34 +0000)]
TBAA: handle scalar TBAA format and struct-path aware TBAA format.
Remove the command line argument "struct-path-tbaa" since we should not depend
on command line argument to decide which format the IR file is using. Instead,
we check the first operand of the tbaa tag node, if it is a MDNode, we treat
it as struct-path aware TBAA format, otherwise, we treat it as scalar TBAA
format.
When clang starts to use struct-path aware TBAA format no matter whether
struct-path-tbaa is no, and we can auto-upgrade existing bc files, the support
for scalar TBAA format can be dropped.
Existing testing cases are updated to use the struct-path aware TBAA format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191538
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Justin Bogner [Fri, 27 Sep 2013 15:30:25 +0000 (15:30 +0000)]
Transforms: Use getFirstNonPHI to set the insertion point for PHIs
We were previously using getFirstInsertionPt to insert PHI
instructions when vectorizing, but getFirstInsertionPt also skips past
landingpads, causing this to generate invalid IR.
We can avoid this issue by using getFirstNonPHI instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191526
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Richard Sandiford [Fri, 27 Sep 2013 15:29:20 +0000 (15:29 +0000)]
[SystemZ] Rein back the use of block operations
The backend tries to use block operations like MVC, NC, OC and XC for
simple scalar operations. For correctness reasons, it rejects any case
in which the regions might partially overlap. However, for performance
reasons, it should also reject cases where the regions might be equal,
since the instruction might then not use the fast path.
This fixes a performance regression seen in bzip2. We may want to limit
the optimisation even more in future, or even remove it entirely, but I'll
try with this for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191525
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Richard Sandiford [Fri, 27 Sep 2013 15:14:04 +0000 (15:14 +0000)]
[SystemZ] Improve handling of PC-relative addresses
The backend previously folded offsets into PC-relative addresses
whereever possible. That's the right thing to do when the address
can be used directly in a PC-relative memory reference (using things
like LRL). But if we have a register-based memory reference and need
to load the PC-relative address separately, it's better to use an anchor
point that could be shared with other accesses to the same area of the
variable.
Fixes a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191524
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Daniel Sanders [Fri, 27 Sep 2013 13:36:54 +0000 (13:36 +0000)]
[mips][msa] Implemented insert.d intrinsic.
This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is
further lowered into a sequence of insert.w's on MIPS32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191521
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Tilmann Scheller [Fri, 27 Sep 2013 13:28:17 +0000 (13:28 +0000)]
ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands.
As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints:
LDRD<c> <Rt>, <Rt2>, ...
(a) Rt must be even-numbered and not r14
(b) Rt2 must be R(t+1)
If those two constraints are not met the result of executing the instruction will be unpredictable.
Constraint (b) was already enforced, this commit adds support for constraint (a).
Fixes rdar://
14479793.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191520
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Daniel Sanders [Fri, 27 Sep 2013 13:20:41 +0000 (13:20 +0000)]
[mips][msa] Implemented fill.d intrinsic.
This intrinsic is lowered into an equivalent BUILD_VECTOR which is further
lowered into a sequence of insert.w's on MIPS32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191519
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Daniel Sanders [Fri, 27 Sep 2013 13:04:21 +0000 (13:04 +0000)]
[mips][msa] Implemented copy_[us].d intrinsic.
This intrinsic is lowered into equivalent copy_s.w instructions during
legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191518
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Daniel Sanders [Fri, 27 Sep 2013 12:45:08 +0000 (12:45 +0000)]
[mips][msa] Rename arguments to MSA_INSERT_DESC_BASE to better match their expected values.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191517
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Daniel Sanders [Fri, 27 Sep 2013 12:31:32 +0000 (12:31 +0000)]
[mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.
For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is
later expanded to appropriate insve.[wd] insns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191515
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Daniel Sanders [Fri, 27 Sep 2013 12:17:32 +0000 (12:17 +0000)]
[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64
For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may
be expanded to subregister copies and/or instructions as appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514
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Andrea Di Biagio [Fri, 27 Sep 2013 12:13:58 +0000 (12:13 +0000)]
Remove superfluous comment accidentally checked-in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191513
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Daniel Sanders [Fri, 27 Sep 2013 12:03:51 +0000 (12:03 +0000)]
[mips][msa] Added support for MSA registers to copyPhysReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191512
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Daniel Sanders [Fri, 27 Sep 2013 11:48:57 +0000 (11:48 +0000)]
[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics)
Updated some of the vshf since they (correctly) emit splati's now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191511
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Andrea Di Biagio [Fri, 27 Sep 2013 11:37:05 +0000 (11:37 +0000)]
Re-apply the change from r191393 with fix for pr17380.
This change fixes the problem reported in pr17380 and re-add the dagcombine
transformation ensuring that the value types are always legal if the
transformation is triggered after Legalization took place.
Added the test case from pr17380.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191509
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Daniel Sanders [Fri, 27 Sep 2013 10:42:22 +0000 (10:42 +0000)]
[mips][msa] Added MSA.txt to describe instruction selection quirks.
This file contains notes about the instruction selection for MSA. For example,
it notes that ilvl.d is cannot be selected because ilvev.d covers the same
cases and is selected instead of ilvl.d.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191507
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Tilmann Scheller [Fri, 27 Sep 2013 10:38:11 +0000 (10:38 +0000)]
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191505
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Tilmann Scheller [Fri, 27 Sep 2013 10:30:18 +0000 (10:30 +0000)]
ARM: Teach assembler to enforce constraint for Thumb2 LDRD (literal/immediate) destination register operands.
LDRD<c> <Rt>, <Rt2>, <label>
LDRD<c> <Rt>, <Rt2>, [<Rn>{, #+/-<imm>}]
LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm>
LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]!
As specified in A8.8.72/A8.8.73 in the ARM ARM, the T1 encoding has a constraint which enforces that Rt != Rt2.
If this constraint is not met the result of executing the instruction will be unpredictable.
Fixes rdar://
14479780.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191504
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Daniel Sanders [Fri, 27 Sep 2013 10:25:41 +0000 (10:25 +0000)]
[mips][msa] Tidy up
lowerMSABinaryIntr, lowerMSABinaryImmIntr, lowerMSABranchIntr,
and lowerMSAUnaryIntr were trivially small functions. Inlined them into
their callers.
lowerMSASplat now takes its callers SDLoc instead of making a new one.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191503
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Daniel Sanders [Fri, 27 Sep 2013 10:08:31 +0000 (10:08 +0000)]
[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498
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Daniel Sanders [Fri, 27 Sep 2013 09:44:59 +0000 (09:44 +0000)]
[mips][msa] Expand all truncstores and loadexts for MSA as well as DSP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191496
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Daniel Sanders [Fri, 27 Sep 2013 09:25:29 +0000 (09:25 +0000)]
[mips][msa] Added missing check in performSRACombine
Reviewers: jacksprat, dsanders
Reviewed By: dsanders
Differential Revision: http://llvm-reviews.chandlerc.com/D1755
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191495
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Puyan Lotfi [Fri, 27 Sep 2013 07:36:10 +0000 (07:36 +0000)]
First check in. Modified a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191491
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Craig Topper [Fri, 27 Sep 2013 07:20:47 +0000 (07:20 +0000)]
Put HasAVX512 predicate on some patterns to properly disable them when AVX512 isn't enabled. Currently it works simply because the SSE and AVX version of the same patterns are checked first in the DAG isel table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191490
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Craig Topper [Fri, 27 Sep 2013 07:16:24 +0000 (07:16 +0000)]
Switch HasAVX to UseAVX in one spot to ensure that AVX512 form of VINSERTPS is used in AVX512 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191489
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Craig Topper [Fri, 27 Sep 2013 07:11:17 +0000 (07:11 +0000)]
Removal some duplicate patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191488
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Yunzhong Gao [Fri, 27 Sep 2013 01:44:23 +0000 (01:44 +0000)]
Fixing Intel format of the vshufpd instruction.
Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191481
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Rui Ueyama [Fri, 27 Sep 2013 01:29:36 +0000 (01:29 +0000)]
Revert "llvm-objdump: Dump COFF import table if -private-headers option is given."
This reverts commit r191472 because it's failing on BE machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191480
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Rui Ueyama [Fri, 27 Sep 2013 00:53:07 +0000 (00:53 +0000)]
Fix another -Wnon-pod-varargs error in r191472.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191474
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Rui Ueyama [Fri, 27 Sep 2013 00:20:53 +0000 (00:20 +0000)]
Fix -Wnon-pod-varargs error in r191472.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191473
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