It is not possible to determie dominance between two PHI nodes
based on their ordering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35369 91177308-0d34-0410-b5e6-96231b3b80d8

Use std::vector<DFCalculateWorkObject> instead of
std::vector<DFCalculateWorkObject *> to reduce malloc/free traffic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35368 91177308-0d34-0410-b5e6-96231b3b80d8

Test case for PR1266.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35367 91177308-0d34-0410-b5e6-96231b3b80d8

findRegisterUseOperand() changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35366 91177308-0d34-0410-b5e6-96231b3b80d8

Fix for PR1266. Don't mark a two address operand IsKill.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35365 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1277:
Implement error handling for bytecode parsing.

Patch by Scott Michel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35364 91177308-0d34-0410-b5e6-96231b3b80d8

Change findRegisterUseOperand() to return operand index instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35363 91177308-0d34-0410-b5e6-96231b3b80d8

Fix reversed logic in getRegsUsed.  Rename RegStates to RegsAvailable to
hopefully forestall similar errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35362 91177308-0d34-0410-b5e6-96231b3b80d8

eliminate use of std::set

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35361 91177308-0d34-0410-b5e6-96231b3b80d8

Add a comment to explain a folding transform.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35360 91177308-0d34-0410-b5e6-96231b3b80d8

Fix this test case to match output after a bug was fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35359 91177308-0d34-0410-b5e6-96231b3b80d8

Get better debug output by having modified instructions print both the
original and new instruction. A slight performance hit with ostringstream
but it is only for debug.
Also, clean up an uninitialized variable warning noticed in a release build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35358 91177308-0d34-0410-b5e6-96231b3b80d8

Get the number of bits to set in a mask correct for a shl/lshr transform.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35357 91177308-0d34-0410-b5e6-96231b3b80d8

Fix testsuite hang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35355 91177308-0d34-0410-b5e6-96231b3b80d8

For PR601:
Initial skeleton for pass documentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35354 91177308-0d34-0410-b5e6-96231b3b80d8

Promote to v1i64 type...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35353 91177308-0d34-0410-b5e6-96231b3b80d8

Updated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35352 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for the v1i64 type. This makes better code for this:

#include <mmintrin.h>

extern __m64 C;

void baz(__v2si *A, __v2si *B)
{
  *A = C;
  _mm_empty();
}

We get this:

_baz:
        call "L1$pb"
"L1$pb":
        popl %eax
        movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
        movq (%eax), %mm0
        movl 4(%esp), %eax
        movq %mm0, (%eax)
        emms
        ret

GCC gives us this:

_baz:
        pushl   %ebx
        call    L3
"L00000000001$pb":
L3:
        popl    %ebx
        subl    $8, %esp
        movl    L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
        movl    (%eax), %edx
        movl    4(%eax), %ecx
        movl    16(%esp), %eax
        movl    %edx, (%eax)
        movl    %ecx, 4(%eax)
        emms
        addl    $8, %esp
        popl    %ebx
        ret

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35351 91177308-0d34-0410-b5e6-96231b3b80d8

SIGN_EXTEND_INREG requires one extra operand, a ValueType node.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35350 91177308-0d34-0410-b5e6-96231b3b80d8

Test case for PR1271 involving construction of a bad mask to replace a
shift instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35349 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1271:
Fix SingleSource/Regression/C/2003-05-21-UnionBitFields.c by changing a
getHighBitsSet call to getLowBitsSet call that was incorrectly converted
from the original lshr constant expression.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35348 91177308-0d34-0410-b5e6-96231b3b80d8

Look through bitcast when finding IVs.  (Chris' patch really.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35347 91177308-0d34-0410-b5e6-96231b3b80d8

Start value symbol tables out small (space for 16 elts), not huge (space for 512).

This is particularly useful for the JIT, which lazily deserializes functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35346 91177308-0d34-0410-b5e6-96231b3b80d8

Add "feature" testcase for new switch lowering code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35345 91177308-0d34-0410-b5e6-96231b3b80d8

Compute getLowBitsSet correctly. Using the complement of a 64-bit value
and shifting down without regard for the bitwidth of the APInt can lead
to incorrect initialization values. Instead, check for the word size case
(to avoid undef results from shift) and then do (1 << loBitsSet) - 1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35344 91177308-0d34-0410-b5e6-96231b3b80d8

Add a test case for PR1271 (necessary, but not sufficient).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35343 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1271:
Remove a use of getLowBitsSet that caused the mask used for replacement of
shl/lshr pairs with an AND instruction to be computed incorrectly. Its not
clear exactly why this is the case. This solves the disappearing shifts
problem, but it doesn't fix Regression/C/2003-05-21-UnionBitFields. It
seems there is more going on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35342 91177308-0d34-0410-b5e6-96231b3b80d8

implement Transforms/InstCombine/cast2.ll:test3 and PR1263

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35341 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35340 91177308-0d34-0410-b5e6-96231b3b80d8

Some cleanup from review:
* Don't assume shift amounts are <= 64 bits
* Avoid creating an extra APInt in SubOne and AddOne by using -- and ++
* Add another use of getLowBitsSet
* Convert a series of if statements to a switch

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35339 91177308-0d34-0410-b5e6-96231b3b80d8

First step of switch lowering refactoring: perform worklist-driven
strategy, emit JT's where possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35338 91177308-0d34-0410-b5e6-96231b3b80d8

Fix authorship

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35337 91177308-0d34-0410-b5e6-96231b3b80d8

fold constantexprs more aggressively, fixing PR1265

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35336 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor several ConstantExpr::getXXX calls with ConstantInt arguments
using the facilities of APInt. While this duplicates a tiny fraction of
the constant folding code, it also makes the code easier to read and
avoids large ConstantExpr overhead for simple, known computations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35335 91177308-0d34-0410-b5e6-96231b3b80d8

add a note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35334 91177308-0d34-0410-b5e6-96231b3b80d8

1. Avoid unnecessary APInt construction if possible.
2. Use isStrictlyPositive() instead of isPositive() in two places where
   they need APInt value > 0 not only >=0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35333 91177308-0d34-0410-b5e6-96231b3b80d8

Implement support for vector operands to inline asm, implementing
CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35332 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35331 91177308-0d34-0410-b5e6-96231b3b80d8

add a note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35330 91177308-0d34-0410-b5e6-96231b3b80d8

Fix CodeGen/PowerPC/2007-03-24-cntlzd.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35329 91177308-0d34-0410-b5e6-96231b3b80d8

test that the ppc backend can do 64-bit cntlz

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35328 91177308-0d34-0410-b5e6-96231b3b80d8

implement initial support for the silly X constraint.  Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35327 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35326 91177308-0d34-0410-b5e6-96231b3b80d8

Make more uses of getHighBitsSet and get rid of some pointless & of an
APInt with its type mask.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35325 91177308-0d34-0410-b5e6-96231b3b80d8

Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35324 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35323 91177308-0d34-0410-b5e6-96231b3b80d8

switch TargetLowering::getConstraintType to take the entire constraint,
not just the first letter.  No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35322 91177308-0d34-0410-b5e6-96231b3b80d8

More APIntification:
* Convert the last use of a uint64_t that should have been an APInt.
* Change ComputeMaskedBits to have a const reference argument for the Mask
  so that recursions don't cause unneeded temporaries. This causes temps
  to be needed in other places (where the mask has to change) but this
  change optimizes for the recursion which is more frequent.
* Remove two instances of &ing a Mask with getAllOnesValue. Its not
  needed any more because APInt is accurate in its bit computations.
* Start using the getLowBitsSet and getHighBits set methods on APInt
  instead of shifting. This makes it more clear in the code what is
  going on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35321 91177308-0d34-0410-b5e6-96231b3b80d8

Allow the b/h/w/k constraints to be applied to values that have multiple alternatives, and end up not being registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35320 91177308-0d34-0410-b5e6-96231b3b80d8

enforce the proper range for the i386 N constraint.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35319 91177308-0d34-0410-b5e6-96231b3b80d8

Fix test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35318 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35317 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a typo in a comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35316 91177308-0d34-0410-b5e6-96231b3b80d8

Actually, for getHighBitsSet and getLowBitsSet, don't make a 0 bit size
illegal. Instead do the 0 valued construction for the user. This is because
the caller may not know (or care to check) that the number of bits set is
zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35315 91177308-0d34-0410-b5e6-96231b3b80d8

fix a regression on vector or instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35314 91177308-0d34-0410-b5e6-96231b3b80d8

Make it illegal to set 0 bits in getHighBitsSet and getLowBitsSet. For that
they should have used the uint64_t constructor. This avoids causing
undefined results via shifts by the word size when the bit width is an
exact multiple of the word size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35313 91177308-0d34-0410-b5e6-96231b3b80d8

In the getBitsSet function, don't optimize for a common case that is
already covered by getLowBitsSet (i.e. when loBits==0). Consequently, remove
the default value for loBits and reorder the arguments to the more natural
loBits, hiBits order. This makes it more clear that this function is for bit
groups in the middle of the bit width and not towards one end or the other.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35312 91177308-0d34-0410-b5e6-96231b3b80d8

Don't invoke undefined behavior in shifts in the functions getHighBitsSet
and getLowBitsSet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35311 91177308-0d34-0410-b5e6-96231b3b80d8

Implement the getBitsSet function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35310 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the last vestiges of this directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35309 91177308-0d34-0410-b5e6-96231b3b80d8

Implement the getHighBitsSet and getLowBitsSet functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35308 91177308-0d34-0410-b5e6-96231b3b80d8

Get the signs in the right place!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35307 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a link.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35306 91177308-0d34-0410-b5e6-96231b3b80d8

Undo the last change and make this really implement remainder and not
modulus. The previous change was a result of incorrect documentation in
the LangRef.html.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35305 91177308-0d34-0410-b5e6-96231b3b80d8

Flip the srem tests around. Previous commit was to correct an apparent
bug in the srem implementation. Turns out it was a documentation bug
instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35304 91177308-0d34-0410-b5e6-96231b3b80d8

Correct the description of srem. remainder follows the dividend not the
divisor!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35303 91177308-0d34-0410-b5e6-96231b3b80d8

Correct the implementation of srem to be remainder, not modulus. The sign of
the result must follow the sign of the divisor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35302 91177308-0d34-0410-b5e6-96231b3b80d8

Fix incorrect test cases for srem. The definition of srem is a remainder so
that the sign of the result follows the sign of the divisor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35301 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up this interface:
1. Group similar methods into doxygen groups
2. Reorganize the groups into a consist flow.
3. Significantly improve the quality of the documentation on several methods
4. Rewrite srem and sdiv to eliminate a copy and improve readability.
5. Eliminate unneeded forward references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35300 91177308-0d34-0410-b5e6-96231b3b80d8

don't rely on ADL

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35299 91177308-0d34-0410-b5e6-96231b3b80d8

add a valuetype for v1i64, which is needed by mmx.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35298 91177308-0d34-0410-b5e6-96231b3b80d8

Make some codes more efficient.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35297 91177308-0d34-0410-b5e6-96231b3b80d8

add a bad case evan though of.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35296 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1205:
Convert some calls to ConstantInt::getZExtValue() into getValue() and
use APInt facilities in the subsequent computations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35294 91177308-0d34-0410-b5e6-96231b3b80d8

Adjust offset to compensate for big endian machines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35293 91177308-0d34-0410-b5e6-96231b3b80d8

Autodetect MMX & SSE stuff for AMD processors

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35292 91177308-0d34-0410-b5e6-96231b3b80d8

This is dead. DEAD I tells you!!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35291 91177308-0d34-0410-b5e6-96231b3b80d8

PR1260:
Add final support to get the QT example to compile.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35290 91177308-0d34-0410-b5e6-96231b3b80d8

Make sure SEXTLOAD of the specific type is supported on the target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35289 91177308-0d34-0410-b5e6-96231b3b80d8

Add more test cases for APIntified InstCombine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35288 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1205:
* APIntify visitAdd and visitSelectInst
* Remove unused uint64_t versions of utility functions that have been
  replaced with APInt versions.
This completes most of the changes for APIntification of InstCombine. This
passes llvm-test and llvm/test/Transforms/InstCombine/APInt.

Patch by Zhou Sheng.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35287 91177308-0d34-0410-b5e6-96231b3b80d8

Also replace uses of SRL if that's also folded during ReduceLoadWidth().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35286 91177308-0d34-0410-b5e6-96231b3b80d8

Add test case for testing InstCombine with arbitrary precision integer
types. These tests mimic the integer test cases in the normal InstCombine
test suite but use "strange" integer bit widths.

Most tests written by Zhou Sheng, a few by me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35284 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1205:
APIntify visitDiv, visitMul and visitRem.

Patch by Zhou Sheng.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35283 91177308-0d34-0410-b5e6-96231b3b80d8

switch AddReachableCodeToWorklist from being recursive to being iterative.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35282 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1205:
APIntify several utility functions supporting logical operators and shift
operators.

Patch by Zhou Sheng.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35281 91177308-0d34-0410-b5e6-96231b3b80d8

Add the 'explicit' keyword to several constructors that accept one
argument that don't appear intended as implicit-conversion operators.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35280 91177308-0d34-0410-b5e6-96231b3b80d8

Test handling of switches with wide case ranges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35279 91177308-0d34-0410-b5e6-96231b3b80d8

Fix constant fold of div by zero and rem by zero to match IEEE 754
requirements. We must return NaN in some cases and correctly signed
infinity in other cases. Passes CFP2006 (not that that says much).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35277 91177308-0d34-0410-b5e6-96231b3b80d8

Make the "KnownZero ^ TypeMask" computation just once.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35276 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify the code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35275 91177308-0d34-0410-b5e6-96231b3b80d8

A couple of bug fixes for reducing load width xform:
1. Address offset is in bytes.
2. Make sure truncate node uses are replaced with new load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35274 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1205:
APInt support for logical operators in visitAnd, visitOr, and visitXor.

Patch by Zhou Sheng.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35273 91177308-0d34-0410-b5e6-96231b3b80d8

The -funcresolve and -raise options no longer exist.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35272 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1205:
* APIntify commonIntCastTransforms
* APIntify visitTrunc
* APIntify visitZExt

Patch by Zhou Sheng.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35271 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1205:
* Re-enable the APInt version of MaskedValueIsZero.
* APIntify the Comput{Un}SignedMinMaxValuesFromKnownBits functions
* APIntify visitICmpInst.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35270 91177308-0d34-0410-b5e6-96231b3b80d8

We generate a shufflevector instruction, so we don't need the builtin
intrinsic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35269 91177308-0d34-0410-b5e6-96231b3b80d8

Cleanup obsolete stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35268 91177308-0d34-0410-b5e6-96231b3b80d8

Be more explicit concerning argument sizes.
Use VC++ byteswap intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35267 91177308-0d34-0410-b5e6-96231b3b80d8

Support added for shifts and unpacking MMX instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35266 91177308-0d34-0410-b5e6-96231b3b80d8