Eliminate IntrinsicLowering from TargetMachine.
Make the CBE and V9 backends create their own, since they're the only ones that use it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26974 91177308-0d34-0410-b5e6-96231b3b80d8

Eliminate IntrinsicLowering from TargetMachine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26973 91177308-0d34-0410-b5e6-96231b3b80d8

simplify some code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26972 91177308-0d34-0410-b5e6-96231b3b80d8

remove always-null IntrinsicLowering argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26971 91177308-0d34-0410-b5e6-96231b3b80d8

remove the intrinsiclowering hook

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26970 91177308-0d34-0410-b5e6-96231b3b80d8

Add v4i32 <-> v4f32 bitconvert patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26969 91177308-0d34-0410-b5e6-96231b3b80d8

Allow result node to be a simple leaf node. This enable bitconvert patterns
like this:
def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26968 91177308-0d34-0410-b5e6-96231b3b80d8

Add 128-bit integer vector load and add (for testing).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26967 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for 8 bit immediates with 16/32 bit cmp instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26966 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26965 91177308-0d34-0410-b5e6-96231b3b80d8

Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do
64-bit vector shuffle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26964 91177308-0d34-0410-b5e6-96231b3b80d8

Replace vector splat test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26963 91177308-0d34-0410-b5e6-96231b3b80d8

Add a v2f64 splat (using movlhps) test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26962 91177308-0d34-0410-b5e6-96231b3b80d8

Implement simple support for vector casting.  This can currently only handle
casts between legal vector types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26961 91177308-0d34-0410-b5e6-96231b3b80d8

Fix comments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26960 91177308-0d34-0410-b5e6-96231b3b80d8

SHUFP* are two address code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26959 91177308-0d34-0410-b5e6-96231b3b80d8

add a new node

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26958 91177308-0d34-0410-b5e6-96231b3b80d8

Some clean up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26957 91177308-0d34-0410-b5e6-96231b3b80d8

- Supposely movlhps is faster / better than unpcklpd.
- Don't forget pshufd is only available with sse2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26956 91177308-0d34-0410-b5e6-96231b3b80d8

test that vspltw is generated for test cases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26955 91177308-0d34-0410-b5e6-96231b3b80d8

- Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support
  splat and PSHUFD cases.
- Clean up shuffle / splat matching code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26954 91177308-0d34-0410-b5e6-96231b3b80d8

silence a bogus gcc warning

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26953 91177308-0d34-0410-b5e6-96231b3b80d8

These changes are necessary to support the new llvm-config tool. llvm-config
is a handy tool for users of LLVM who want to be able to quickly get
information about LLVM's configuration. It is intended to be used in the
command line of other tools. Documentation will be forthcoming in a
subsequent patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26952 91177308-0d34-0410-b5e6-96231b3b80d8

- VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches
  PSHUFD. We can make permutes entries which point to the undef pointing
  anything we want.
- Change some names to appease Chris.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26951 91177308-0d34-0410-b5e6-96231b3b80d8

add a note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26950 91177308-0d34-0410-b5e6-96231b3b80d8

Fix PSHUF* and SHUF* jit code emission problems

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26949 91177308-0d34-0410-b5e6-96231b3b80d8

Eliminate the dependency of ExecutionEngine on the JIT/Interpreter libraries.

Now you can build a tool with just the JIT or just the interpreter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26946 91177308-0d34-0410-b5e6-96231b3b80d8

wrap lines to 80 columns.

Add static JITCtor/InterpCtor fields

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26945 91177308-0d34-0410-b5e6-96231b3b80d8

This has been implemented.  Tweak it into another note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26944 91177308-0d34-0410-b5e6-96231b3b80d8

When possible, custom lower 32-bit SINT_TO_FP to this:

_foo2:
        extsw r2, r3
        std r2, -8(r1)
        lfd f0, -8(r1)
        fcfid f0, f0
        frsp f1, f0
        blr

instead of this:

_foo2:
        lis r2, ha16(LCPI2_0)
        lis r4, 17200
        xoris r3, r3, 32768
        stw r3, -4(r1)
        stw r4, -8(r1)
        lfs f0, lo16(LCPI2_0)(r2)
        lfd f1, -8(r1)
        fsub f0, f1, f0
        frsp f1, f0
        blr

This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for "ri" addressing modes where the immediate is a 14-bit field
which is shifted left two bits before use.  Instructions like STD use this
addressing mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26942 91177308-0d34-0410-b5e6-96231b3b80d8

fix a warning

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26941 91177308-0d34-0410-b5e6-96231b3b80d8

Some splat and shuffle support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26940 91177308-0d34-0410-b5e6-96231b3b80d8

Add a couple more pseudo instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26939 91177308-0d34-0410-b5e6-96231b3b80d8

Endianness does not affect the order of vector fields.  This fixes
SingleSource/UnitTests/Vector/build.c

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26936 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26935 91177308-0d34-0410-b5e6-96231b3b80d8

Enclose some variables in a scope to avoid error with some gcc versions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26934 91177308-0d34-0410-b5e6-96231b3b80d8

Didn't mean to check this in. No MMX support yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26933 91177308-0d34-0410-b5e6-96231b3b80d8

- Use movaps to store 128-bit vector integers.
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26932 91177308-0d34-0410-b5e6-96231b3b80d8

add expand support for extractelement

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26931 91177308-0d34-0410-b5e6-96231b3b80d8

These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26930 91177308-0d34-0410-b5e6-96231b3b80d8

Don't forget to promote xform function to an explicit node for def : Pat<>
patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26929 91177308-0d34-0410-b5e6-96231b3b80d8

add some trivial support for extractelement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26928 91177308-0d34-0410-b5e6-96231b3b80d8

add some nodes for extractelement

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26927 91177308-0d34-0410-b5e6-96231b3b80d8

Don't emit pseudo instructions!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26926 91177308-0d34-0410-b5e6-96231b3b80d8

Add a hacky workaround for crashes due to vectors live across blocks.
Note that this code won't work for vectors that aren't legal on the
target.  Improvements coming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26925 91177308-0d34-0410-b5e6-96231b3b80d8

Update readme

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26924 91177308-0d34-0410-b5e6-96231b3b80d8

Add an integer splat test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26923 91177308-0d34-0410-b5e6-96231b3b80d8

Print absolute memory references like this:

       lwz r2, 8(0)
instead of this:
       lwz r2, 8(r0)

This fixes the llc/llc-beta failures on PPC last night.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26922 91177308-0d34-0410-b5e6-96231b3b80d8

Combine 2 entries

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26921 91177308-0d34-0410-b5e6-96231b3b80d8

Add a note about x86 register coallescing

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26920 91177308-0d34-0410-b5e6-96231b3b80d8

- Remove scalar to vector pseudo ops. They are just wrong.
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26919 91177308-0d34-0410-b5e6-96231b3b80d8

minor code simplification

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26918 91177308-0d34-0410-b5e6-96231b3b80d8

With Evan's latest tblgen patch, this code is obsolete, thanks Evan!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26917 91177308-0d34-0410-b5e6-96231b3b80d8

Cause the various warnings list to be generated via a <ul> list with
text enclosed in <tt>. This ensures that (a) the text is in a fixed width
font (to indicated generated text) and (b) the text wraps without causing
the page width to be extended. The main result of this is that the report
will wrap to conform to the window size in which it is displayed instead of
having a very wide length if a warning message is long.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26916 91177308-0d34-0410-b5e6-96231b3b80d8

Document ENABLE_ASSERTIONS=1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26915 91177308-0d34-0410-b5e6-96231b3b80d8

Enable assertions to be enabled in release builds by building with
make ENABLE_OPTIMIZED=1 ENABLE_ASSERTIONS=1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26914 91177308-0d34-0410-b5e6-96231b3b80d8

When codegen'ing vector MUL using VFMADD, *add* the 0, don't *mul* the 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26913 91177308-0d34-0410-b5e6-96231b3b80d8

minor note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26912 91177308-0d34-0410-b5e6-96231b3b80d8

x86 ISD::SCALAR_TO_VECTOR support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26911 91177308-0d34-0410-b5e6-96231b3b80d8

Junk unused vector register classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26910 91177308-0d34-0410-b5e6-96231b3b80d8

The node wrapped in PatLeaf<> should be treated as a leaf even if it isn't
one, i.e. don't select it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26909 91177308-0d34-0410-b5e6-96231b3b80d8

Handle constant addresses more efficiently, folding the low bits into the
disp field of the load/store if possible.  This compiles
CodeGen/PowerPC/load-constant-addr.ll to:

_test:
        lis r2, 2838
        lfs f1, 26848(r2)
        blr

instead of:

_test:
        lis r2, 2838
        ori r2, r2, 26848
        lfs f1, 0(r2)
        blr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26908 91177308-0d34-0410-b5e6-96231b3b80d8

remove dead variable

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26907 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26906 91177308-0d34-0410-b5e6-96231b3b80d8

Move some common data structures between dom and pdom into the base class

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26905 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a couple of bugs in permute/splat generate, thanks to Nate for actually
figuring these out! :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26904 91177308-0d34-0410-b5e6-96231b3b80d8

Option -enable-x86-lsr has been removed

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26903 91177308-0d34-0410-b5e6-96231b3b80d8

reenable this hack, the tblgen version isn't quite ready

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26902 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the pattern for VADDUWM, add i32 splat

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26901 91177308-0d34-0410-b5e6-96231b3b80d8

Use tblgen'd VECTOR_SHUFFLE selection code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26900 91177308-0d34-0410-b5e6-96231b3b80d8

It should be ok for a xform output type to be different from input type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26899 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for generating vspltw, instead of a vperm instruction with a
constant pool load.  This generates significantly nicer code for splats.

When tblgen gets bugfixed, we can remove the custom selection code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26898 91177308-0d34-0410-b5e6-96231b3b80d8

Implement PPC::isSplatShuffleMask and PPC::getVSPLTImmediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26897 91177308-0d34-0410-b5e6-96231b3b80d8

fix duplicate definition errors

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26896 91177308-0d34-0410-b5e6-96231b3b80d8

Add a build_vector node

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26895 91177308-0d34-0410-b5e6-96231b3b80d8

Check in some intermediate code that adds a skeleton for  matching vsplt*
instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26894 91177308-0d34-0410-b5e6-96231b3b80d8

Move a few things around.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26893 91177308-0d34-0410-b5e6-96231b3b80d8

Copy matching pattern's output type info to instruction result pattern.
The instruction patterns do not contain enough information to resolve the
exact type of the destination if it of a generic vector type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26892 91177308-0d34-0410-b5e6-96231b3b80d8

add vector_shuffle

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26891 91177308-0d34-0410-b5e6-96231b3b80d8

Add a new SDTCisIntVectorOfSameSize type constraint

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26890 91177308-0d34-0410-b5e6-96231b3b80d8

fix typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26889 91177308-0d34-0410-b5e6-96231b3b80d8

add vsplat instructions, fix sched description for vperm

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26888 91177308-0d34-0410-b5e6-96231b3b80d8

Custom lower arbitrary VECTOR_SHUFFLE's to VPERM.
TODO: leave specific ones as VECTOR_SHUFFLE's and turn them into specialized
operations like vsplt*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26887 91177308-0d34-0410-b5e6-96231b3b80d8

Claim to have v16i8 for perm masks

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26886 91177308-0d34-0410-b5e6-96231b3b80d8

If a target supports splatting with SHUFFLE_VECTOR, lower to it from BUILD_VECTOR(x,x,x,x)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26885 91177308-0d34-0410-b5e6-96231b3b80d8

TargetData doesn't know the alignment of vectors :(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26884 91177308-0d34-0410-b5e6-96231b3b80d8

add the vperm instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26883 91177308-0d34-0410-b5e6-96231b3b80d8

Add some helper methods

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26882 91177308-0d34-0410-b5e6-96231b3b80d8

Add another helper

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26881 91177308-0d34-0410-b5e6-96231b3b80d8

Add very basic support for VECTOR_SHUFFLE

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26880 91177308-0d34-0410-b5e6-96231b3b80d8

add a node

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26879 91177308-0d34-0410-b5e6-96231b3b80d8

Add a helper method

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26878 91177308-0d34-0410-b5e6-96231b3b80d8

add a note with a testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26877 91177308-0d34-0410-b5e6-96231b3b80d8

The library dependency file in flat format. This file is generated by the
makefile using the utils/GenLibDeps.pl script with the -flat option. It
records the dependencies between libraries in such a way that the
llvm-config script can easily read it (in makefile dependency format).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26876 91177308-0d34-0410-b5e6-96231b3b80d8

First cut at the Makefile for llvm-config. This initial version just provides
the rule for building the LibDeps.txt file using GenLibDeps.pl. This needs
to be done from time to time manually in order to keep LibDeps.txt up to
date.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26875 91177308-0d34-0410-b5e6-96231b3b80d8

Add a note about the MUL -> FMADD vector bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26874 91177308-0d34-0410-b5e6-96231b3b80d8

Add a -flat option for generating the library dependencies in a flat
format with one library per line, similar to a makefile dependency list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26873 91177308-0d34-0410-b5e6-96231b3b80d8

Teach cee to propagate through switch statements.  This implements
Transforms/CorrelatedExprs/switch.ll

Patch contributed by Eric Kidd!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26872 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase, contributed by Eric Kidd.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26871 91177308-0d34-0410-b5e6-96231b3b80d8