Tim Northover [Fri, 28 Mar 2014 13:52:56 +0000 (13:52 +0000)]
R600: avoid calling std::next on an iterator that might be end()
This was causing my llc to go into an infinite loop on
CodeGen/R600/address-space.ll (just triggered recently by some allocator
changes).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205005
91177308-0d34-0410-b5e6-
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Tim Northover [Fri, 28 Mar 2014 12:31:39 +0000 (12:31 +0000)]
Intrinsics: expand semantics of LLVMExtendedVectorType (& trunc)
These are used in the ARM backends to aid type-checking on patterns involving
intrinsics. By making sure one argument is an extended/truncated version of
another.
However, there's no reason to limit them to just vectors types. For example
AArch64 has the instruction "uqshrn sD, dN, #imm" which would naturally use an
intrinsic taking an i64 and returning an i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205003
91177308-0d34-0410-b5e6-
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Chandler Carruth [Fri, 28 Mar 2014 09:18:42 +0000 (09:18 +0000)]
[Allocator Cleanup] Sink the private data members and methods to the
bottom of the interface to make it easier to scan and find the public
API.
No functionality changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204996
91177308-0d34-0410-b5e6-
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Chandler Carruth [Fri, 28 Mar 2014 09:08:14 +0000 (09:08 +0000)]
[Allocator Cleanup] Move generic pointer alignment helper out of an
out-of-line private static method and into the collection of inline
alignment helpers in MathExtras.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204995
91177308-0d34-0410-b5e6-
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Chandler Carruth [Fri, 28 Mar 2014 08:53:25 +0000 (08:53 +0000)]
[Allocator Cleanup] Make the growth of the "slab" size of the
BumpPtrAllocator significantly less strange by making it a simple
function of the number of slabs allocated rather than by making it
a recurrance. I *think* the previous behavior was essentially that the
size of the slabs would be doubled after the first 128 were allocated,
and then doubled again each time 64 more were allocated, but only if
every allocation packed perfectly into the slab size. If not, the wasted
space wouldn't be counted toward increasing the size, but allocations
over the size threshold *would*. And since the allocations over the size
threshold might be much larger than the slab size, this could have
somewhat surprising consequences where we rapidly grow the slab size.
This currently requires adding state to the allocator to track the
number of slabs currently allocated, but that isn't too bad. I'm
planning further changes to the allocator that will make this state fall
out even more naturally.
It still doesn't fully decouple the growth rate from the allocations
which are over the size threshold. That fix is coming later.
This specific fix will allow making the entire thing into a more
stateless device and lifting the parameters into template parameters
rather than runtime parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204993
91177308-0d34-0410-b5e6-
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Chandler Carruth [Fri, 28 Mar 2014 08:53:08 +0000 (08:53 +0000)]
[cleanup] Hoist the initialization and constants for slab sizes to the
top of the default jit memory manager. This will allow them to be used
as template parameters rather than runtime parameters in a subsequent
commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204992
91177308-0d34-0410-b5e6-
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David Blaikie [Thu, 27 Mar 2014 23:42:21 +0000 (23:42 +0000)]
PBQP: Minor cleanups to r204857
* Use assignment instead of swap (since the original value is being
destroyed anyway)
* Rename "updateAdjEdgeId" to "setAdjEdgeId"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204983
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Adrian Prantl [Thu, 27 Mar 2014 23:30:04 +0000 (23:30 +0000)]
C++11: convert verbose loops to range-based loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204981
91177308-0d34-0410-b5e6-
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Hal Finkel [Thu, 27 Mar 2014 23:12:31 +0000 (23:12 +0000)]
[PowerPC] Use a small cleanup pass to remove VSX self copies
As explained in r204976, because of how the allocation of VSX registers
interacts with the call-lowering code, we sometimes end up generating self VSX
copies. Specifically, things like this:
%VSL2<def> = COPY %F2, %VSL2<imp-use,kill>
(where %F2 is really a sub-register of %VSL2, and so this copy is a nop)
This adds a small cleanup pass to remove these prior to post-RA scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204980
91177308-0d34-0410-b5e6-
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Manman Ren [Thu, 27 Mar 2014 23:10:04 +0000 (23:10 +0000)]
Provide a target override for the cost of using a callee-saved register
for the first time.
Thanks Andy for the discussion.
rdar://
16162005
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204979
91177308-0d34-0410-b5e6-
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Saleem Abdulrasool [Thu, 27 Mar 2014 22:50:05 +0000 (22:50 +0000)]
Canonicalise Windows target triple spellings
Construct a uniform Windows target triple nomenclature which is congruent to the
Linux counterpart. The old triples are normalised to the new canonical form.
This cleans up the long-standing issue of odd naming for various Windows
environments.
There are four different environments on Windows:
MSVC: The MS ABI, MSVCRT environment as defined by Microsoft
GNU: The MinGW32/MinGW32-W64 environment which uses MSVCRT and auxiliary libraries
Itanium: The MSVCRT environment + libc++ built with Itanium ABI
Cygnus: The Cygwin environment which uses custom libraries for everything
The following spellings are now written as:
i686-pc-win32 => i686-pc-windows-msvc
i686-pc-mingw32 => i686-pc-windows-gnu
i686-pc-cygwin => i686-pc-windows-cygnus
This should be sufficiently flexible to allow us to target other windows
environments in the future as necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204977
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Hal Finkel [Thu, 27 Mar 2014 22:46:28 +0000 (22:46 +0000)]
[PowerPC] Don't remove self VSX copies in PPCInstrInfo::copyPhysReg
Because of how the allocation of VSX registers interacts with the call-lowering
code, we sometimes end up generating self VSX copies. Specifically, things like
this:
%VSL2<def> = COPY %F2, %VSL2<imp-use,kill>
(where %F2 is really a sub-register of %VSL2, and so this copy is a nop)
The problem is that ExpandPostRAPseudos always assumes that *some* instruction
has been inserted, and adds implicit defs to it. This is a problem if no copy
was inserted because it can cause subtle problems during post-RA scheduling.
These self copies will have to be removed some other way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204976
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Lang Hames [Thu, 27 Mar 2014 22:45:42 +0000 (22:45 +0000)]
Temporarily remove assert while I dig in to issues that it's causing for LLDB.
<rdar://problem/
16349536>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204975
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Rui Ueyama [Thu, 27 Mar 2014 22:36:06 +0000 (22:36 +0000)]
Revert "[C++11] Do not check __GXX_EXPERIMENTAL_CXX0X__."
This reverts commit r204964 because it disabled "= delete", "constexpr"
and "explicit" on GCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204973
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Quentin Colombet [Thu, 27 Mar 2014 22:27:41 +0000 (22:27 +0000)]
[X86][Vector Cost Model] Add a comment to explain the workaround
in my previous commit (r204884).
<rdar://problem/
16381225>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204972
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Hal Finkel [Thu, 27 Mar 2014 22:22:48 +0000 (22:22 +0000)]
[PowerPC] Fix v2f64 vector extract and related patterns
First, v2f64 vector extract had not been declared legal (and so the existing
patterns were not being used). Second, the patterns for that, and for
scalar_to_vector, should really be a regclass copy, not a subregister
operation, because the VSX registers directly hold both the vector and scalar data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204971
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Rui Ueyama [Thu, 27 Mar 2014 21:56:29 +0000 (21:56 +0000)]
[C++11] Do not check __GXX_EXPERIMENTAL_CXX0X__.
Summary: Checking the experimental flag for C++0x is no longer needed.
Differential Revision: http://llvm-reviews.chandlerc.com/D3206
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204964
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Hal Finkel [Thu, 27 Mar 2014 21:26:33 +0000 (21:26 +0000)]
[PowerPC] Expand v2i64 shifts
These operations need to be expanded during legalization so that isel does not
crash. In theory, we might be able to custom lower some of these. That,
however, would need to be follow-up work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204963
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Manman Ren [Thu, 27 Mar 2014 21:21:57 +0000 (21:21 +0000)]
Register Allocator: refactoring and add comments.
No functionality change. Thanks Andy for reviewing.
rdar://
16162005
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204962
91177308-0d34-0410-b5e6-
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Rafael Espindola [Thu, 27 Mar 2014 20:49:35 +0000 (20:49 +0000)]
Remove another unused argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204961
91177308-0d34-0410-b5e6-
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Hans Wennborg [Thu, 27 Mar 2014 20:48:37 +0000 (20:48 +0000)]
Win installer: provide a pretty icon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204960
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David Blaikie [Thu, 27 Mar 2014 20:45:58 +0000 (20:45 +0000)]
DebugInfo: Support for compressed debug info sections
1) When creating a .debug_* section and instead create a .zdebug_
section.
2) When creating a fragment in a .zdebug_* section, make it a compressed
fragment.
3) When computing the size of a compressed section, compress the data
and use the size of the compressed data.
4) Emit the compressed bytes.
Also, check that only if a section has a compressed fragment, then that
is the only fragment in the section.
Assert-fail if the fragment's data is modified after it is compressed.
Initial review on llvm-commits by Eric Christopher and Rafael Espindola.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204958
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David Blaikie [Thu, 27 Mar 2014 20:45:41 +0000 (20:45 +0000)]
DebugInfo: TargetOptions/MCAsmInfo support for compressed debug info sections
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204957
91177308-0d34-0410-b5e6-
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Rafael Espindola [Thu, 27 Mar 2014 20:41:17 +0000 (20:41 +0000)]
Remove unused argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204956
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Reid Kleckner [Thu, 27 Mar 2014 17:49:27 +0000 (17:49 +0000)]
InstCombine: Don't combine constants on unsigned icmps
Fixes a miscompile introduced in r204912. It would miscompile code like
(unsigned)(a + -49) <= 5U. The transform would turn this into
(unsigned)a < 55U, which would return true for values in [0, 49], when
it should not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204948
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Matt Arsenault [Thu, 27 Mar 2014 17:23:31 +0000 (17:23 +0000)]
R600: Implement isZExtFree.
This allows 64-bit operations that are truncated to be reduced
to 32-bit ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204946
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Matt Arsenault [Thu, 27 Mar 2014 17:23:24 +0000 (17:23 +0000)]
R600/SI: Fix unreachable with a sext_in_reg to an illegal type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204945
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Daniel Sanders [Thu, 27 Mar 2014 16:42:17 +0000 (16:42 +0000)]
[mips] Some uses of isMips64()/hasMips64() are really tests for 64-bit GPR's
Summary:
No functional change since these predicates are (currently) synonymous.
Extracted from a patch by David Chisnall
His work was sponsored by: DARPA, AFRL
Differential Revision: http://llvm-reviews.chandlerc.com/D3202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204943
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Logan Chien [Thu, 27 Mar 2014 16:28:09 +0000 (16:28 +0000)]
[AArch64] Lower SHL_PARTS, SRA_PARTS and SRL_PARTS
Lower SHL_PARTS, SRA_PARTS and SRL_PARTS to perform 128-bit integer shift
Patch by GuanHong Liu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204940
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Rafael Espindola [Thu, 27 Mar 2014 15:26:56 +0000 (15:26 +0000)]
Prevent alias from pointing to weak aliases.
This adds back r204781.
Original message:
Aliases are just another name for a position in a file. As such, the
regular symbol resolutions are not applied. For example, given
define void @my_func() {
ret void
}
@my_alias = alias weak void ()* @my_func
@my_alias2 = alias void ()* @my_alias
We produce without this patch:
.weak my_alias
my_alias = my_func
.globl my_alias2
my_alias2 = my_alias
That is, in the resulting ELF file my_alias, my_func and my_alias are
just 3 names pointing to offset 0 of .text. That is *not* the
semantics of IR linking. For example, linking in a
@my_alias = alias void ()* @other_func
would require the strong my_alias to override the weak one and
my_alias2 would end up pointing to other_func.
There is no way to represent that with aliases being just another
name, so the best solution seems to be to just disallow it, converting
a miscompile into an error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204934
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Daniel Sanders [Thu, 27 Mar 2014 15:00:44 +0000 (15:00 +0000)]
[mips] Attempting to use register $32 should be an error instead of an assertion.
Reviewers: matheusalmeida
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3201
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204932
91177308-0d34-0410-b5e6-
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Aaron Ballman [Thu, 27 Mar 2014 14:10:00 +0000 (14:10 +0000)]
The forward declare should be a struct instead of a class (to be consistent with the definition, as well as to silence an MSVC C4099 warning).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204928
91177308-0d34-0410-b5e6-
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Daniel Sanders [Thu, 27 Mar 2014 13:52:53 +0000 (13:52 +0000)]
[mips] Add support for .cpsetup
Summary:
Patch by Robert N. M. Watson
His work was sponsored by: DARPA, AFRL
Small corrections by myself.
CC: theraven, matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3199
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204924
91177308-0d34-0410-b5e6-
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Daniel Sanders [Thu, 27 Mar 2014 12:49:34 +0000 (12:49 +0000)]
[mips] The decision between GOT_DISP and GOT16 for global addresses depends on ABI rather than MIPS64
Summary: No functional change (for supported use cases)
Reviewers: matheusalmeida
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3191
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204922
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Zoran Jovanovic [Thu, 27 Mar 2014 12:38:40 +0000 (12:38 +0000)]
Split the file MipsAsmBackend.cpp in Split the file MipsAsmBackend.cpp and Split the file MipsAsmBackend.h.
Differential Revision: http://llvm-reviews.chandlerc.com/D3134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204921
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Karthik Bhat [Thu, 27 Mar 2014 12:08:23 +0000 (12:08 +0000)]
All new elements except the last one initialized to NULL. Ideally, once parsing is complete, all elements should be non-NULL.
To safe-guard BitcodeReader, this patch adds null check for all access to these list.
Patch by Dinesh Dwivedi!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204920
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Matheus Almeida [Thu, 27 Mar 2014 12:02:48 +0000 (12:02 +0000)]
[mips] Remove unused private field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204919
91177308-0d34-0410-b5e6-
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Matheus Almeida [Thu, 27 Mar 2014 11:52:20 +0000 (11:52 +0000)]
[mips] NaCl should now use the custom MipsELFStreamer (recently added) in spite
of MCELFStreamer.
This is so that changes to MipsELFStreamer will automatically propagate through
its subclasses.
No functional changes (MipsELFStreamer has the same functionality of MCELFStreamer
at the moment).
Differential Revision: http://llvm-reviews.chandlerc.com/D3130
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204918
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Matheus Almeida [Thu, 27 Mar 2014 11:39:03 +0000 (11:39 +0000)]
[mips] Implement custom MCELFStreamer.
This allows us to insert some hooks before emitting data into an actual object file.
For example, we can capture the register usage for a translation unit by overriding
the EmitInstruction method. The register usage information is needed to generate
.reginfo and .Mips.options ELF sections.
No functional changes.
Differential Revision: http://llvm-reviews.chandlerc.com/D3129
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204917
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NAKAMURA Takumi [Thu, 27 Mar 2014 11:38:28 +0000 (11:38 +0000)]
Untabify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204916
91177308-0d34-0410-b5e6-
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NAKAMURA Takumi [Thu, 27 Mar 2014 11:33:11 +0000 (11:33 +0000)]
SmallVector<3> may be used here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204915
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NAKAMURA Takumi [Thu, 27 Mar 2014 11:32:41 +0000 (11:32 +0000)]
IRTests/InstructionsTest.cpp: Avoid initializer list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204914
91177308-0d34-0410-b5e6-
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Erik Verbruggen [Thu, 27 Mar 2014 11:16:05 +0000 (11:16 +0000)]
InstCombine: merge constants in both operands of icmp.
Transform:
icmp X+Cst2, Cst
into:
icmp X, Cst-Cst2
when Cst-Cst2 does not overflow, and the add has nsw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204912
91177308-0d34-0410-b5e6-
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Daniel Sanders [Thu, 27 Mar 2014 10:46:12 +0000 (10:46 +0000)]
[mips] Stop caching the result of hasMips64(), isABI_O32(), isABI_N32(), and isABI_N64() from MipsSubTarget in MipsTargetLowering
Summary:
The short name is quite convenient so provide an accessor for them instead.
No functional change
Depends on D3177
Reviewers: matheusalmeida
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204911
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Chandler Carruth [Thu, 27 Mar 2014 09:56:23 +0000 (09:56 +0000)]
[cleanup] Run clang-format over these routines to remove formatting
differences from subsequent diffs, and ease review. Going to be
performing some major surgery to simplify this stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204908
91177308-0d34-0410-b5e6-
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Chandler Carruth [Thu, 27 Mar 2014 09:53:31 +0000 (09:53 +0000)]
[cleanup] Modernize doxygen comments for the BumpPtrAllocator and
rewrite some of them to be more clear.
The terminology being used in our allocators is making me really sad. We
call things slab allocators that aren't at all slab allocators. It is
quite confusing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204907
91177308-0d34-0410-b5e6-
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Elena Demikhovsky [Thu, 27 Mar 2014 09:45:08 +0000 (09:45 +0000)]
AVX-512: Implemented masking for integer arithmetic & logic instructions.
By Robert Khasanov rob.khasanov@gmail.com
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204906
91177308-0d34-0410-b5e6-
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Timur Iskhodzhanov [Thu, 27 Mar 2014 08:52:14 +0000 (08:52 +0000)]
Add a PR reference
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204904
91177308-0d34-0410-b5e6-
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Timur Iskhodzhanov [Thu, 27 Mar 2014 08:46:44 +0000 (08:46 +0000)]
Make the recent COFF debug info tests more readable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204902
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Stepan Dyatkovskiy [Thu, 27 Mar 2014 08:38:18 +0000 (08:38 +0000)]
Rejected r204899 and r204900 due to remaining test failures on cmake-llvm-x86_64-linux buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204901
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Stepan Dyatkovskiy [Thu, 27 Mar 2014 08:20:26 +0000 (08:20 +0000)]
Fixed test for r204899 (pr18931 fix)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204900
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Stepan Dyatkovskiy [Thu, 27 Mar 2014 07:49:39 +0000 (07:49 +0000)]
Fix for pr18931: Crash using integrated assembler with immediate arithmetic
Fix description:
Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage,
since it is impossible to resolve labels on this stage. In the end of stage we still have
expression (MCExpr).
Then, when we want to encode it, we expect it to be an immediate, but it still an expression.
Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204899
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Jiangning Liu [Thu, 27 Mar 2014 07:42:58 +0000 (07:42 +0000)]
ARM: raise error message when complex SO expressions can't really be
solved as a constant at compilation time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204898
91177308-0d34-0410-b5e6-
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Lang Hames [Thu, 27 Mar 2014 02:58:32 +0000 (02:58 +0000)]
Add missing #include <cassert> to MCSymbolizer.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204894
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Lang Hames [Thu, 27 Mar 2014 02:49:18 +0000 (02:49 +0000)]
Assert that MCSymbolizer is constructed with a valid (or at least non-null)
RelocationInfo argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204893
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Lang Hames [Thu, 27 Mar 2014 02:42:52 +0000 (02:42 +0000)]
Move MCSymbolizer's constructor into header. It's trivial - there's no need for
it to be out-of-line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204892
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Lang Hames [Thu, 27 Mar 2014 02:39:01 +0000 (02:39 +0000)]
Update MCSymbolizer and its subclasses' constructors to reflect the fact that
they take ownership of the RelocationInfo they're constructed with.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204891
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Reid Kleckner [Thu, 27 Mar 2014 01:38:48 +0000 (01:38 +0000)]
inalloca: *Really* fix the docs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204890
91177308-0d34-0410-b5e6-
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Reid Kleckner [Thu, 27 Mar 2014 01:34:51 +0000 (01:34 +0000)]
Remove unneeded stale type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204889
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Reid Kleckner [Thu, 27 Mar 2014 01:32:22 +0000 (01:32 +0000)]
inalloca: Fix incorrect example IR and remove LangRef warning
The LangRef warning wasn't formatting the way I intended it to anyway.
Surprisingly inalloca appears to work, even when optimizations are
enabled. We generate very bad code for it, but we can self-host and run
lots of big tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204888
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Lang Hames [Thu, 27 Mar 2014 01:05:49 +0000 (01:05 +0000)]
Remove forward declaration for Target class - Target is already defined here.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204885
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Quentin Colombet [Thu, 27 Mar 2014 00:52:16 +0000 (00:52 +0000)]
[X86][Vectorizer Cost Model] Correct vectorization cost model for v2i64->v2f64
and v4i64->v4f64.
The new costs match what we did for SSE2 and reflect the reality of our codegen.
<rdar://problem/
16381225>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204884
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Rafael Espindola [Thu, 27 Mar 2014 00:28:24 +0000 (00:28 +0000)]
Correctly propagates st_size.
This also finally removes a bogus call to AliasedSymbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204883
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Jim Grosbach [Thu, 27 Mar 2014 00:20:42 +0000 (00:20 +0000)]
add 'requires asserts' to test that needs it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204882
91177308-0d34-0410-b5e6-
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Justin Bogner [Thu, 27 Mar 2014 00:06:36 +0000 (00:06 +0000)]
llvm-cov: When reading strings in gcov data, skip leading zeros
It seems that gcov, when faced with a string that is apparently zero
length, just keeps reading words until it finds a length it likes
better. I'm not really sure why this is, but it's simple enough to
make llvm-cov follow suit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204881
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Jim Grosbach [Thu, 27 Mar 2014 00:04:11 +0000 (00:04 +0000)]
X86: Correct vectorization cost model for v8f32->v8i8.
Fix the cost model to reflect the reality of our codegen.
rdar://
16370633
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204880
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Nick Lewycky [Wed, 26 Mar 2014 23:45:15 +0000 (23:45 +0000)]
Treat lifetime.start'd memory like we treat freshly alloca'd memory. Patch by Björn Steinbrink!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204876
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Eric Christopher [Wed, 26 Mar 2014 23:10:28 +0000 (23:10 +0000)]
Reorder arguments on test command line to make it easier to cut and
paste.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204875
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Hal Finkel [Wed, 26 Mar 2014 22:58:37 +0000 (22:58 +0000)]
[PowerPC] Generate VSX permutations for v2[fi]64 vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204873
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Justin Bogner [Wed, 26 Mar 2014 22:51:39 +0000 (22:51 +0000)]
llvm-cov: Move XFAIL after the body of the test
llvm-cov tests are sensitive to line number changes, so putting this
at the end will limit churn when we fix the XFAIL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204871
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Justin Bogner [Wed, 26 Mar 2014 22:36:48 +0000 (22:36 +0000)]
llvm-cov: Disable test on big endian machines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204868
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Reid Kleckner [Wed, 26 Mar 2014 22:26:35 +0000 (22:26 +0000)]
CloneFunction: Clone all attributes, including the CC
Summary:
Tested with a unit test because we don't appear to have any transforms
that use this other than ASan, I think.
Fixes PR17935.
Reviewers: nicholas
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D3194
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204866
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Ekaterina Romanova [Wed, 26 Mar 2014 22:15:28 +0000 (22:15 +0000)]
This is a fix for PR# 19051. I noticed code gen differences due to code motion when running tests with and without the debug info at O2. The problem is in branch folding. A loop wanted to skip the debug info, but actually it didn't do so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204865
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Manman Ren [Wed, 26 Mar 2014 22:14:09 +0000 (22:14 +0000)]
Add comments. Addressing review comments from Evan on r204690.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204864
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Justin Bogner [Wed, 26 Mar 2014 22:03:06 +0000 (22:03 +0000)]
llvm-cov: Handle functions with no line number
Functions may in an instrumented binary but not in the original source
when they're inserted by the compiler or the runtime. These functions
aren't meaningful to the user, so teach llvm-cov to skip over them
instead of crashing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204863
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Kevin Enderby [Wed, 26 Mar 2014 21:54:11 +0000 (21:54 +0000)]
Fix a problem with the ARM assembler incorrectly matching a
vector list parameter that is using all lanes "{d0[], d2[]}" but can
match and instruction with a ”{d0, d2}" parameter.
I’m finishing up a fix for proper checking of the unsupported
alignments on vld/vst instructions and ran into this. Thus I don’t
have a test case at this time. And adding all code that will
demonstrate the bug would obscure the very simple one line fix.
So if you would indulge me on not having a test case at this
time I’ll instead offer up a detailed explanation of what is
going on in this commit message.
This instruction:
vld2.8 {d0[], d2[]}, [r4:64]
is not legal as the alignment can only be 16 when the size is 8.
Per this documentation:
A8.8.325 VLD2 (single 2-element structure to all lanes)
<align> The alignment. It can be one of:
16 2-byte alignment, available only if <size> is 8, encoded as a = 1.
32 4-byte alignment, available only if <size> is 16, encoded as a = 1.
64 8-byte alignment, available only if <size> is 32, encoded as a = 1.
omitted Standard alignment, see Unaligned data access on page A3-108.
So when code is added to the llvm integrated assembler to not match
that instruction because of the alignment it then goes on to try to match
other instructions and comes across this:
vld2.8 {d0, d2}, [r4:64]
and and matches it. This is because of the method
ARMOperand::isVecListDPairSpaced() is missing the check of the Kind.
In this case the Kind is k_VectorListAllLanes . While the name of the method
may suggest that this is OK it really should check that the Kind is
k_VectorList.
As the method ARMOperand::isDoubleSpacedVectorAllLanes() is what was
used to match {d0[], d2[]} and correctly checks the Kind:
bool isDoubleSpacedVectorAllLanes() const {
return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
}
where the original ARMOperand::isVecListDPairSpaced() does not check
the Kind:
bool isVecListDPairSpaced() const {
if (isSingleSpacedVectorList()) return false;
return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
.contains(VectorList.RegNum));
}
Jim Grosbach has reviewed the change and said: Yep, that sounds right. …
And by "right" I mean, "wow, that's a nasty latent bug I'm really, really
glad to see fixed." :)
rdar://
16436683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204861
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Eli Bendersky [Wed, 26 Mar 2014 21:46:24 +0000 (21:46 +0000)]
Add a unit test for Invoke iteration, similar to the one for Call
The tests are refactored to use the same fixture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204860
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Arnold Schwaighofer [Wed, 26 Mar 2014 21:30:19 +0000 (21:30 +0000)]
PR15967 Fix in basicaa for faulty returning no alias.
This commit consist of two parts.
The first part fix the PR15967. The wrong conclusion was made when the MaxLookup
limit was reached. The fix introduce a out parameter (MaxLookupReached) to
DecomposeGEPExpression that the function aliasGEP can act upon.
The second part is introducing the constant MaxLookupSearchDepth to make sure
that DecomposeGEPExpression and GetUnderlyingObject use the same search depth.
This is a small cleanup to clarify the original algorithm.
Patch by Karl-Johan Karlsson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204859
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Lang Hames [Wed, 26 Mar 2014 21:21:53 +0000 (21:21 +0000)]
Simplify PBQP graph removeAdjEdgeId implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204857
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Eli Bendersky [Wed, 26 Mar 2014 21:11:34 +0000 (21:11 +0000)]
Fix bot breakage in InstructionsTest.
Makes sure the Call dies before the Function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204856
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Eli Bendersky [Wed, 26 Mar 2014 20:41:15 +0000 (20:41 +0000)]
Fix problem with r204836
In CallInst, op_end() points at the callee, which we don't want to iterate over
when just iterating over arguments. Now take this into account when returning
a iterator_range from arg_operands. Similar reasoning for InvokeInst.
Also adds a unit test to verify this actually works as expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204851
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Hal Finkel [Wed, 26 Mar 2014 19:39:09 +0000 (19:39 +0000)]
[PowerPC] VSX loads and stores support unaligned access
I've not yet updated PPCTTI because I'm not sure what the actual relative cost
is compared to the aligned uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204848
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Kevin Enderby [Wed, 26 Mar 2014 19:35:40 +0000 (19:35 +0000)]
Fix the ARM VST4 (single 4-element structure from one lane)
size 16 double-spaced registers instruction printing.
This:
vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]!
was being printed as:
vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]!
rdar://
16435096
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204847
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Lang Hames [Wed, 26 Mar 2014 19:22:51 +0000 (19:22 +0000)]
Remove PBQP-cost dimension sanity assertion in PBQP::Graph::addConstructedEdge.
We're already effectively checking sanity for that in PBQP::Graph::addEdge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204844
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Hal Finkel [Wed, 26 Mar 2014 19:13:54 +0000 (19:13 +0000)]
[PowerPC] Use v2f64 <-> v2i64 VSX conversion instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204843
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Lang Hames [Wed, 26 Mar 2014 18:58:00 +0000 (18:58 +0000)]
Change the PBQP graph adjacency list structure from std::set to std::vector.
The edge data structure (EdgeEntry) now holds the indices of its entries in the
adjacency lists of the nodes it connects. This trades a little ugliness for
faster insertion/removal, which is now O(1) with a cheap constant factor. All
of this is implementation detail within the PBQP graph, the external API remains
unchanged.
Individual register allocations are likely to change, since the adjacency lists
will now be ordered differently (or rather, will now be unordered). This
shouldn't affect the average quality of allocations however.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204841
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Matt Arsenault [Wed, 26 Mar 2014 18:31:06 +0000 (18:31 +0000)]
R600: Add a testcase for sext_in_reg I missed.
This sext_inreg i32 in i64 case was already handled, but not enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204840
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Hal Finkel [Wed, 26 Mar 2014 18:26:36 +0000 (18:26 +0000)]
[PowerPC] Remove some dead VSX v4f32 store patterns
These patterns are dead (because v4f32 stores are currently promoted to v4i32
and stored using Altivec instructions), and also are likely not correct
(because they'd store the vector elements in the opposite order from that
assumed by the rest of the Altivec code).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204839
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Hal Finkel [Wed, 26 Mar 2014 18:26:30 +0000 (18:26 +0000)]
[PowerPC] Use VSX vector load/stores for v2[fi]64
These instructions have access to the complete VSX register file. In addition,
they "swap" the order of the elements so that element 0 (the scalar part) comes
first in memory and element 1 follows at a higher address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204838
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Juergen Ributzka [Wed, 26 Mar 2014 18:19:27 +0000 (18:19 +0000)]
[MCJIT] Check if there have been errors during RuntimeDyld execution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204837
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Eli Bendersky [Wed, 26 Mar 2014 18:18:02 +0000 (18:18 +0000)]
Enable range-for iteration over call/invoke arguments.
Similar to r204835
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204836
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Eli Bendersky [Wed, 26 Mar 2014 18:04:27 +0000 (18:04 +0000)]
Add args() iteartor adapter to Function, for range-for loops.
This patch is in similar vein to what done earlier to Module::globals/aliases
etc. It allows to iterate over function arguments like this:
for (Argument Arg : F.args()) {
...
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204835
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Jim Grosbach [Wed, 26 Mar 2014 17:27:01 +0000 (17:27 +0000)]
Fix for incorrect address sinking in the presence of potential overflows.
In some cases it is possible for CGP to attempt to reuse a base address from
another basic block. In those cases we have to be sure that all the address
math was either done at the same bit width, or that none of it overflowed
before it was extended.
Patch by Louis Gerbarg <lgg@apple.com>
rdar://
16307442
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204833
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Hans Wennborg [Wed, 26 Mar 2014 16:30:54 +0000 (16:30 +0000)]
Revert "X86 memcpy lowering: use "rep movs" even when esi is used as base pointer" (r204174)
> For functions where esi is used as base pointer, we would previously fall ba
> from lowering memcpy with "rep movs" because that clobbers esi.
>
> With this patch, we just store esi in another physical register, and restore
> it afterwards. This adds a little bit of register preassure, but the more
> efficient memcpy should be worth it.
>
> Differential Revision: http://llvm-reviews.chandlerc.com/D2968
This didn't work. I was ending up with code like this:
lea edi,[esi+38h]
mov ecx,0Fh
mov edx,esi
mov esi,ebx
rep movs dword ptr es:[edi],dword ptr [esi]
lea ecx,[esi+74h] <-- Ooops, we're now using esi before restoring it from edx.
add ebx,3Ch
mov esi,edx
I guess if we want to do this we need stronger glue or something, or doing the expansion
much later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204829
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Hal Finkel [Wed, 26 Mar 2014 16:12:58 +0000 (16:12 +0000)]
[PowerPC] Add v2i64 as a legal VSX type
v2i64 needs to be a legal VSX type because it is the SetCC result type from
v2f64 comparisons. We need to expand all non-arithmetic v2i64 operations.
This fixes the lowering for v2f64 VSELECT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204828
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Matheus Almeida [Wed, 26 Mar 2014 16:09:43 +0000 (16:09 +0000)]
[mips] Use TwoOperandAliasConstraint for ArithLogicR instructions.
This enables TableGen to generate an additional two operand matcher
for our ArithLogicR class of instructions (constituted by 3 register operands).
E.g.: and $1, $2 <=> and $1, $1, $2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204826
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Matheus Almeida [Wed, 26 Mar 2014 15:44:18 +0000 (15:44 +0000)]
[mips] Add support to the '.dword' directive.
The '.dword' directive accepts a list of expressions and emits
them in 8-byte chunks in successive locations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204822
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Joerg Sonnenberger [Wed, 26 Mar 2014 15:30:21 +0000 (15:30 +0000)]
Clarify that select is only non-branching on the IR-level, it often ends
up as jump table or other forms of branches on the machine level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204819
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Matheus Almeida [Wed, 26 Mar 2014 15:24:36 +0000 (15:24 +0000)]
[mips] Rename function in MipsAsmParser.
parseDirectiveWord is a generic function that parses an expression which
means there's no need for it to have such an specific name. Renaming it to
parseDataDirective so that it can also be used to handle .dword directives[1].
[1]To be added in a follow up commit.
No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204818
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Matheus Almeida [Wed, 26 Mar 2014 15:14:32 +0000 (15:14 +0000)]
[mips] Add support to '.set mips64'.
The '.set mips64' directive enables the feature Mips:FeatureMips64
from assembly. Note that it doesn't modify the ELF header as opposed
to the use of -mips64 from the command-line. The reason for this
is that we want to be as compatible as possible with existing assemblers
like GAS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204817
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