Jakub Staszak [Tue, 4 Sep 2012 23:11:11 +0000 (23:11 +0000)]
BypassSlowDivision: Assign to reference, don't copy the object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163179
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Jakob Stoklund Olesen [Tue, 4 Sep 2012 22:59:30 +0000 (22:59 +0000)]
Search the whole instruction for tied operands.
Implicit uses can be dynamically tied to defs. This will soon be used
for predicated instructions on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163177
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Chad Rosier [Tue, 4 Sep 2012 22:46:24 +0000 (22:46 +0000)]
[ms-inline asm] Add the inline assembly dialect, AsmDialect, to the InlineAsm
class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163175
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Chad Rosier [Tue, 4 Sep 2012 22:29:45 +0000 (22:29 +0000)]
[ms-inline asm] Remove the Inline Asm Non-Standard Dialect attribute. This
implementation does not co-exist well with how the sideeffect and alignstack
attributes are handled. The reverts r161641.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163174
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David Blaikie [Tue, 4 Sep 2012 22:09:04 +0000 (22:09 +0000)]
[LIT] Add a clang_tools_extra_site_cfg to match the various other site_cfg.
This doesn't seem ideal, perhaps we could just keep the llvm_site_cfg and have
other config (clang and clang-tools-extra) derive their site_cfg from that.
Suggestions/complaints/ideas welcome.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163171
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Jakub Staszak [Tue, 4 Sep 2012 21:16:59 +0000 (21:16 +0000)]
Fix my previous patch (r163164). It does now what it is supposed to do:
Doesn't set MadeChange to TRUE if BypassSlowDivision doesn't change anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163165
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Jakub Staszak [Tue, 4 Sep 2012 20:48:24 +0000 (20:48 +0000)]
Return false if BypassSlowDivision doesn't change anything.
Also a few minor changes:
- use pre-inc instead of post-inc
- use isa instead of dyn_cast
- 80 col
- trailing spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163164
91177308-0d34-0410-b5e6-
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Jakub Staszak [Tue, 4 Sep 2012 19:49:17 +0000 (19:49 +0000)]
Remove unneeded code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163160
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Jakob Stoklund Olesen [Tue, 4 Sep 2012 18:44:43 +0000 (18:44 +0000)]
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163154
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Jakob Stoklund Olesen [Tue, 4 Sep 2012 18:43:25 +0000 (18:43 +0000)]
Actually use the MachineOperand field for isRegTiedToDefOperand().
The MachineOperand::TiedTo field was maintained, but not used.
This patch enables it in isRegTiedToDefOperand() and
isRegTiedToUseOperand() which are the actual functions use by the
register allocator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163153
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Jakob Stoklund Olesen [Tue, 4 Sep 2012 18:38:28 +0000 (18:38 +0000)]
Move tie checks into MachineVerifier::visitMachineOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163152
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Jakob Stoklund Olesen [Tue, 4 Sep 2012 18:36:28 +0000 (18:36 +0000)]
Allow tied uses and defs in different orders.
After much agonizing, use a full 4 bits of precious MachineOperand space
to encode this. This uses existing padding, and doesn't grow
MachineOperand beyond its current 32 bytes.
This allows tied defs among the first 15 operands on a normal
instruction, just like the current MCInstrDesc constraint encoding.
Inline assembly needs to be able to tie more than the first 15 operands,
and gets special treatment.
Tied uses can appear beyond 15 operands, as long as they are tied to a
def that's in range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163151
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Preston Gurd [Tue, 4 Sep 2012 18:22:17 +0000 (18:22 +0000)]
Generic Bypass Slow Div
- CodeGenPrepare pass for identifying div/rem ops
- Backend specifies the type mapping using addBypassSlowDivType
- Enabled only for Intel Atom with O2 32-bit -> 8-bit
- Replace IDIV with instructions which test its value and use DIVB if the value
is positive and less than 256.
- In the case when the quotient and remainder of a divide are used a DIV
and a REM instruction will be present in the IR. In the non-Atom case
they are both lowered to IDIVs and CSE removes the redundant IDIV instruction,
using the quotient and remainder from the first IDIV. However,
due to this optimization CSE is not able to eliminate redundant
IDIV instructions because they are located in different basic blocks.
This is overcome by calculating both the quotient (DIV) and remainder (REM)
in each basic block that is inserted by the optimization and reusing the result
values when a subsequent DIV or REM instruction uses the same operands.
- Test cases check for the presents of the optimization when calculating
either the quotient, remainder, or both.
Patch by Tyler Nowicki!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163150
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Bob Wilson [Tue, 4 Sep 2012 17:42:53 +0000 (17:42 +0000)]
Make sure macros in the include subdirectory are not used without being defined.
Rationale: For each preprocessor macro, either the definedness is what's
meaningful, or the value is what's meaningful, or both. If definedness is
meaningful, we should use #ifdef. If the value is meaningful, we should use
and #ifdef interchangeably for the same macro, seems ugly to me, even if
undefined macros are zero if used.
This also has the benefit that including an LLVM header doesn't prevent
you from compiling with -Wundef -Werror.
Patch by John Garvin!
<rdar://problem/
12189979>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163148
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Sergei Larin [Tue, 4 Sep 2012 14:49:56 +0000 (14:49 +0000)]
Porting Hexagon MI Scheduler to the new API.
Change current Hexagon MI scheduler to use new converging
scheduler. Integrates DFA resource model into it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163137
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Arnold Schwaighofer [Tue, 4 Sep 2012 14:37:49 +0000 (14:37 +0000)]
Patch to implement UMLAL/SMLAL instructions for the ARM architecture
This patch corrects the definition of umlal/smlal instructions and adds support
for matching them to the ARM dag combiner.
Bug 12213
Patch by Yin Ma!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163136
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Elena Demikhovsky [Tue, 4 Sep 2012 12:49:02 +0000 (12:49 +0000)]
This patch optimizes shuffle instruction - generates 2 instructions instead of 4.
Since this specific shuffle is widely used in many workloads we have ~10% performance on them.
shufflevector <8 x float> %A, <8 x float> %B, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
vmovaps (%rdx), %ymm0
vshufps $8, %ymm0, %ymm0, %ymm0
vmovaps (%rcx), %ymm1
vshufps $8, %ymm0, %ymm1, %ymm1
vunpcklps %ymm0, %ymm1, %ymm0
vmovaps (%rcx), %ymm0
vmovsldup (%rdx), %ymm1
vblendps $85, %ymm0, %ymm1, %ymm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163134
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Nadav Rotem [Tue, 4 Sep 2012 10:25:04 +0000 (10:25 +0000)]
LICM may hoist an instruction with undefined behavior above a trap.
Scan the body of the loop and find instructions that may trap.
Use this information when deciding if it is safe to hoist or sink instructions.
Notice that we can optimize the search of instructions that may throw in the case of nested loops.
rdar://
11518836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163132
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Evgeniy Stepanov [Tue, 4 Sep 2012 09:14:45 +0000 (09:14 +0000)]
Fix Android build of gtest and lib/Support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163131
91177308-0d34-0410-b5e6-
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Alexey Samsonov [Tue, 4 Sep 2012 08:12:33 +0000 (08:12 +0000)]
Add support for fetching inlining context (stack of source code locations)
by instruction address from DWARF.
Add --inlining flag to llvm-dwarfdump to demonstrate and test this functionality,
so that "llvm-dwarfdump --inlining --address=0x..." now works much like
"addr2line -i 0x...", provided that the binary has debug info
(Clang's -gline-tables-only *is* enough).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163128
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Bob Wilson [Tue, 4 Sep 2012 03:30:13 +0000 (03:30 +0000)]
Be conservative about allocations that may alias the accessed pointer.
If an allocation has a must-alias relation to the access pointer, we treat it
as a Def. Otherwise, without this check, the code here was just skipping over
the allocation call and ignoring it. I noticed this by inspection and don't
have a specific testcase that it breaks, but it seems like we need to treat
a may-alias allocation as a Clobber.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163127
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Chad Rosier [Mon, 3 Sep 2012 20:37:01 +0000 (20:37 +0000)]
[ms-inline asm] Make comment more verbose and add an assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163125
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Chad Rosier [Mon, 3 Sep 2012 20:31:23 +0000 (20:31 +0000)]
[ms-inline asm] Asm operands can map to one or more MCOperands. Therefore, add
the NumMCOperands argument to the GetMCInstOperandNum() function that is set
to the number of MCOperands this asm operand mapped to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163124
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Chad Rosier [Mon, 3 Sep 2012 19:04:35 +0000 (19:04 +0000)]
[ms-inline asm] Add a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163123
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Chad Rosier [Mon, 3 Sep 2012 18:47:45 +0000 (18:47 +0000)]
[ms-inline asm] Add an interface to the GetMCInstOperandNum() function in the
MCTargetAsmParser class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163122
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Chad Rosier [Mon, 3 Sep 2012 17:39:57 +0000 (17:39 +0000)]
Remove extraneous return.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163119
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Chad Rosier [Mon, 3 Sep 2012 17:33:50 +0000 (17:33 +0000)]
[ms-inline asm] Return the MCOperandNum instead of passing a reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163118
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Roman Divacky [Mon, 3 Sep 2012 16:55:42 +0000 (16:55 +0000)]
Remove always true checks. Noticed by Adhemerval Zanella.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163117
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Chad Rosier [Mon, 3 Sep 2012 16:21:15 +0000 (16:21 +0000)]
Add braces to the case statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163116
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Benjamin Kramer [Mon, 3 Sep 2012 12:27:43 +0000 (12:27 +0000)]
IRBuilderify the SjlLjEHPrepare pass.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163115
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Lang Hames [Mon, 3 Sep 2012 06:31:45 +0000 (06:31 +0000)]
When updating live range endpoints, make sure to preserve the early clobber bit.
Fixs PR13719.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163107
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Bob Wilson [Mon, 3 Sep 2012 05:15:15 +0000 (05:15 +0000)]
Fix more fallout from r158919, similar to PR13547.
This code used to only handle malloc-like calls, which do not read memory.
r158919 changed it to check isNoAliasFn(), which includes strdup-like and
realloc-like calls, but it was not checking for dependencies on the memory
read by those calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163106
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Chad Rosier [Mon, 3 Sep 2012 03:16:09 +0000 (03:16 +0000)]
Removed unused argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163104
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Chris Lattner [Mon, 3 Sep 2012 02:58:21 +0000 (02:58 +0000)]
some peepholes that should match horizontal add/sub operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163103
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Chad Rosier [Mon, 3 Sep 2012 02:06:46 +0000 (02:06 +0000)]
[ms-inline asm] Expose the Kind and Opcode variables from the
MatchInstructionImpl() function.
These values are used by the ConvertToMCInst() function to index into the
ConversionTable. The values are also needed to call the GetMCInstOperandNum()
function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163101
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Chad Rosier [Mon, 3 Sep 2012 01:55:11 +0000 (01:55 +0000)]
Move ErrorLoc decl into the scope where it's actually used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163100
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Nuno Lopes [Sun, 2 Sep 2012 15:16:51 +0000 (15:16 +0000)]
escape special char when handling CXX_FOR_OCAMLOPT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163098
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Nuno Lopes [Sun, 2 Sep 2012 15:07:25 +0000 (15:07 +0000)]
fix test's RUN lines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163097
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Nuno Lopes [Sun, 2 Sep 2012 14:42:56 +0000 (14:42 +0000)]
add support for ocaml 3.12
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163096
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Nuno Lopes [Sun, 2 Sep 2012 14:19:21 +0000 (14:19 +0000)]
replace a couple of single-line comments with /* */ to fix the build of stuff depending on the C headers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163095
91177308-0d34-0410-b5e6-
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Nadav Rotem [Sun, 2 Sep 2012 12:21:50 +0000 (12:21 +0000)]
Fix a typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163094
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Nadav Rotem [Sun, 2 Sep 2012 12:10:19 +0000 (12:10 +0000)]
Not all targets have efficient ISel code generation for select instructions.
For example, the ARM target does not have efficient ISel handling for vector
selects with scalar conditions. This patch adds a TLI hook which allows the
different targets to report which selects are supported well and which selects
should be converted to CF duting codegen prepare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163093
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Benjamin Kramer [Sun, 2 Sep 2012 11:57:22 +0000 (11:57 +0000)]
LoopRotation: Make the brute force DomTree update more brute force.
We update until we hit a fixpoint. This is probably slow but also
slightly simplifies the code. It should also fix the occasional
invalid domtrees observed when building with expensive checking.
I couldn't find a case where this had a measurable slowdown, but
if someone finds a pathological case where it does we may have
to find a cleverer way of updating dominators here.
Thanks to Duncan for the test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163091
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Logan Chien [Sun, 2 Sep 2012 09:29:46 +0000 (09:29 +0000)]
Rename ANDROIDEABI to Android.
Most of the code guarded with ANDROIDEABI are not
ARM-specific, and having no relation with arm-eabi.
Thus, it will be more natural to call this
environment "Android" instead of "ANDROIDEABI".
Note: We are not using ANDROID because several projects
are using "-DANDROID" as the conditional compilation
flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163087
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Nadav Rotem [Sun, 2 Sep 2012 08:20:07 +0000 (08:20 +0000)]
Generate better select code by allowing the target to use scalar select, and not sign-extend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163086
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Pete Cooper [Sat, 1 Sep 2012 22:27:48 +0000 (22:27 +0000)]
Only legalise a VSELECT in to bitwise operations if the vector mask bool is zeros or all ones. A vector bool with just ones isn't suitable for masking with.
No test case unfortunately as i couldn't find a target which fit all
the conditions needed to hit this code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163075
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Benjamin Kramer [Sat, 1 Sep 2012 20:50:18 +0000 (20:50 +0000)]
PR13689: Check for backtrace(3) in the cmake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163074
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Tim Northover [Sat, 1 Sep 2012 18:07:29 +0000 (18:07 +0000)]
Limit domain conversion to cases where it won't break dep chains.
NEON domain conversion was too heavy-handed with its widened
registers, which could have stripped existing instructions of their
dependency, leaving them vulnerable to scheduling errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163070
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Pete Cooper [Sat, 1 Sep 2012 17:37:55 +0000 (17:37 +0000)]
Revert "Take account of boolean vector contents when promoting a build vector from i1 to some other type. rdar://problem/
12210060"
This reverts commit
5dd9e214fb92847e947f9edab170f9b4e52b908f.
Thanks to Duncan for explaining how this should have been done.
Conflicts:
test/CodeGen/X86/vec_select.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163064
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Logan Chien [Sat, 1 Sep 2012 15:06:36 +0000 (15:06 +0000)]
Fix Thumb2 fixup kind in the integrated-as.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163063
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Logan Chien [Sat, 1 Sep 2012 14:58:11 +0000 (14:58 +0000)]
Add ARM ELF support to llvm-objdump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163062
91177308-0d34-0410-b5e6-
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Logan Chien [Sat, 1 Sep 2012 14:43:30 +0000 (14:43 +0000)]
Code cleanup: tools/opt/opt.cpp
Remove unused local variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163061
91177308-0d34-0410-b5e6-
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Logan Chien [Sat, 1 Sep 2012 12:11:41 +0000 (12:11 +0000)]
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163059
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Sat, 1 Sep 2012 12:04:51 +0000 (12:04 +0000)]
LoopRotation: Check some invariants of the dominator updating code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163058
91177308-0d34-0410-b5e6-
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Craig Topper [Sat, 1 Sep 2012 06:33:50 +0000 (06:33 +0000)]
Typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163053
91177308-0d34-0410-b5e6-
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Owen Anderson [Sat, 1 Sep 2012 06:04:27 +0000 (06:04 +0000)]
Teach DAG combine a number of tricks to simplify FMA expressions in fast-math mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163051
91177308-0d34-0410-b5e6-
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Michael Liao [Sat, 1 Sep 2012 04:09:16 +0000 (04:09 +0000)]
Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163049
91177308-0d34-0410-b5e6-
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NAKAMURA Takumi [Sat, 1 Sep 2012 00:26:28 +0000 (00:26 +0000)]
llvm/test/CodeGen/X86/fp-fast.ll: Suppress FMA4 on AMD Bulldozer host, corresponding to r162999.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163041
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Manman Ren [Sat, 1 Sep 2012 00:17:06 +0000 (00:17 +0000)]
Fix Atom bots for r163036.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163040
91177308-0d34-0410-b5e6-
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Manman Ren [Fri, 31 Aug 2012 23:16:57 +0000 (23:16 +0000)]
SelectionDAG: when constructing VZEXT_LOAD from other loads, make sure its
output chain is correctly setup.
As an example, if the original load must happen before later stores, we need
to make sure the constructed VZEXT_LOAD is constrained to be before the stores.
rdar://
11457792
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163036
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Craig Topper [Fri, 31 Aug 2012 23:10:34 +0000 (23:10 +0000)]
Mark FMA4 instructions as commutable and add them to the folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163035
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Eric Christopher [Fri, 31 Aug 2012 22:39:14 +0000 (22:39 +0000)]
Make sure to build libpthread to check for HAVE_PTHREAD_MUTEX_LOCK.
Patch by Brad Smith!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163033
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Chad Rosier [Fri, 31 Aug 2012 22:12:31 +0000 (22:12 +0000)]
Remove an unused argument. The MCInst opcode is set in the ConvertToMCInst()
function nowadays.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163030
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Craig Topper [Fri, 31 Aug 2012 22:12:16 +0000 (22:12 +0000)]
Add selection of RegOp2MemOpTable3 to canFoldMemoryOperand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163029
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Jakob Stoklund Olesen [Fri, 31 Aug 2012 20:50:53 +0000 (20:50 +0000)]
Add MachineInstr::tieOperands, remove setIsTied().
Manage tied operands entirely internally to MachineInstr. This makes it
possible to change the representation of tied operands, as I will do
shortly.
The constraint that tied uses and defs must be in the same order was too
restrictive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163021
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Michael Liao [Fri, 31 Aug 2012 20:12:31 +0000 (20:12 +0000)]
Fix PR12359
- In addition to undefined, if V2 is zero vector, skip 2nd PSHUFB and POR as
well as PSHUFB will zero elements with negative indices.
Patch by Sriram Murali <sriram.murali@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163018
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Jack Carter [Fri, 31 Aug 2012 18:06:48 +0000 (18:06 +0000)]
The instruction DINS may be transformed into DINSU or DEXTM depending
on the size of the extraction and its position in the 64 bit word.
This patch allows support of the dext transformations with mips64 direct
object output.
0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword
32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword
32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163010
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Bill Wendling [Fri, 31 Aug 2012 17:31:28 +0000 (17:31 +0000)]
Move the GCOVFormat enums into their own namespace per the LLVM coding standard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163008
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Chad Rosier [Fri, 31 Aug 2012 17:24:10 +0000 (17:24 +0000)]
Add a comment to explain what's really going on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163005
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Chad Rosier [Fri, 31 Aug 2012 16:41:07 +0000 (16:41 +0000)]
The ConvertToMCInst() function can't fail, so remove the now dead Match_ConversionFail enum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163002
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Craig Topper [Fri, 31 Aug 2012 16:31:13 +0000 (16:31 +0000)]
Mark FMA3 instructions as commutable so that the operands to the multiply part can be commuted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163001
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Craig Topper [Fri, 31 Aug 2012 16:30:05 +0000 (16:30 +0000)]
Use CloneMachineInstr to make a new MI in commuteInstruction to make the code tolerant of instructions with more than two input operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163000
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Craig Topper [Fri, 31 Aug 2012 15:40:30 +0000 (15:40 +0000)]
Add support for converting llvm.fma to fma4 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162999
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Jakob Stoklund Olesen [Fri, 31 Aug 2012 15:34:59 +0000 (15:34 +0000)]
Don't enforce ordered inline asm operands.
I was too optimistic, inline asm can have tied operands that don't
follow the def order.
Fixes PR13742.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162998
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Benjamin Kramer [Fri, 31 Aug 2012 12:43:07 +0000 (12:43 +0000)]
Clean up ProfileDataLoader a bit.
- Overloading operator<< for raw_ostream and pointers is dangerous, it alters
the behavior of code that includes the header.
- Remove unused ID.
- Use LLVM's byte swapping helpers instead of a hand-coded.
- Make ReadProfilingData work directly on a pointer.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162992
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NAKAMURA Takumi [Fri, 31 Aug 2012 10:02:22 +0000 (10:02 +0000)]
llvm/test/CodeGen/X86/vec_select.ll: Fix failure on xmm-less hosts, to add -mattr=+sse2.
FIXME: Should this be tested with both +avx and -avx,+sse2?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162983
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Bill Wendling [Fri, 31 Aug 2012 05:18:31 +0000 (05:18 +0000)]
Cleanups due to feedback. No functionality change. Patch by Alistair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162979
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Michael Liao [Fri, 31 Aug 2012 03:01:35 +0000 (03:01 +0000)]
Clean up AddedComplexity further after adding UseSSEx
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162973
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Jakob Stoklund Olesen [Fri, 31 Aug 2012 02:08:34 +0000 (02:08 +0000)]
Fix a couple of typos in EmitAtomic.
Thumb2 instructions are mostly constrained to rGPR, not tGPR which is
for Thumb1.
rdar://problem/
12203728
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162968
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Jim Grosbach [Fri, 31 Aug 2012 00:30:30 +0000 (00:30 +0000)]
X86: Fix encoding of 'movd %xmm0, %rax'
The assembly string for the VMOVPQIto64rr instruction incorrectly lacked the 'v'
prefix, resulting in mis-assembly of the vanilla movd instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162963
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Chad Rosier [Fri, 31 Aug 2012 00:03:31 +0000 (00:03 +0000)]
With the fix in r162954/162955 every cvt function returns true. Thus, have
the ConvertToMCInst() return void, rather then a bool. Update all the cvt
functions as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162961
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Pete Cooper [Thu, 30 Aug 2012 23:58:52 +0000 (23:58 +0000)]
Take account of boolean vector contents when promoting a build vector from i1 to some other type. rdar://problem/
12210060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162960
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Owen Anderson [Thu, 30 Aug 2012 23:51:20 +0000 (23:51 +0000)]
Try to make this test more generic to unbreak buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162958
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Owen Anderson [Thu, 30 Aug 2012 23:35:16 +0000 (23:35 +0000)]
Teach the DAG combiner to turn chains of FADDs (x+x+x+x+...) into FMULs by constants. This is only enabled in unsafe FP math mode, since it does not preserve rounding effects for all such constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162956
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Chad Rosier [Thu, 30 Aug 2012 23:22:05 +0000 (23:22 +0000)]
Fix for r162954. Return the Error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162955
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Chad Rosier [Thu, 30 Aug 2012 23:20:38 +0000 (23:20 +0000)]
Move a check to the validateInstruction() function where it more properly belongs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162954
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Michael Gottesman [Thu, 30 Aug 2012 23:11:49 +0000 (23:11 +0000)]
[llvm] Updated the test fold-vector-select so that we test the vector selects exhaustively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162953
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Chad Rosier [Thu, 30 Aug 2012 23:00:00 +0000 (23:00 +0000)]
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162952
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Chad Rosier [Thu, 30 Aug 2012 21:47:00 +0000 (21:47 +0000)]
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162946
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Chad Rosier [Thu, 30 Aug 2012 21:46:00 +0000 (21:46 +0000)]
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162945
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Chad Rosier [Thu, 30 Aug 2012 21:43:05 +0000 (21:43 +0000)]
Hoist a check to eliminate obvious mismatches as early as possible. Also, fix
an 80-column violation in the generated code. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162944
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Nadav Rotem [Thu, 30 Aug 2012 19:17:29 +0000 (19:17 +0000)]
Currently targets that do not support selects with scalar conditions and vector operands - scalarize the code. ARM is such a target
because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR
to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2).
rdar://
12201387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162926
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Chad Rosier [Thu, 30 Aug 2012 17:59:25 +0000 (17:59 +0000)]
[ms-inline asm] Add a new function, GetMCInstOperandNum, to the
AsmMatcherEmitter. This function maps inline assembly operands to MCInst
operands.
For example, '__asm mov j, eax' is represented by the follow MCInst:
<MCInst 1460 <MCOperand Reg:0> <MCOperand Imm:1> <MCOperand Reg:0>
<MCOperand Expr:(j)> <MCOperand Reg:0> <MCOperand Reg:43>>
The first 5 MCInst operands are a result of j matching as a memory operand
consisting of a BaseReg (Reg:0), MemScale (Imm:1), MemIndexReg(Reg:0),
Expr (Expr:(j), and a MemSegReg (Reg:0). The 6th MCInst operand represents
the eax register (Reg:43).
This translation is necessary to determine the Input and Output Exprs. If a
single asm operand maps to multiple MCInst operands, the index of the first
MCInst operand is returned. Ideally, it would return the operand we really
care out (i.e., the Expr:(j) in this case), but I haven't found an easy way
of doing this yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162920
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Michael Liao [Thu, 30 Aug 2012 16:54:46 +0000 (16:54 +0000)]
Introduce 'UseSSEx' to force SSE legacy encoding
- Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is
enabled.
As the penalty of inter-mixing SSE and AVX instructions, we need
prevent SSE legacy insn from being generated except explicitly
specified through some intrinsics. For patterns supported by both
SSE and AVX, so far, we force AVX insn will be tried first relying on
AddedComplexity or position in td file. It's error-prone and
introduces bugs accidentally.
'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited
by AVX, we need this predicate to force VEX encoding or SSE legacy
encoding only.
For insns not inherited by AVX, we still use the previous predicates,
i.e. 'HasSSEx'. So far, these insns fall into the following
categories:
* SSE insns with MMX operands
* SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH,
CRC, and etc.)
* SSE4A insns.
* MMX insns.
* x87 insns added by SSE.
2 test cases are modified:
- test/CodeGen/X86/fast-isel-x86-64.ll
AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be
selected by fast-isel due to complicated pattern and fast-isel
fallback to materialize it from constant pool.
- test/CodeGen/X86/widen_load-1.ll
AVX code generation is different from SSE one after fixing SSE/AVX
inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of
'vmovaps'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162919
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NAKAMURA Takumi [Thu, 30 Aug 2012 16:22:32 +0000 (16:22 +0000)]
ADTTests: [CMake] Exclude DenseMapTest.cpp and SmallVectorTest.cpp on MSVC9 due to its bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162918
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NAKAMURA Takumi [Thu, 30 Aug 2012 16:22:26 +0000 (16:22 +0000)]
Apply "/Og-" also to MSC15(aka VS9) on VMCore/Function.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162917
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NAKAMURA Takumi [Thu, 30 Aug 2012 15:52:29 +0000 (15:52 +0000)]
PPCISelLowering.cpp: Fix r162725.
[Tobias von Koch] What's happening here is that the CR6SET/CR6UNSET is breaking the chain of register copies glued to the function call (BL_SVR4 node). The scheduler then moves other instructions in between those and the function call, which isn't good!
Right. That's the case where there is no chain of register copies before the call, so InFlag == 0... Attached is a new revision of the patch which should fix this for good.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162916
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NAKAMURA Takumi [Thu, 30 Aug 2012 15:52:23 +0000 (15:52 +0000)]
PPCISelLowering.cpp: Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162915
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Michael Ilseman [Thu, 30 Aug 2012 15:45:16 +0000 (15:45 +0000)]
test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162914
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Benjamin Kramer [Thu, 30 Aug 2012 15:42:45 +0000 (15:42 +0000)]
Fix test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162913
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