Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially.  For example, an instruciton that prints d0[0] instead of s0.
Patch by Jim Grosbach.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133940 91177308-0d34-0410-b5e6-96231b3b80d8

Add exception necessitated by 133938.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133939 91177308-0d34-0410-b5e6-96231b3b80d8

ARM assembly carry set/clear condition code aliases for 'hi/lo'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133938 91177308-0d34-0410-b5e6-96231b3b80d8

ARM assembler support for ldmfd/stmfd mnemonics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133936 91177308-0d34-0410-b5e6-96231b3b80d8

Allow lr in the register options here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133935 91177308-0d34-0410-b5e6-96231b3b80d8

ARM assembler support for vpush/vpop.

Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple
writeback instructions w/ SP as the base pointer.

rdar://9683231

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133932 91177308-0d34-0410-b5e6-96231b3b80d8

Rename unnecessary forward declaration.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133928 91177308-0d34-0410-b5e6-96231b3b80d8

More refactoring. MC doesn't need know about subreg indices.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133927 91177308-0d34-0410-b5e6-96231b3b80d8

ARM Assembly syntax support for arithmetic implied dest operand.

When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.

For example, the following two instructions are equivalent:
  sub r2, r2, #6
  sub r2, #6

rdar://9682597

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133925 91177308-0d34-0410-b5e6-96231b3b80d8

The index stored in the RegDefIter is one after the current index.  When getting the index, decrement it so that it points to the current element.  Fixes an off-by-one bug encountered when trying to make use of MVT::untyped.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133923 91177308-0d34-0410-b5e6-96231b3b80d8

Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8

pre-RA-sched: Cleanup register pressure tracking.

Removed the check that peeks past EXTRA_SUBREG, which I don't think
makes sense any more. Intead treat it as a normal register def. No
significant affect on x86 or ARM benchmarks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133917 91177308-0d34-0410-b5e6-96231b3b80d8

Move all inline-asm-fpstack tests to a single file.

Also fix some of the tests that were actually testing wrong behavior -
An input operand in {st} is only popped by the inline asm when {st} is
also in the clobber list.

The original bug reports all had ~{st} clobbers as they should.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133916 91177308-0d34-0410-b5e6-96231b3b80d8

Track live-out physical registers in MachineDCE.

Patch by Sanjoy Das!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133910 91177308-0d34-0410-b5e6-96231b3b80d8

Teach one piece of scalarrepl to handle lifetime markers. When transforming an
alloca that only holds a copy of a global and we're going to replace the users
of the alloca with that global, just nuke the lifetime intrinsics. Part of
PR10121.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133905 91177308-0d34-0410-b5e6-96231b3b80d8

Move onlyUsedByLifetimeMarkers to ValueTracking so that it can be used by other
passes as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133904 91177308-0d34-0410-b5e6-96231b3b80d8

Grow the X86FloatingPoint register map to hold 16 registers.

This allows for more live scratch registers which is needed to handle
live ST registers before return and inline asm instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133903 91177308-0d34-0410-b5e6-96231b3b80d8

Distinguish early clobber output operands from clobbered registers.

Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we
now use two different asm operand kinds.

The new Kind_Clobber is treated identically to the old
Kind_RegDefEarlyClobber for now, but x87 floating point stack inline
assembly does care about the difference.

This will pop a register off the stack:

  asm("fstp %st" : : "t"(x) : "st");

While this will pop the input and push an output:

  asm("fst %st" : "=&t"(r) : "t"(x));

We need to know if ST0 was a clobber or an output operand, and we can't
depend on <dead> flags for that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133902 91177308-0d34-0410-b5e6-96231b3b80d8

Decode and pretty print inline asm operand descriptors.

The INLINEASM MachineInstrs have an immediate operand describing each
original inline asm operand. Decode the bits in MachineInstr::print() so
it is easier to read:

  INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133901 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unused methods.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133900 91177308-0d34-0410-b5e6-96231b3b80d8

There is only one register coalescer. Merge it into the base class and
remove the analysis group.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133899 91177308-0d34-0410-b5e6-96231b3b80d8

Merge SimpleRegisterCoalescing.cpp into RegisterCoalescer.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133897 91177308-0d34-0410-b5e6-96231b3b80d8

merge SimpleRegisterCoalescing.h into RegisterCoalescer.h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133896 91177308-0d34-0410-b5e6-96231b3b80d8

Move RegisterCoalescer.h to lib/CodeGen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133895 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unnecessary wrapper.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133886 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: corrected tests that were failing

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133875 91177308-0d34-0410-b5e6-96231b3b80d8

Replace dyn_cast<> with cast<> since the cast is already guarded by the necessary check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133874 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Reverting implementation of i8.

The .b8 operations in PTX are far more limiting than I first thought. The mov operation isn't even supported, so there's no way of converting a .pred value into a .b8 without going via .b16, which is
not sensible. An improved implementation needs to use the fact that loads and stores automatically extend and truncate to implement support for EXTLOAD and TRUNCSTORE in order to correctly support
boolean values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133873 91177308-0d34-0410-b5e6-96231b3b80d8

Object: Add proper error handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133872 91177308-0d34-0410-b5e6-96231b3b80d8

Modify llvm-nm to use new Binary creation method.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133871 91177308-0d34-0410-b5e6-96231b3b80d8

Make Binary the parent of ObjectFile and update children to new interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133870 91177308-0d34-0410-b5e6-96231b3b80d8

Add Binary class. This is a cleaner parent than ObjectFile.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133869 91177308-0d34-0410-b5e6-96231b3b80d8

Add Object/Error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133868 91177308-0d34-0410-b5e6-96231b3b80d8

Enhance the sanity check for block sizes; check that the resulting pointer is
pointing to the range [first character, last character] instead of just not
after the last character. Patch by Yan Ivnitskiy!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133867 91177308-0d34-0410-b5e6-96231b3b80d8

Test case for r133858 (tail call optimize in the presence of byval).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133863 91177308-0d34-0410-b5e6-96231b3b80d8

Update CMake library dependencies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133859 91177308-0d34-0410-b5e6-96231b3b80d8

Enable tail call optimization in the presence of a byval (x86-32 and x86-64).
<rdar://problem/9483883>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133858 91177308-0d34-0410-b5e6-96231b3b80d8

Move ARM-specific test to ARM directory.

Hopefully make the x86-target-only Windows bots happy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133856 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak CMake build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133853 91177308-0d34-0410-b5e6-96231b3b80d8

Remove dead typedefs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133851 91177308-0d34-0410-b5e6-96231b3b80d8

Add include guard.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133847 91177308-0d34-0410-b5e6-96231b3b80d8

Rename TargetDesc to MCTargetDesc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133846 91177308-0d34-0410-b5e6-96231b3b80d8

Rename TargetRegisterDesc to MCRegisterDesc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133845 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor MachO relocation generaration into the Target directories.

Move the target-specific RecordRelocation logic out of the generic MC
MachObjectWriter and into the target-specific object writers. This allows
nuking quite a bit of target knowledge from the supposedly target-independent
bits in lib/MC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133844 91177308-0d34-0410-b5e6-96231b3b80d8

The scheduler needs to be aware on the existence of untyped nodes when it performs type propagation for EXTRACT_SUBREG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133838 91177308-0d34-0410-b5e6-96231b3b80d8

Revert "Shorten some ARM builtin names by removing unnecessary "neon" prefix."
Sorry, this was a bad idea.  Within clang these builtins are in a separate
"ARM" namespace, but the actual builtin names should clearly distinguish that
they are target specific.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133832 91177308-0d34-0410-b5e6-96231b3b80d8

Fix cmake build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133830 91177308-0d34-0410-b5e6-96231b3b80d8

Fix struct member's scope. Patch by Xi Wang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133828 91177308-0d34-0410-b5e6-96231b3b80d8

Shorten some ARM builtin names by removing unnecessary "neon" prefix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133825 91177308-0d34-0410-b5e6-96231b3b80d8

Hoist simple check above more complex checking to avoid unnecessary
overheads.  No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133824 91177308-0d34-0410-b5e6-96231b3b80d8

Testcase for r133818

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133823 91177308-0d34-0410-b5e6-96231b3b80d8

Revert unintentional check-in.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133822 91177308-0d34-0410-b5e6-96231b3b80d8

Handle debug info for  i128 constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133821 91177308-0d34-0410-b5e6-96231b3b80d8

- Add MCRegisterInfo registration machinery. Also added x86 registration routines.
- Rename TargetRegisterDesc to MCRegisterDesc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133820 91177308-0d34-0410-b5e6-96231b3b80d8

ARM movw/movt fixups need to mask the high bits.

The fixup value comes in as the whole 32-bit value, so for the lo16 fixup,
the upper bits need to be masked off. Previously we assumed the masking had
already been done and asserted.

rdar://9635991

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133818 91177308-0d34-0410-b5e6-96231b3b80d8

tidy up whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133815 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Add support for i8 type and introduce associated .b8 registers

The i8 type is required for boolean values, but can only use ld, st and mov instructions. The i1 type continues to be used for predicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133814 91177308-0d34-0410-b5e6-96231b3b80d8

The Neon VCVT (between floating-point and fixed-point, Advanced SIMD)
instructions can be used to match combinations of multiply/divide and VCVT
(between floating-point and integer, Advanced SIMD).  Basically the VCVT
immediate operand that specifies the number of fraction bits corresponds to a
floating-point multiply or divide by the corresponding power of 2.

For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a
combination of VMUL and VCVT (floating-point to integer) as follows:

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
  vmul.f32        d16, d17, d16
  vcvt.s32.f32    d16, d16
becomes:
  vcvt.s32.f32    d16, d16, #3

Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a
combinations of VCVT (integer to floating-point) and VDIV as follows:

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
  vcvt.f32.s32    d16, d16
  vdiv.f32        d16, d17, d16
becomes:
  vcvt.f32.s32    d16, d16, #3

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133813 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Add preliminary support for outputting debug information in the form of
     .file and .loc directives.

Ideally, we would utilize the existing support in AsmPrinter for this, but
I cannot find a way to get .file and .loc directives to print without the
rest of the associated DWARF sections, which ptxas cannot handle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133812 91177308-0d34-0410-b5e6-96231b3b80d8

Change the chain input of nodes that load the address of a function. This change
 enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133811 91177308-0d34-0410-b5e6-96231b3b80d8

Fixup info for Thumb2 unconditional branch.

rdar://9667872

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133808 91177308-0d34-0410-b5e6-96231b3b80d8

Prevent generation of redundant addiu instructions that compute address of
static variables or functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133803 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Re-work target sm/compute selection and add some basic GPU
     targets: g80, gt200, gf100(fermi)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133799 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133798 91177308-0d34-0410-b5e6-96231b3b80d8

Now that bb with phis are not considered simple, duplicate them even if
we cannot duplicate to every predecessor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133797 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify now that blocks with phis are not considered simple.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133793 91177308-0d34-0410-b5e6-96231b3b80d8

Fix CellSPU CMakeList.txt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133792 91177308-0d34-0410-b5e6-96231b3b80d8

Make the generated InitXXXMCRegisterInfo function "static inline", so it doesn't get emitted into multiple object files.

This caused linker errors when linking both libLLVMX86Desc and libLLVMX86CodeGen
into a single binary (for example when building a monolithic libLLVM shared library).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133791 91177308-0d34-0410-b5e6-96231b3b80d8

Fix CellSPU CMakeLists.txt

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133787 91177308-0d34-0410-b5e6-96231b3b80d8

Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8

Calculate backedge probability correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133776 91177308-0d34-0410-b5e6-96231b3b80d8

Tidy up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133770 91177308-0d34-0410-b5e6-96231b3b80d8

Missing files for the BlockFrequency analysis added.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133767 91177308-0d34-0410-b5e6-96231b3b80d8

Introduce BlockFrequency analysis for BasicBlocks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133766 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for movntil/movntiq mnemonics.  Reported on llvmdev.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133759 91177308-0d34-0410-b5e6-96231b3b80d8

PR10180: Fix a instcombine crash with FP vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133756 91177308-0d34-0410-b5e6-96231b3b80d8

Fix build for (some versions of?) MinGW.  Patch by Ruben Van Boxem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133741 91177308-0d34-0410-b5e6-96231b3b80d8

Rename TargetOptions::StackAlignment to StackAlignmentOverride.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133739 91177308-0d34-0410-b5e6-96231b3b80d8

Remove TargetOptions.h dependency from ARMSubtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133738 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Always use registers for return values, but use .param space for device
     parameters if SM >= 2.0

- Update test cases to be more robust against register allocation changes
- Bump up the number of registers to 128 per type
- Include Python script to re-generate register file with any number of
  registers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Fixup test cases for device param changes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133735 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Whitespace fixes and remove commented out code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133734 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Prevent DCE from eliminating st.param calls, and unify the handling of
     st.param and ld.param

FIXME: Test cases still need to be updated

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133733 91177308-0d34-0410-b5e6-96231b3b80d8

PTX: Use .param space for parameters in device functions for SM >= 2.0

FIXME: DCE is eliminating the final st.param.x calls, figure out why

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133732 91177308-0d34-0410-b5e6-96231b3b80d8

cmake+lit: final cleanup related to the recent churn

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133729 91177308-0d34-0410-b5e6-96231b3b80d8

Remove TargetOptions.h dependency from X86Subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133726 91177308-0d34-0410-b5e6-96231b3b80d8

cmake+lit: handle ENABLE_ASSERTIONS feature properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133725 91177308-0d34-0410-b5e6-96231b3b80d8

Revert "revert 133714"

This reverts commit e8e00f5efb4a22238f2407bf813de4606f30c5aa.

The cmake build on OS X is still broken.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133718 91177308-0d34-0410-b5e6-96231b3b80d8

Add missing file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133717 91177308-0d34-0410-b5e6-96231b3b80d8

revert 133714

It broke the build worse.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133716 91177308-0d34-0410-b5e6-96231b3b80d8

133713 broke the build, revert it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133714 91177308-0d34-0410-b5e6-96231b3b80d8

Support: make floating-exception header private

It has only one user. This eliminates the last include of
config.h from the public headers -- ideally, config.h
shouldn't even be installed by `make install` anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133713 91177308-0d34-0410-b5e6-96231b3b80d8

Don't include config.h in public headers

Replace it with llvm-config.h, which defines a subset of
config.h's macros "so that they can be in exported headers
and won't override package specific directives", e.g.,
PACKAGE_NAME.

Endian.h wasn't using any macros at all though, so just delete
the include there instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133712 91177308-0d34-0410-b5e6-96231b3b80d8

remove CMake mode_t define

It's now replaced with a simple ifdef _MSC_VER in the one
place it's needed (clang's FileManager.h header).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133711 91177308-0d34-0410-b5e6-96231b3b80d8

CppBackend: fixup for api change

This broke after r133364.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133709 91177308-0d34-0410-b5e6-96231b3b80d8

Reinstate r133513 (reverted in r133700) with an additional fix for a
-Wshorten-64-to-32 warning in Instructions.h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133708 91177308-0d34-0410-b5e6-96231b3b80d8

Use a reference. Don't make a useless copy of the vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133707 91177308-0d34-0410-b5e6-96231b3b80d8

Formatting changes. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133706 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r133513:

"Reinstate r133435 and r133449 (reverted in r133499) now that the clang
self-hosted build failure has been fixed (r133512)."

Due to some additional warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133700 91177308-0d34-0410-b5e6-96231b3b80d8

Use the presence of the __compact_unwind section to indicate that a target
supports compact unwind info instead of having a separate flag indicating this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133685 91177308-0d34-0410-b5e6-96231b3b80d8