Vincent Lejeune [Tue, 1 Oct 2013 19:32:49 +0000 (19:32 +0000)]
R600: Put PRED_X instruction in its own clause
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191789
91177308-0d34-0410-b5e6-
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Vincent Lejeune [Tue, 1 Oct 2013 19:32:38 +0000 (19:32 +0000)]
R600: Enable -verify-machineinstrs in some tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191788
91177308-0d34-0410-b5e6-
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Quentin Colombet [Tue, 1 Oct 2013 19:21:24 +0000 (19:21 +0000)]
[MC] When MCInstPrint::printAnnotation uses a comment stream, it has to ensure
that each comment ends with a newline to match the definition in the header
file.
This is part of <rdar://problem/
14687488>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191787
91177308-0d34-0410-b5e6-
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Matt Arsenault [Tue, 1 Oct 2013 18:05:30 +0000 (18:05 +0000)]
Don't merge tiny functions.
It's silly to merge functions like these:
define void @foo(i32 %x) {
ret void
}
define void @bar(i32 %x) {
ret void
}
to get
define void @bar(i32) {
tail call void @foo(i32 %0)
ret void
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191786
91177308-0d34-0410-b5e6-
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Rafael Espindola [Tue, 1 Oct 2013 17:40:47 +0000 (17:40 +0000)]
Reverts commit r190808 and r190556.
The use of these features in clang has been reverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191785
91177308-0d34-0410-b5e6-
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Preston Gurd [Tue, 1 Oct 2013 17:02:48 +0000 (17:02 +0000)]
Add test case for PR16785.
Thanks for Dimitry Andric, Rafael Espindola, and Benjamin Kramer
for providing and progressively reducing the test case!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191782
91177308-0d34-0410-b5e6-
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Alexey Samsonov [Tue, 1 Oct 2013 16:52:46 +0000 (16:52 +0000)]
[DebugInfo] Simplify and speedup .debug_aranges parsing
Parsing .debug_aranges section now takes O(nlogn) operations instead
of O(n^2), where "n" is the number of address ranges. With this change,
the time required to symbolize an address from a random large
Clang-generated binary drops from 165 seconds to 1.5 seconds.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191781
91177308-0d34-0410-b5e6-
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Andrew Kaylor [Tue, 1 Oct 2013 16:42:50 +0000 (16:42 +0000)]
Fixing MCJIT multiple module linking for OSX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191780
91177308-0d34-0410-b5e6-
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Alexey Samsonov [Tue, 1 Oct 2013 16:25:14 +0000 (16:25 +0000)]
[DebugInfo] Further simplify DWARFDebugAranges. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191779
91177308-0d34-0410-b5e6-
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Alexey Samsonov [Tue, 1 Oct 2013 15:48:10 +0000 (15:48 +0000)]
[DebugInfo] Remove unused functions from DWARFDebugAranges and fix code style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191778
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 15:00:44 +0000 (15:00 +0000)]
[SystemZ] Add comparisons of high words and memory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191777
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 14:56:23 +0000 (14:56 +0000)]
[SystemZ] Add comparisons of large immediates using high words
There are no corresponding patterns for small immediates because they would
prevent the use of fused compare-and-branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191775
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 14:53:46 +0000 (14:53 +0000)]
[SystemZ] Add immediate addition involving high words
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191774
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 14:41:52 +0000 (14:41 +0000)]
[SystemZ] Extend test-under-mask support to high GR32s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191773
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 14:36:20 +0000 (14:36 +0000)]
[SystemZ] Extend 32-bit RISBG optimizations to high words
This involves using RISB[LH]G, whereas the equivalent z10 optimization
uses RISBG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191770
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 14:33:55 +0000 (14:33 +0000)]
[SystemZ] Extend pseudo conditional 8- and 16-bit stores to high words
As the comment says, we always want to use STOC for 32-bit stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191767
91177308-0d34-0410-b5e6-
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Tim Northover [Tue, 1 Oct 2013 14:33:28 +0000 (14:33 +0000)]
ARM: support interrupt attribute
This function-attribute modifies the callee-saved register list and function
epilogue (specifically the return instruction) so that a routine is suitable
for use as an interrupt-handler of the specified type without disrupting
user-mode applications.
rdar://problem/
14207019
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191766
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 14:31:50 +0000 (14:31 +0000)]
[SystemZ] Add test missing from r191764.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191765
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 14:31:11 +0000 (14:31 +0000)]
[SystemZ] Optimize 32-bit FPR<->GPR moves for z196 and above
Floats are stored in the high 32 bits of an FPR, and the only GPR<->FPR
transfers are full-register transfers. This patch optimizes GPR<->FPR
float transfers when the high word of a GPR is directly accessible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191764
91177308-0d34-0410-b5e6-
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Tareq A. Siraj [Tue, 1 Oct 2013 14:28:18 +0000 (14:28 +0000)]
Add non-blocking Wait() for launched processes
- New ProcessInfo class to encapsulate information about child processes.
- Generalized the Wait() to support non-blocking wait on child processes.
- ExecuteNoWait() now returns a ProcessInfo object with information about
the launched child. Users will be able to use this object to
perform non-blocking wait.
- ExecuteNoWait() now accepts an ExecutionFailed param that tells if execution
failed or not.
These changes will allow users to implement basic process parallel
tools.
Differential Revision: http://llvm-reviews.chandlerc.com/D1728
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191763
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 14:20:41 +0000 (14:20 +0000)]
[SystemZ] Allow integer AND involving high words
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191762
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 14:08:44 +0000 (14:08 +0000)]
[SystemZ] Allow integer XOR involving high words
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191759
91177308-0d34-0410-b5e6-
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Rafael Espindola [Tue, 1 Oct 2013 13:32:03 +0000 (13:32 +0000)]
Remove several unused variables.
Patch by Alp Toker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191757
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 13:22:41 +0000 (13:22 +0000)]
[SystemZ] Allow integer OR involving high words
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191755
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 13:18:56 +0000 (13:18 +0000)]
[SystemZ] Allow integer insertions with a high-word destination
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191753
91177308-0d34-0410-b5e6-
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Sylvestre Ledru [Tue, 1 Oct 2013 13:17:09 +0000 (13:17 +0000)]
Fix a typo in the documentation. Thanks to Diana Vasile for the patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191752
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 13:10:16 +0000 (13:10 +0000)]
[SystemZ] Allow selects with a high-word destination
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191751
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 13:02:28 +0000 (13:02 +0000)]
[SystemZ] Add patterns to load a constant into a high word (IIHF)
Similar to low words, we can use the shorter LLIHL and LLIHH if it turns
out that the other half of the GR64 isn't live.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191750
91177308-0d34-0410-b5e6-
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Joey Gouly [Tue, 1 Oct 2013 13:01:10 +0000 (13:01 +0000)]
[ARM] Remove an unused function from the disassembler.
Pointed out by Joerg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191749
91177308-0d34-0410-b5e6-
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Matheus Almeida [Tue, 1 Oct 2013 12:53:00 +0000 (12:53 +0000)]
Test commit. Updated comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191748
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 12:49:07 +0000 (12:49 +0000)]
[SystemZ] Add register zero extensions involving at least one high word
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191746
91177308-0d34-0410-b5e6-
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Joerg Sonnenberger [Tue, 1 Oct 2013 12:42:48 +0000 (12:42 +0000)]
Remove empty directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191745
91177308-0d34-0410-b5e6-
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Joey Gouly [Tue, 1 Oct 2013 12:39:11 +0000 (12:39 +0000)]
[ARM] Introduce the 'sevl' instruction in ARMv8.
This also removes the restriction on the immediate field of the 'hint'
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191744
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 12:22:49 +0000 (12:22 +0000)]
[SystemZ] Add truncating high-word stores (STCH and STHH)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191743
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 12:19:08 +0000 (12:19 +0000)]
[SystemZ] Add zero-extending high-word loads (LLCH and LLHH)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191742
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Tue, 1 Oct 2013 12:17:11 +0000 (12:17 +0000)]
SCEVExpander: Fix a regression I introduced by to eagerly adding RAII objects.
PR17425.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191741
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 12:11:47 +0000 (12:11 +0000)]
[SystemZ] Add sign-extending high-word loads (LBH and LHH)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191740
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 11:26:28 +0000 (11:26 +0000)]
[SystemZ] Use upper words of GR64s for codegen
This just adds the basics necessary for allocating the upper words to
virtual registers (move, load and store). The move support is parameterised
in a way that makes it easy to handle zero extensions, but the associated
zero-extend patterns are added by a later patch.
The easiest way of testing this seemed to be add a new "h" register
constraint for high words. I don't expect the constraint to be useful
in real inline asms, but it should work, so I didn't try to hide it
behind an option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191739
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 10:31:04 +0000 (10:31 +0000)]
[SystemZ] Reapply: Add definitions of LFH and STFH
Originally committed as r191661, but reverted because it changed the matching
order of comparisons on some hosts. That should have been fixed by r191735.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191738
91177308-0d34-0410-b5e6-
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Daniel Sanders [Tue, 1 Oct 2013 10:22:35 +0000 (10:22 +0000)]
[mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191737
91177308-0d34-0410-b5e6-
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Richard Sandiford [Tue, 1 Oct 2013 09:49:01 +0000 (09:49 +0000)]
Fix pattern sort in DAGISelEmitter.cpp
The old code skipped one of the sorting criteria if either pattern had
no types. This could lead to cycles of the form X < Y, Y < Z, Z < X.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191735
91177308-0d34-0410-b5e6-
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Vladimir Medic [Tue, 1 Oct 2013 09:48:56 +0000 (09:48 +0000)]
This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191734
91177308-0d34-0410-b5e6-
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Elena Demikhovsky [Tue, 1 Oct 2013 08:38:02 +0000 (08:38 +0000)]
AVX-512: Added X86vzmovl patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191733
91177308-0d34-0410-b5e6-
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Craig Topper [Tue, 1 Oct 2013 07:10:28 +0000 (07:10 +0000)]
Remove 0 as a valid encoding for the m-mmmm field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191732
91177308-0d34-0410-b5e6-
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Craig Topper [Tue, 1 Oct 2013 06:56:57 +0000 (06:56 +0000)]
Remove unneeded fields from disassembler internal instruction format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191731
91177308-0d34-0410-b5e6-
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Craig Topper [Tue, 1 Oct 2013 03:48:26 +0000 (03:48 +0000)]
BEXTR should be defined to take same type for bother operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191728
91177308-0d34-0410-b5e6-
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Tom Stellard [Tue, 1 Oct 2013 02:09:00 +0000 (02:09 +0000)]
SelectionDAG: Clarify comments from r191600
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191724
91177308-0d34-0410-b5e6-
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Andrew Kaylor [Tue, 1 Oct 2013 01:48:36 +0000 (01:48 +0000)]
Tests for MCJIT multiple module support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191723
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Andrew Kaylor [Tue, 1 Oct 2013 01:47:35 +0000 (01:47 +0000)]
Adding multiple module support for MCJIT.
Tests to follow.
PIC with small code model and EH frame handling will not work with multiple modules. There are also some rough edges to be smoothed out for remote target support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191722
91177308-0d34-0410-b5e6-
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Eric Christopher [Tue, 1 Oct 2013 00:43:36 +0000 (00:43 +0000)]
Add the DW_AT_GNU_ranges_base attribute if we've emitted any ranges
into the debug_ranges section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191721
91177308-0d34-0410-b5e6-
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Eric Christopher [Tue, 1 Oct 2013 00:43:31 +0000 (00:43 +0000)]
Update comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191720
91177308-0d34-0410-b5e6-
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Matt Arsenault [Tue, 1 Oct 2013 00:01:14 +0000 (00:01 +0000)]
Fix code duplication
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191716
91177308-0d34-0410-b5e6-
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Preston Gurd [Mon, 30 Sep 2013 23:51:22 +0000 (23:51 +0000)]
Forgot to add a break statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191715
91177308-0d34-0410-b5e6-
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Matt Arsenault [Mon, 30 Sep 2013 23:31:55 +0000 (23:31 +0000)]
Use CHECK-LABEL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191713
91177308-0d34-0410-b5e6-
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Matt Arsenault [Mon, 30 Sep 2013 23:31:50 +0000 (23:31 +0000)]
Reuse variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191712
91177308-0d34-0410-b5e6-
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Preston Gurd [Mon, 30 Sep 2013 23:18:42 +0000 (23:18 +0000)]
The X86FixupLEAs pass for Intel Atom must not call convertToThreeAddress
on ADD16rr opcodes, if src1 != src, since that would cause
convertToThreeAddress to try to create a virtual register. This is not
permitted after register allocation, which is when the X86FixupLEAs pass
runs.
This patch fixes PR16785.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191711
91177308-0d34-0410-b5e6-
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Eric Christopher [Mon, 30 Sep 2013 23:14:16 +0000 (23:14 +0000)]
The DW_AT_GNU_pubnames/pubtypes attributes are actually form
SEC_OFFSET from the beginning of the section so go ahead and emit
a label at the beginning of each one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191710
91177308-0d34-0410-b5e6-
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Eric Christopher [Mon, 30 Sep 2013 21:55:01 +0000 (21:55 +0000)]
Add llvm-readobj to the list of programs to find in the freshly built
toolchain.
Patch by Richard Pennington.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191706
91177308-0d34-0410-b5e6-
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Matt Arsenault [Mon, 30 Sep 2013 21:23:03 +0000 (21:23 +0000)]
Fix getOrInsertGlobal dropping the address space.
Currently it will insert an illegal bitcast.
Arguably, the address space argument should be
added for the creation case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191702
91177308-0d34-0410-b5e6-
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Matt Arsenault [Mon, 30 Sep 2013 21:11:01 +0000 (21:11 +0000)]
Use right address space size in InstCombineCompares
The test's output doesn't change, but this ensures
this is actually hit with a different address space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191701
91177308-0d34-0410-b5e6-
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Matt Arsenault [Mon, 30 Sep 2013 21:06:18 +0000 (21:06 +0000)]
Constant fold ptrtoint + compare with address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191699
91177308-0d34-0410-b5e6-
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Manman Ren [Mon, 30 Sep 2013 19:42:10 +0000 (19:42 +0000)]
Debug Info: constify and rename from generateRef to getRef.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191696
91177308-0d34-0410-b5e6-
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Anders Waldenborg [Mon, 30 Sep 2013 19:11:32 +0000 (19:11 +0000)]
llvm-c: use typedef for function pointers
This makes it consistent with other function pointers used in llvm-c
Differential Revision: http://llvm-reviews.chandlerc.com/D1712
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191693
91177308-0d34-0410-b5e6-
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Tilmann Scheller [Mon, 30 Sep 2013 18:50:51 +0000 (18:50 +0000)]
[ARM] Fix Thumb(-2) diagnostic tests.
Changing the diagnostic message for out of range branch targets in 191686 broke the tests.
The diagnostic message for out of range branch targets was changed to be more consistent with the other diagnostics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191691
91177308-0d34-0410-b5e6-
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Manman Ren [Mon, 30 Sep 2013 18:17:55 +0000 (18:17 +0000)]
TBAA: update tbaa format from scalar format to struct-path aware format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191690
91177308-0d34-0410-b5e6-
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Manman Ren [Mon, 30 Sep 2013 18:17:35 +0000 (18:17 +0000)]
TBAA: remove !tbaa from testing cases when they are not needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191689
91177308-0d34-0410-b5e6-
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Jack Carter [Mon, 30 Sep 2013 18:05:18 +0000 (18:05 +0000)]
[mips][msa] Direct Object Emission for I8 instructions.
This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191688
91177308-0d34-0410-b5e6-
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Jack Carter [Mon, 30 Sep 2013 17:58:07 +0000 (17:58 +0000)]
[mips][msa] Direct Object Emission for I5 instructions.
This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191687
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Tilmann Scheller [Mon, 30 Sep 2013 17:57:30 +0000 (17:57 +0000)]
[ARM] Clean up ARMAsmParser::validateInstruction().
Fix some LLVM Coding Standards violations.
No changes in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191686
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Jack Carter [Mon, 30 Sep 2013 17:52:33 +0000 (17:52 +0000)]
[mips][msa] Direct Object Emission for 2R instructions.
This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}.
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191685
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Jack Carter [Mon, 30 Sep 2013 17:43:04 +0000 (17:43 +0000)]
[PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR
and not an MSA register
Patch by Matheus Almeida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191684
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Tilmann Scheller [Mon, 30 Sep 2013 17:31:26 +0000 (17:31 +0000)]
[ARM] Use FileCheck instead of grep for ARM LDRD negative tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191683
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Rafael Espindola [Mon, 30 Sep 2013 16:39:19 +0000 (16:39 +0000)]
Move command line options to the users of libLTO. Fixes --enable-shared build.
Patch by Richard Sandiford.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191680
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Rafael Espindola [Mon, 30 Sep 2013 16:32:51 +0000 (16:32 +0000)]
Revert "Enable building LTO on WIN32."
This reverts commit r191670.
It was causing build failures on the msvc bots:
http://bb.pgr.jp/builders/ninja-clang-i686-msc17-R/builds/5166/steps/compile/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191679
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Tilmann Scheller [Mon, 30 Sep 2013 16:11:48 +0000 (16:11 +0000)]
[ARM] Assembler: ARM LDRD with writeback requires the base register to be different from the destination registers.
See ARM ARM A8.8.72.
Violating this constraint results in unpredictable behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191678
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Arnold Schwaighofer [Mon, 30 Sep 2013 15:56:34 +0000 (15:56 +0000)]
Swift model: Fix uop description on some writes
Those writes really need two/three uops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191677
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Benjamin Kramer [Mon, 30 Sep 2013 15:52:50 +0000 (15:52 +0000)]
BoundsChecking: Fix refacto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191676
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Benjamin Kramer [Mon, 30 Sep 2013 15:40:17 +0000 (15:40 +0000)]
Convert manual insert point restores to the new RAII object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191675
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Benjamin Kramer [Mon, 30 Sep 2013 15:39:59 +0000 (15:39 +0000)]
InstCombine: Replace manual fast math flag copying with the new IRBuilder RAII helper.
Defines away the issue where cast<Instruction> would fail because constant
folding happened. Also slightly cleaner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191674
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Benjamin Kramer [Mon, 30 Sep 2013 15:39:48 +0000 (15:39 +0000)]
IRBuilder: Add RAII objects to reset insertion points or fast math flags.
Inspired by the object from the SLPVectorizer. This found a minor bug in the
debug loc restoration in the vectorizer where the location of a following
instruction was attached instead of the location from the original instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191673
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Benjamin Kramer [Mon, 30 Sep 2013 15:39:27 +0000 (15:39 +0000)]
IRBuilder: Move fast math flags to IRBuilderBase.
They don't depend on the templated stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191672
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Arnold Schwaighofer [Mon, 30 Sep 2013 15:28:56 +0000 (15:28 +0000)]
IfConverter: Use TargetSchedule for instruction latencies
For targets that have instruction itineraries this means no change. Targets
that move over to the new schedule model will use be able the new schedule
module for instruction latencies in the if-converter (the logic is such that if
there is no itineary we will use the new sched model for the latencies).
Before, we queried "TTI->getInstructionLatency()" for the instruction latency
and the extra prediction cost. Now, we query the TargetSchedule abstraction for
the instruction latency and TargetInstrInfo for the extra predictation cost. The
TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if
an itinerary exists, otherwise it will use the new schedule model.
ATTENTION: Out of tree targets!
(I will also send out an email later to LLVMDev)
This means, if your target implements
unsigned getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI,
unsigned *PredCost);
and returns a value for "PredCost", you now also need to implement
unsigned getPredictationCost(const MachineInstr *MI);
(if your target uses the IfConversion.cpp pass)
radar://
15077010
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191671
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Rafael Espindola [Mon, 30 Sep 2013 15:28:14 +0000 (15:28 +0000)]
Enable building LTO on WIN32.
Enable building the LTO library (.lib and.dll) and llvm-lto.exe on Windows with
MSVC and Mingw as well as re-enabling the associated test.
Patch by Greg Bedwell!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191670
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Joey Gouly [Mon, 30 Sep 2013 14:18:35 +0000 (14:18 +0000)]
Fix a bug in InstCombine where it attempted to cast a Value* to an Instruction*
when it was actually a Constant*.
There are quite a few other casts to Instruction that might have the same problem,
but this is the only one I have a test case for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191668
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Tilmann Scheller [Mon, 30 Sep 2013 13:04:22 +0000 (13:04 +0000)]
[ARM] Assembler: Add more negative tests for ARM LDRD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191664
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Richard Sandiford [Mon, 30 Sep 2013 12:01:35 +0000 (12:01 +0000)]
[SystemZ] Revert r191661: Add definitions of LFH and STFH
For some reason, adding definitions for these load and store
instructions changed whether some of the build bots matched
comparisons as signed or unsigned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191663
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Richard Sandiford [Mon, 30 Sep 2013 10:50:33 +0000 (10:50 +0000)]
[SystemZ] Add definitions of LFH and STFH
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191661
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Richard Sandiford [Mon, 30 Sep 2013 10:45:16 +0000 (10:45 +0000)]
[SystemZ] Add GRH32 for the high word of a GR64
The only thing this does on its own is make the definitions of RISB[HL]G
a bit more precise. Those instructions are only used by the MC layer at
the moment, so no behavioral change is intended. The class is needed by
later patches though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191660
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Richard Sandiford [Mon, 30 Sep 2013 10:28:35 +0000 (10:28 +0000)]
[SystemZ] Rename subregs and add subreg_h32
Use subreg_hNN and subreg_lNN for the high and low NN bits of a register.
List the low registers first, so that subreg_l32 also means the low 32
bits of a 128-bit register.
Floats are stored in the upper 32 bits of a 64-bit register, so they
should use subreg_h32 rather than subreg_l32.
No behavioral change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191659
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Daniel Sanders [Mon, 30 Sep 2013 09:35:37 +0000 (09:35 +0000)]
[mips] Fix a broken link to mips.com in the documentation.
It now points to the equivalent page on imgtec.com
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191658
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Richard Sandiford [Mon, 30 Sep 2013 08:54:17 +0000 (08:54 +0000)]
[SystemZ] Add change missing from previous commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191656
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Richard Sandiford [Mon, 30 Sep 2013 08:48:38 +0000 (08:48 +0000)]
[SystemZ] Rename 32-bit GPR registers
I'm about to add support for high-word operations, so it seemed better
for the low-word registers to have names like R0L rather than R0W.
No behavioral change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191655
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Craig Topper [Mon, 30 Sep 2013 06:23:19 +0000 (06:23 +0000)]
Filter out repeated sections from the X86 disassembler modRMTable. Saves about ~43K from a released build. Unfortunately the disassembler tables are still upwards of 800K.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191652
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Craig Topper [Mon, 30 Sep 2013 02:50:51 +0000 (02:50 +0000)]
Add a few more FMA4 disassembler test cases to match the scalar set with regards to combinations of L and W-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191650
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Craig Topper [Mon, 30 Sep 2013 02:46:36 +0000 (02:46 +0000)]
Various x86 disassembler fixes.
Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191649
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Benjamin Kramer [Sun, 29 Sep 2013 19:39:13 +0000 (19:39 +0000)]
ObjectSizeOffsetEvaluator: Don't run into infinite recursion if we have a cyclic GEP.
Those can occur in dead code. PR17402.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191644
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Benjamin Kramer [Sun, 29 Sep 2013 19:39:02 +0000 (19:39 +0000)]
Remove an old workaround for a compiler that EOL'd years ago.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191643
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Benjamin Kramer [Sun, 29 Sep 2013 11:29:20 +0000 (11:29 +0000)]
Plug a memory leak in a unit test. Stack allocation is sufficient here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191638
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Benjamin Kramer [Sun, 29 Sep 2013 11:24:02 +0000 (11:24 +0000)]
Deallocate type units when destroying a DWARFContext.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191637
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Benjamin Kramer [Sun, 29 Sep 2013 11:18:56 +0000 (11:18 +0000)]
Allocate AtomicSDNode operands in SelectionDAG's allocator to stop leakage.
SDNode destructors are never called. As an optimization use AtomicSDNode's
internal storage if we have a small number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191636
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