Chad Rosier [Thu, 15 Dec 2011 22:11:31 +0000 (22:11 +0000)]
Add missing zmovl AVX patterns which were causing crashes.
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146689
91177308-0d34-0410-b5e6-
96231b3b80d8
Kostya Serebryany [Thu, 15 Dec 2011 21:59:03 +0000 (21:59 +0000)]
[asan] fix a bug (issue 19) where dlclose and the following mmap caused a false positive. compiler part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146688
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Thu, 15 Dec 2011 21:54:55 +0000 (21:54 +0000)]
Silence warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146686
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Thu, 15 Dec 2011 21:44:33 +0000 (21:44 +0000)]
ARM NEON two-register double spaced register list parsing support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146685
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Thu, 15 Dec 2011 21:34:44 +0000 (21:34 +0000)]
Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX.
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146684
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Friedman [Thu, 15 Dec 2011 21:11:38 +0000 (21:11 +0000)]
Zap unnecessary semicolons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146682
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 15 Dec 2011 20:22:34 +0000 (20:22 +0000)]
Set specific target cpu for testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146678
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 15 Dec 2011 19:56:07 +0000 (19:56 +0000)]
Added test case for r146671.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146675
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Thu, 15 Dec 2011 19:26:23 +0000 (19:26 +0000)]
Use the proper comparator for set_intersection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146674
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 15 Dec 2011 18:57:27 +0000 (18:57 +0000)]
Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/
10559581>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146671
91177308-0d34-0410-b5e6-
96231b3b80d8
Devang Patel [Thu, 15 Dec 2011 18:21:18 +0000 (18:21 +0000)]
Update DebugLoc while merging nodes at -O0.
Patch by Kyriakos Georgiou!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146670
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Thu, 15 Dec 2011 17:59:23 +0000 (17:59 +0000)]
Add a test case to make sure that the nop really does follow the bl on ppc64 elf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146666
91177308-0d34-0410-b5e6-
96231b3b80d8
Devang Patel [Thu, 15 Dec 2011 17:55:56 +0000 (17:55 +0000)]
Virtual table holder field is either metadata or null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146665
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Thu, 15 Dec 2011 17:54:01 +0000 (17:54 +0000)]
Ensure that the nop that should follow a bl call in PPC64 ELF actually does
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146664
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Thu, 15 Dec 2011 16:48:55 +0000 (16:48 +0000)]
Synthesize missing register class intersections.
The function TRI::getCommonSubClass(A, B) returns the largest common
sub-class of the register classes A and B. This patch teaches TableGen
to synthesize sub-classes such that the answer is always maximal.
In other words, every register that is in both A and B will also be
present in getCommonSubClass(A, B).
This introduces these synthetic register classes:
ARM:
GPRnopc_and_hGPR
GPRnopc_and_hGPR
hGPR_and_rGPR
GPRnopc_and_hGPR
GPRnopc_and_hGPR
hGPR_and_rGPR
tGPR_and_tcGPR
hGPR_and_tcGPR
X86:
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR64_NOSP_and_GR64_TC
GR64_NOSP_and_GR64_TC
GR64_NOREX_and_GR64_TC
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR64_NOSP_and_GR64_TC
GR64_NOREX_and_GR64_TC
GR64_NOREX_NOSP_and_GR64_TC
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR32_ABCD_and_GR32_NOAX
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR32_ABCD_and_GR32_NOAX
GR32_NOAX_and_GR32_TC
GR32_NOAX_and_GR32_NOSP
GR64_NOSP_and_GR64_TC
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR64_NOREX_and_GR64_TC
GR64_NOREX_NOSP_and_GR64_TC
GR32_ABCD_and_GR32_NOAX
GR64_ABCD_and_GR64_TC
GR32_NOAX_and_GR32_TC
GR32_AD_and_GR32_NOAX
Other targets are unaffected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146657
91177308-0d34-0410-b5e6-
96231b3b80d8
Richard Osborne [Thu, 15 Dec 2011 15:18:35 +0000 (15:18 +0000)]
Pass optLevel to XCoreDAGToDAGISel.
Patch by Kyriakos Georgiou.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146656
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Friedman [Thu, 15 Dec 2011 04:52:47 +0000 (04:52 +0000)]
Fix test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146642
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Friedman [Thu, 15 Dec 2011 04:33:48 +0000 (04:33 +0000)]
Make constant folding for GEPs a bit more aggressive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146639
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Friedman [Thu, 15 Dec 2011 02:07:20 +0000 (02:07 +0000)]
Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146630
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Thu, 15 Dec 2011 01:16:09 +0000 (01:16 +0000)]
Use SmallVector/assign(), rather than std::vector/push_back().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146627
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Thu, 15 Dec 2011 01:02:25 +0000 (01:02 +0000)]
Add support for lowering fneg when AVX is enabled.
rdar://
10566486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146625
91177308-0d34-0410-b5e6-
96231b3b80d8
Pete Cooper [Thu, 15 Dec 2011 00:56:45 +0000 (00:56 +0000)]
Added InstCombine for "select cond, ~cond, x" type patterns
These can be reduced to "~cond & x" or "~cond | x"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146624
91177308-0d34-0410-b5e6-
96231b3b80d8
Owen Anderson [Thu, 15 Dec 2011 00:54:12 +0000 (00:54 +0000)]
Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls. These are already marked as illegal by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146623
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Friedman [Thu, 15 Dec 2011 00:50:34 +0000 (00:50 +0000)]
Make loop preheader insertion in LoopSimplify handle the case where the loop header is a landing pad correctly (by splitting the landingpad out of the loop header). Make some adjustments to the rest of LoopSimplify to make it clear that the rest of LoopSimplify isn't making bad assumptions about the presence of landing pads. PR11575.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146621
91177308-0d34-0410-b5e6-
96231b3b80d8
Bill Wendling [Thu, 15 Dec 2011 00:14:24 +0000 (00:14 +0000)]
Re-re-enable compact unwind after fixing a failure in SingleSource/Benchmarks/Shootout-C++/except.cpp and friends. It was encoding the stored registers in the wrong order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146617
91177308-0d34-0410-b5e6-
96231b3b80d8
Kevin Enderby [Thu, 15 Dec 2011 00:00:27 +0000 (00:00 +0000)]
Another improvement to the implementation of .incbin directive by avoiding a
buffer copy. Suggestion by Chris Lattner!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146614
91177308-0d34-0410-b5e6-
96231b3b80d8
Bill Wendling [Wed, 14 Dec 2011 23:53:24 +0000 (23:53 +0000)]
The saved registers weren't being processed in the correct order. This lead to
the compact unwind claiming that one register was saved before another, which
isn't all that great in general. Process them in the natural order. Reverse the
list only when necessary for the algorithm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146612
91177308-0d34-0410-b5e6-
96231b3b80d8
Dan Gohman [Wed, 14 Dec 2011 23:49:11 +0000 (23:49 +0000)]
Move Instruction::isSafeToSpeculativelyExecute out of VMCore and
into Analysis as a standalone function, since there's no need for
it to be in VMCore. Also, update it to use isKnownNonZero and
other goodies available in Analysis, making it more precise,
enabling more aggressive optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146610
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Wed, 14 Dec 2011 23:48:54 +0000 (23:48 +0000)]
Consider CPE alignment in CreateNewWater().
An aligned constant pool entry may require extra alignment padding where
the new water is created. Take that into account when computing offset.
Also consider the alignment of other constant pool entries when
splitting a basic block. Alignment padding may make it necessary to
move the split point higher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146609
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Wed, 14 Dec 2011 23:35:06 +0000 (23:35 +0000)]
ARM NEON better assembly operand range checking for lane indices of VLD/VST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146608
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Wed, 14 Dec 2011 23:25:46 +0000 (23:25 +0000)]
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605
91177308-0d34-0410-b5e6-
96231b3b80d8
Devang Patel [Wed, 14 Dec 2011 23:20:38 +0000 (23:20 +0000)]
Do not sink instruction, if it is not profitable.
On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator.
Radar
10266272.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146604
91177308-0d34-0410-b5e6-
96231b3b80d8
Evan Cheng [Wed, 14 Dec 2011 22:57:45 +0000 (22:57 +0000)]
Add a blurb about MachineInstr bundling support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146603
91177308-0d34-0410-b5e6-
96231b3b80d8
Bill Wendling [Wed, 14 Dec 2011 22:45:33 +0000 (22:45 +0000)]
Reapply r146481 with a fix to create the Builder value in the correct place and
with the correct iterator.
<rdar://problem/
10530851>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146600
91177308-0d34-0410-b5e6-
96231b3b80d8
Kevin Enderby [Wed, 14 Dec 2011 22:34:45 +0000 (22:34 +0000)]
Improve the implementation of .incbin directive by replacing a loop by using
getStreamer().EmitBytes. Suggestion by Benjamin Kramer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146599
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrew Trick [Wed, 14 Dec 2011 22:07:19 +0000 (22:07 +0000)]
LSR: Fold redundant bitcasts on-the-fly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146597
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Wed, 14 Dec 2011 21:49:24 +0000 (21:49 +0000)]
ARM NEON fix alignment encoding for VST2 w/ writeback.
Add tests for w/ writeback instruction parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146594
91177308-0d34-0410-b5e6-
96231b3b80d8
Kevin Enderby [Wed, 14 Dec 2011 21:47:48 +0000 (21:47 +0000)]
Add the .incbin directive which takes the binary data from a file and emits
it to the streamer. rdar://
10383898
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146592
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Wed, 14 Dec 2011 21:41:32 +0000 (21:41 +0000)]
Nuke old code. Missed in last commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146590
91177308-0d34-0410-b5e6-
96231b3b80d8
Evan Cheng [Wed, 14 Dec 2011 21:32:14 +0000 (21:32 +0000)]
Add high level description of MachineInstr bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146589
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Wed, 14 Dec 2011 21:32:11 +0000 (21:32 +0000)]
ARM NEON refactor VST2 w/ writeback instructions.
In addition to improving the representation, this adds support for assembly
parsing of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146588
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Wed, 14 Dec 2011 20:59:15 +0000 (20:59 +0000)]
ARM NEON improve factoring a bit. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146585
91177308-0d34-0410-b5e6-
96231b3b80d8
Evan Cheng [Wed, 14 Dec 2011 20:00:08 +0000 (20:00 +0000)]
Model ARM predicated write as read-mod-write. e.g.
r0 = mov #0
r0 = moveq #1
Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146583
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Wed, 14 Dec 2011 19:35:22 +0000 (19:35 +0000)]
ARM NEON VST2 assembly parsing and encoding.
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579
91177308-0d34-0410-b5e6-
96231b3b80d8
Stepan Dyatkovskiy [Wed, 14 Dec 2011 19:19:17 +0000 (19:19 +0000)]
Fix for bug #11429: Wrong behaviour for switches. Small improvement for code size heuristics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146578
91177308-0d34-0410-b5e6-
96231b3b80d8
Dan Gohman [Wed, 14 Dec 2011 19:10:53 +0000 (19:10 +0000)]
It turns out that clang does use pointer-to-function types to
point to ARC-managed pointers sometimes. This fixes rdar://
10551239.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146577
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Wed, 14 Dec 2011 18:49:13 +0000 (18:49 +0000)]
Fix speling and 80-col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146575
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Wed, 14 Dec 2011 18:26:41 +0000 (18:26 +0000)]
Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object
emission is not supported yet, but a patch that adds the support should follow
soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146572
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Wed, 14 Dec 2011 18:12:37 +0000 (18:12 +0000)]
Fix copy/pasto that skipped the 'modify' step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146571
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Wed, 14 Dec 2011 17:56:51 +0000 (17:56 +0000)]
ARM/Thumb2 mov vs. mvn alias goes both ways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146570
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Wed, 14 Dec 2011 17:55:03 +0000 (17:55 +0000)]
VFP2 is required for FP loads. Noticed by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146569
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Wed, 14 Dec 2011 17:32:02 +0000 (17:32 +0000)]
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146568
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Wed, 14 Dec 2011 17:30:24 +0000 (17:30 +0000)]
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://
10552389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146567
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Wed, 14 Dec 2011 17:26:05 +0000 (17:26 +0000)]
Fix 80-column violation and extraneous brackets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146566
91177308-0d34-0410-b5e6-
96231b3b80d8
Duncan Sands [Wed, 14 Dec 2011 15:44:20 +0000 (15:44 +0000)]
Vectors are not aggregate types (see isAggregateType).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146561
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Wed, 14 Dec 2011 03:50:53 +0000 (03:50 +0000)]
llvm/lib/CodeGen: Fix cmake build since r146542.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146550
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Friedman [Wed, 14 Dec 2011 02:54:39 +0000 (02:54 +0000)]
Fix a stupid typo in MemDepPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146549
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Friedman [Wed, 14 Dec 2011 02:28:54 +0000 (02:28 +0000)]
Add missing cases to SDNode::getOperationName(). Patch by Micah Villmow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146548
91177308-0d34-0410-b5e6-
96231b3b80d8
Evan Cheng [Wed, 14 Dec 2011 02:28:53 +0000 (02:28 +0000)]
Allow target to specify register output dependency. Still default to one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146547
91177308-0d34-0410-b5e6-
96231b3b80d8
Bill Wendling [Wed, 14 Dec 2011 02:18:26 +0000 (02:18 +0000)]
Revert r146481 to review possible miscompilations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146546
91177308-0d34-0410-b5e6-
96231b3b80d8
Bill Wendling [Wed, 14 Dec 2011 02:16:54 +0000 (02:16 +0000)]
Disable to review some failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146545
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Wed, 14 Dec 2011 02:16:11 +0000 (02:16 +0000)]
ARM assembler support for the target-specific .req directive.
rdar://
10549683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146543
91177308-0d34-0410-b5e6-
96231b3b80d8
Evan Cheng [Wed, 14 Dec 2011 02:11:42 +0000 (02:11 +0000)]
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146542
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Wed, 14 Dec 2011 01:34:39 +0000 (01:34 +0000)]
Add newline at EOF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146538
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Lewycky [Wed, 14 Dec 2011 00:56:07 +0000 (00:56 +0000)]
DW_AT_virtuality is also defined to be constant, not flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146534
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Wed, 14 Dec 2011 00:29:31 +0000 (00:29 +0000)]
Per discussion on the list, remove BitcodeVerify pass to reimplement as a free function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146531
91177308-0d34-0410-b5e6-
96231b3b80d8
Kostya Serebryany [Wed, 14 Dec 2011 00:01:51 +0000 (00:01 +0000)]
[asan] remove .preinit_array from the compiler module (it breaks .so builds). This should be done in the run-time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146527
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael J. Spencer [Tue, 13 Dec 2011 23:17:29 +0000 (23:17 +0000)]
llvm-nm: refactor in order to support reading files from stdin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146524
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael J. Spencer [Tue, 13 Dec 2011 23:17:12 +0000 (23:17 +0000)]
Support/FileSystem: Add file_magic and move a vew clients over to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146523
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael J. Spencer [Tue, 13 Dec 2011 23:16:49 +0000 (23:16 +0000)]
Support/Program: Make Change<stream>ToBinary return error_code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146522
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael J. Spencer [Tue, 13 Dec 2011 23:16:15 +0000 (23:16 +0000)]
Cleanup whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146521
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Tue, 13 Dec 2011 22:45:11 +0000 (22:45 +0000)]
Thumb2 assembler aliases for "mov(shifted register)"
rdar://
10549767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146520
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Tue, 13 Dec 2011 21:48:29 +0000 (21:48 +0000)]
ARM LDM/STM system instruction variants.
rdar://
10550269
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146519
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Tue, 13 Dec 2011 21:10:25 +0000 (21:10 +0000)]
Thumb2 pre/post indexed stores can be from any non-PC GPR.
rdar://
10549786
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146518
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Tue, 13 Dec 2011 21:06:59 +0000 (21:06 +0000)]
Test for 146516
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146517
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Tue, 13 Dec 2011 21:06:41 +0000 (21:06 +0000)]
Thumb2 tweak for ccout handling in RSB parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146516
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Tue, 13 Dec 2011 20:50:38 +0000 (20:50 +0000)]
ARM thumb2 parsing of "rsb rd, rn, #0".
rdar://
10549741
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146515
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Tue, 13 Dec 2011 20:40:37 +0000 (20:40 +0000)]
ARM NEON two-operand aliases for VQDMULH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146514
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Tue, 13 Dec 2011 20:23:22 +0000 (20:23 +0000)]
ARM pre-UAL NEG mnemonic for convenience when porting old code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146511
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Tue, 13 Dec 2011 20:13:48 +0000 (20:13 +0000)]
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146508
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Tue, 13 Dec 2011 20:08:32 +0000 (20:08 +0000)]
ARM add more 'gas' compatibility aliases for NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146507
91177308-0d34-0410-b5e6-
96231b3b80d8
Kostya Serebryany [Tue, 13 Dec 2011 19:46:24 +0000 (19:46 +0000)]
mention AddressSanitizer in 3.1 release notes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146505
91177308-0d34-0410-b5e6-
96231b3b80d8
Kostya Serebryany [Tue, 13 Dec 2011 19:34:53 +0000 (19:34 +0000)]
[asan] report an error if blacklist file contains a malformed regex. fixes asan issue 17
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146503
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Tue, 13 Dec 2011 19:22:14 +0000 (19:22 +0000)]
[fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
load and then move the result from a GPR to a FPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146502
91177308-0d34-0410-b5e6-
96231b3b80d8
Chris Lattner [Tue, 13 Dec 2011 17:55:30 +0000 (17:55 +0000)]
Rip llvm 3.0 out of the release notes, making room for LLVM 3.1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146493
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Tue, 13 Dec 2011 17:45:06 +0000 (17:45 +0000)]
[fast-isel] Remove SelectInsertValue() as fast-isel wasn't designed to handle
instructions that define aggregate types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146492
91177308-0d34-0410-b5e6-
96231b3b80d8
Bill Wendling [Tue, 13 Dec 2011 09:22:43 +0000 (09:22 +0000)]
Avoid using the 'insertvalue' instruction here.
Fast ISel isn't able to handle 'insertvalue' and it causes a large slowdown
during -O0 compilation. We don't necessarily need to generate an aggregate of
the values here if they're just going to be extracted directly afterwards.
<rdar://problem/
10530851>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146481
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Lewycky [Tue, 13 Dec 2011 05:09:11 +0000 (05:09 +0000)]
DW_AT_accessibility is "constant" class, not form class, so it may not use
DW_FORM_flag. Use DW_FORM_data1 for one byte.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146475
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Tue, 13 Dec 2011 04:12:49 +0000 (04:12 +0000)]
Add test/MC/Mips/dg.exp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146472
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Tue, 13 Dec 2011 03:50:34 +0000 (03:50 +0000)]
Move direct object emitter test to directory test/MC/Mips. Rename it to
elf-relsym.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146470
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Tue, 13 Dec 2011 03:09:05 +0000 (03:09 +0000)]
Expand .cprestore directive to multiple instructions if the offset does not fit
in a 16-bit field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146469
91177308-0d34-0410-b5e6-
96231b3b80d8
Akira Hatanaka [Tue, 13 Dec 2011 02:27:40 +0000 (02:27 +0000)]
Relocation against a symbol, instead of against section. We had some extreme
test cases where there were a lot of relocations applied relative to a large
rodata section. Gas would create a symbol for each of these whereas we would
be relative to the beginning of the rodata section. This change mimics what
gas does.
Patch by Jack Carter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146468
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Tue, 13 Dec 2011 02:19:11 +0000 (02:19 +0000)]
Don't default the *cached* list of targets to build to an explicit list
of the targets we know about. Because this is cached, rebuilds won't
detect when new targets show up. It's also a bit simpler to just say
"all". If users want to restrict the target set, they can still do so,
and then the cache will preserve what they have explicitly set this
field to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146467
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Tue, 13 Dec 2011 01:56:10 +0000 (01:56 +0000)]
Initial CodeGen support for CTTZ/CTLZ where a zero input produces an
undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.
Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.
Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146466
91177308-0d34-0410-b5e6-
96231b3b80d8
Bill Wendling [Tue, 13 Dec 2011 01:07:07 +0000 (01:07 +0000)]
Use the example from clang, not the GCC frontend, which doesn't exist anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146461
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrew Trick [Tue, 13 Dec 2011 00:55:33 +0000 (00:55 +0000)]
Cleanup. Clarify LSRInstance public methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146459
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakob Stoklund Olesen [Tue, 13 Dec 2011 00:44:30 +0000 (00:44 +0000)]
Account for CPE alignment when searching for new water.
Constant pool entries with different alignment may cause more alignment
padding to be inserted. Compute the amount of padding needed, and try to
pick the location that requires the least amount of padding.
Also take the extra padding into account when the water is above the
use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146458
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Tue, 13 Dec 2011 00:36:04 +0000 (00:36 +0000)]
Target/Hexagon: Fix CMake build. We don't use add_llvm_library_dependencies().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146457
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Lewycky [Tue, 13 Dec 2011 00:34:14 +0000 (00:34 +0000)]
Don't rely on a particular version string for llvm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146456
91177308-0d34-0410-b5e6-
96231b3b80d8
Tony Linthicum [Tue, 13 Dec 2011 00:33:45 +0000 (00:33 +0000)]
Temporarily disable Hexagon tests. They are failing on OS X
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146455
91177308-0d34-0410-b5e6-
96231b3b80d8