Akira Hatanaka [Wed, 5 Oct 2011 01:09:37 +0000 (01:09 +0000)]
Add comments and move assignment statement. If sawStore is true, sawLoad does
not have to be set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141147
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Akira Hatanaka [Wed, 5 Oct 2011 01:06:57 +0000 (01:06 +0000)]
Correct description string of enable-mips-delay-filler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141146
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Bill Wendling [Wed, 5 Oct 2011 00:39:32 +0000 (00:39 +0000)]
Look at the number of entries in the jump table and jump to a 'trap' block if
the value exceeds that number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141143
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Jakob Stoklund Olesen [Wed, 5 Oct 2011 00:35:49 +0000 (00:35 +0000)]
Add TRI::getSubClassWithSubReg(RC, Idx) function.
This function is used to constrain a register class to a sub-class that
supports the given sub-register index.
For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD.
The function will be used to compute register classes when emitting
INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation
of sub-register operations.
The version provided by TableGen is usually adequate, but targets can
override.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141142
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Bill Wendling [Wed, 5 Oct 2011 00:02:33 +0000 (00:02 +0000)]
Checkpoint for SJLJ EH code.
This is a first pass at generating the jump table for the sjlj dispatch. It
currently generates something plausible, but hasn't been tested thoroughly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141140
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Jakob Stoklund Olesen [Wed, 5 Oct 2011 00:01:48 +0000 (00:01 +0000)]
Also add <imp-use,kill> flags for redefined super-registers.
For example:
%vreg10:dsub_0<def,undef> = COPY %vreg1
%vreg10:dsub_1<def> = COPY %vreg2
is rewritten as:
%D2<def> = COPY %D0, %Q1<imp-def>
%D3<def> = COPY %D1, %Q1<imp-use,kill>, %Q1<imp-def>
The first COPY doesn't care about the previous value of %Q1, so it
doesn't read that register.
The second COPY is a partial redefinition of %Q1, so it implicitly kills
and redefines that register.
This makes it possible to recognize instructions that can harmlessly
clobber the full super-register. The write and don't read the
super-register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141139
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Jakob Stoklund Olesen [Wed, 5 Oct 2011 00:01:46 +0000 (00:01 +0000)]
Also add <def,undef> flags when coalescing sub-registers.
RegisterCoalescer can create sub-register defs when it is joining a
register with a sub-register. Add <undef> flags to these new
sub-register defs where appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141138
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Owen Anderson [Tue, 4 Oct 2011 23:26:17 +0000 (23:26 +0000)]
Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141135
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Kevin Enderby [Tue, 4 Oct 2011 22:44:48 +0000 (22:44 +0000)]
Adding back support for printing operands symbolically to ARM's new disassembler
using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141129
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Bill Wendling [Tue, 4 Oct 2011 22:00:35 +0000 (22:00 +0000)]
Create a mapping between the landing pad basic block and the call site index for later use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141125
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Jakob Stoklund Olesen [Tue, 4 Oct 2011 21:49:33 +0000 (21:49 +0000)]
Allow <undef> flags on def operands as well as uses.
The <undef> flag says that a MachineOperand doesn't read its register,
or doesn't depend on the previous value of its register.
A full register def never depends on the previous register value. A
partial register def may depend on the previous value if it is intended
to update part of a register.
For example:
%vreg10:dsub_0<def,undef> = COPY %vreg1
%vreg10:dsub_1<def> = COPY %vreg2
The first copy instruction defines the full %vreg10 register with the
bits not covered by dsub_0 defined as <undef>. It is not considered a
read of %vreg10.
The second copy modifies part of %vreg10 while preserving the rest. It
has an implicit read of %vreg10.
This patch adds a MachineOperand::readsReg() method to determine if an
operand reads its register.
Previously, this was modelled by adding a full-register <imp-def>
operand to the instruction. This approach makes it possible to
determine directly from a MachineOperand if it reads its register. No
scanning of MI operands is required.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141124
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Jim Grosbach [Tue, 4 Oct 2011 21:43:51 +0000 (21:43 +0000)]
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141123
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Bill Wendling [Tue, 4 Oct 2011 21:25:01 +0000 (21:25 +0000)]
Doxygen-ize comments. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141122
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Daniel Dunbar [Tue, 4 Oct 2011 21:17:19 +0000 (21:17 +0000)]
Remove unused web page.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141118
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Jim Grosbach [Tue, 4 Oct 2011 21:16:42 +0000 (21:16 +0000)]
Un-XFAIL file. Comment out individual failing instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141117
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Francois Pichet [Tue, 4 Oct 2011 21:08:56 +0000 (21:08 +0000)]
Replace snprintf with raw_string_ostream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141116
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Jim Grosbach [Tue, 4 Oct 2011 20:52:57 +0000 (20:52 +0000)]
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141115
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Jim Grosbach [Tue, 4 Oct 2011 20:50:05 +0000 (20:50 +0000)]
Un-XFAIL file. Fix incorrect CHECK lines. General format cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141114
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Jim Grosbach [Tue, 4 Oct 2011 20:46:49 +0000 (20:46 +0000)]
Un-XFAIL file. Fix incorrect CHECK line. General format cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141113
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Jim Grosbach [Tue, 4 Oct 2011 20:42:35 +0000 (20:42 +0000)]
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141111
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Jim Grosbach [Tue, 4 Oct 2011 20:42:09 +0000 (20:42 +0000)]
Un-XFAIL file. Fix incorrect CHECK line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141110
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Jim Grosbach [Tue, 4 Oct 2011 20:34:11 +0000 (20:34 +0000)]
Un-XFAIL the file. Disable only the individual tests that aren't working yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141108
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Bill Wendling [Tue, 4 Oct 2011 20:31:56 +0000 (20:31 +0000)]
Add method to determine if a begin label has a call site number associated with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141107
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Jakob Stoklund Olesen [Tue, 4 Oct 2011 20:18:39 +0000 (20:18 +0000)]
Properly use const_iterator.
This should unbreak the Windows build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141105
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Devang Patel [Tue, 4 Oct 2011 19:38:16 +0000 (19:38 +0000)]
Update cmake list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141104
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David Chisnall [Tue, 4 Oct 2011 19:36:30 +0000 (19:36 +0000)]
Tell people using the tutorial how to make it actually work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141103
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David Greene [Tue, 4 Oct 2011 18:55:40 +0000 (18:55 +0000)]
Test Operand Arguments
Add a test to do list manipulation and pass the result as arguments.
This tests the new list element operator resolve code and provides an
example of using list manipulation to do instruction pattern
substitution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141102
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David Greene [Tue, 4 Oct 2011 18:55:36 +0000 (18:55 +0000)]
Allow Operator Arguments
When resolving an operator list element reference, resolve all
operator operands and try to fold the operator first. This allows the
operator to collapse to a list which may then be indexed.
Before, it was not possible to do this:
class D<int a, int b> { ... }
class C<list<int> A> : D<A[0], A[1]>;
class B<list<int> b> : C<!foreach(...,b)>;
Now it is.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141101
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Jim Grosbach [Tue, 4 Oct 2011 18:43:15 +0000 (18:43 +0000)]
Un-XFAIL the file. Disable only the individual tests that aren't working yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141099
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Ted Kremenek [Tue, 4 Oct 2011 18:22:24 +0000 (18:22 +0000)]
Unbreak CMake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141097
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Jim Grosbach [Tue, 4 Oct 2011 17:49:45 +0000 (17:49 +0000)]
Tidy up. Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141096
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Devang Patel [Tue, 4 Oct 2011 17:24:48 +0000 (17:24 +0000)]
Put GCOVFile and other related interface in a common header so that llvm-cov tool can share it with GCOV writer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141095
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Francois Pichet [Tue, 4 Oct 2011 16:28:07 +0000 (16:28 +0000)]
Unbreak MSVC build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141093
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David Dean [Tue, 4 Oct 2011 16:26:41 +0000 (16:26 +0000)]
Fix PR9833/PR11054 (patch provided by Patrik Hägglund)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141092
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Jakob Stoklund Olesen [Tue, 4 Oct 2011 15:28:49 +0000 (15:28 +0000)]
Teach TableGen to infer missing register classes.
The set of register classes should be closed under sub-register
operations and intersections. That will allow the register allocator to
model combinations of constraints accurately.
This patch implements the easiest form of register class inference: For
every register class, and for every sub-register SubIdx, the subset of
registers in RC that have a SubIdx sub-register should also be a register
class.
This does create some new register classes for the targets in the tree:
ARM gets a new QQQQPR_with_ssub_0. This class was omitted from the .td
file on purpose because it only has two registers. InstrEmitter and
RegisterCoalescer have safeguards against selecting too small register
classes, so it is harmless.
PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32
sub-register of LR8. I think that might be an omission?
X86 puts RIP in the GR64 class, and since that register doesn't have
8-bit sub-registers, we get:
GR64_with_sub_8bit
GR64_TC_with_sub_8bit
GR64_NOREX_with_sub_8bit
GR64_TC_with_sub_8bit_hi
The various CodeGen classes have already been fixed so adding new
register classes should not affect compile time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141084
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Jakob Stoklund Olesen [Tue, 4 Oct 2011 15:28:47 +0000 (15:28 +0000)]
Teach PPCInstrInfo to handle sub-classes.
This has already been done for most other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141083
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Jakob Stoklund Olesen [Tue, 4 Oct 2011 15:28:44 +0000 (15:28 +0000)]
TableGen: Store all allocation orders together.
There is no need to keep the primary order separate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141082
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Jakob Stoklund Olesen [Tue, 4 Oct 2011 15:28:08 +0000 (15:28 +0000)]
TableGen: Privatize CodeGenRegisterClass::TheDef and Name.
When TableGen starts creating its own register classes, the synthesized
classes won't have a Record reference. All register classes must have a
name, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141081
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Jakob Stoklund Olesen [Tue, 4 Oct 2011 15:27:53 +0000 (15:27 +0000)]
TableGen: Don't add synthetic Records to the RecordKeeper.
The RecordKeeper could be shared by multiple target instances, causing
duplicate record errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141080
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Che-Liang Chiou [Tue, 4 Oct 2011 15:14:51 +0000 (15:14 +0000)]
tblgen: add preprocessor as a separate mode
This patch adds a preprocessor that can expand nested for-loops for
saving some copy-n-paste in *.td files.
The preprocessor is not yet integrated with TGParser, and so it has
no direct effect on *.td inputs. However, you may preprocess an td
input (and only preprocess it).
To test the proprecessor, type:
tblgen -E -o $@ $<
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141079
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Nadav Rotem [Tue, 4 Oct 2011 12:05:35 +0000 (12:05 +0000)]
Set operation actions to legal types only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141075
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Nadav Rotem [Tue, 4 Oct 2011 10:03:32 +0000 (10:03 +0000)]
Operations should be custom lowered only if their type is legal.
Test: CellSPU/v2i32.ll when running with -promote-elements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141074
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Nick Lewycky [Tue, 4 Oct 2011 06:51:26 +0000 (06:51 +0000)]
The product of two chrec's can always be represented as a chrec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141066
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Craig Topper [Tue, 4 Oct 2011 06:30:42 +0000 (06:30 +0000)]
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065
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Andrew Trick [Tue, 4 Oct 2011 03:50:44 +0000 (03:50 +0000)]
LSR should avoid redundant edge splitting.
This handles the case in which LSR rewrites an IV user that is a phi and
splits critical edges originating from a switch.
Fixes <rdar://problem/
6453893> LSR is not splitting edges "nicely"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141059
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Andrew Trick [Tue, 4 Oct 2011 03:34:49 +0000 (03:34 +0000)]
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141058
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Rafael Espindola [Tue, 4 Oct 2011 03:08:43 +0000 (03:08 +0000)]
Remove last references to hotpatch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141057
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Peter Collingbourne [Tue, 4 Oct 2011 00:30:34 +0000 (00:30 +0000)]
Exclude libLLVMTableGen.a from the shared library
Unbreaks tools for --enable-shared build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141052
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Bill Wendling [Tue, 4 Oct 2011 00:16:40 +0000 (00:16 +0000)]
Generic cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141050
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Andrew Trick [Tue, 4 Oct 2011 00:07:02 +0000 (00:07 +0000)]
Unit test for r140919, loop unroll heuristics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141049
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Jim Grosbach [Mon, 3 Oct 2011 23:40:13 +0000 (23:40 +0000)]
Tidy up. These tests are covered in the .s file tests now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141047
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Jim Grosbach [Mon, 3 Oct 2011 23:38:36 +0000 (23:38 +0000)]
ARM assembly parsing and encoding for VMOV immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046
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Jim Grosbach [Mon, 3 Oct 2011 23:03:26 +0000 (23:03 +0000)]
Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141043
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Bill Wendling [Mon, 3 Oct 2011 22:44:15 +0000 (22:44 +0000)]
Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141042
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Bill Wendling [Mon, 3 Oct 2011 22:42:40 +0000 (22:42 +0000)]
Don't carry over the dispatchsetup hack from the old system.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141040
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Jim Grosbach [Mon, 3 Oct 2011 22:30:24 +0000 (22:30 +0000)]
ARM parsing/encoding for VCMP/VCMPE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038
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Nick Lewycky [Mon, 3 Oct 2011 21:30:08 +0000 (21:30 +0000)]
Fix typo in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141032
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Bill Wendling [Mon, 3 Oct 2011 21:25:38 +0000 (21:25 +0000)]
Check-pointing the new SjLj EH lowering.
This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141031
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Akira Hatanaka [Mon, 3 Oct 2011 21:24:30 +0000 (21:24 +0000)]
Move CHECK after entry label.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141030
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Akira Hatanaka [Mon, 3 Oct 2011 21:23:18 +0000 (21:23 +0000)]
Add support for 64-bit logical NOR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141029
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Akira Hatanaka [Mon, 3 Oct 2011 21:16:50 +0000 (21:16 +0000)]
Add support for 64-bit count leading ones and zeros instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141028
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Bill Wendling [Mon, 3 Oct 2011 21:15:28 +0000 (21:15 +0000)]
Move the grabbing of the jump buffer into the caller function, eliminating the need for returning a std::pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141026
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Jim Grosbach [Mon, 3 Oct 2011 21:12:43 +0000 (21:12 +0000)]
ARM assembly parsing and encoding for VMRS/FMSTAT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025
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Akira Hatanaka [Mon, 3 Oct 2011 21:06:13 +0000 (21:06 +0000)]
Add support for 64-bit divide instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141024
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Devang Patel [Mon, 3 Oct 2011 20:59:18 +0000 (20:59 +0000)]
Add C api for Instruction->eraseFromParent().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141023
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Jim Grosbach [Mon, 3 Oct 2011 20:58:08 +0000 (20:58 +0000)]
Update test for 141010.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141022
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Jim Grosbach [Mon, 3 Oct 2011 20:51:59 +0000 (20:51 +0000)]
Thumb2 ADD/SUB can take SP as a destination register.
It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141020
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Akira Hatanaka [Mon, 3 Oct 2011 20:38:08 +0000 (20:38 +0000)]
Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141019
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Akira Hatanaka [Mon, 3 Oct 2011 20:01:11 +0000 (20:01 +0000)]
Add support for 64-bit integer multiply instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141017
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Akira Hatanaka [Mon, 3 Oct 2011 19:28:44 +0000 (19:28 +0000)]
Add definitions of instructions which move values between 64-bit integer
registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141015
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Bob Wilson [Mon, 3 Oct 2011 18:48:16 +0000 (18:48 +0000)]
Find the strip tool that works with the specified SDKROOT. rdar://
10165908
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141013
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Jim Grosbach [Mon, 3 Oct 2011 17:59:31 +0000 (17:59 +0000)]
Tidy up a bit. Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141010
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Craig Topper [Mon, 3 Oct 2011 17:28:23 +0000 (17:28 +0000)]
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007
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Eric Christopher [Mon, 3 Oct 2011 15:49:20 +0000 (15:49 +0000)]
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141005
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Eric Christopher [Mon, 3 Oct 2011 15:49:16 +0000 (15:49 +0000)]
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141004
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Rafael Espindola [Mon, 3 Oct 2011 14:45:37 +0000 (14:45 +0000)]
Add the returns_twice attribute to LLVM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141001
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Craig Topper [Mon, 3 Oct 2011 08:14:29 +0000 (08:14 +0000)]
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140997
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Craig Topper [Mon, 3 Oct 2011 07:53:59 +0000 (07:53 +0000)]
Test updates that were supposed to go with r140993.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140994
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Craig Topper [Mon, 3 Oct 2011 07:51:09 +0000 (07:51 +0000)]
Fix VEX disassembling to ignore REX.RXBW bits in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140993
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Nick Lewycky [Mon, 3 Oct 2011 07:10:45 +0000 (07:10 +0000)]
Reapply r140979 with fix! We never did get a testcase, but careful review of the
logic by David Meyer revealed this bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140992
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Torok Edwin [Mon, 3 Oct 2011 06:41:46 +0000 (06:41 +0000)]
attempt to fix ocaml bindings: landing pads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140991
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Nick Lewycky [Mon, 3 Oct 2011 05:14:59 +0000 (05:14 +0000)]
Revert r140979 due to reports of bootstrap failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140980
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Nick Lewycky [Mon, 3 Oct 2011 01:03:57 +0000 (01:03 +0000)]
Add one more case we compute a max trip count.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140979
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Craig Topper [Sun, 2 Oct 2011 21:08:12 +0000 (21:08 +0000)]
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974
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Craig Topper [Sun, 2 Oct 2011 16:56:09 +0000 (16:56 +0000)]
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140971
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Nick Lewycky [Sun, 2 Oct 2011 10:37:37 +0000 (10:37 +0000)]
Add a new icmp+select optz'n. Also shows off the load(cst) folding added in
r140966.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140969
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Nick Lewycky [Sun, 2 Oct 2011 09:12:55 +0000 (09:12 +0000)]
Enhance a couple places where we were doing constant folding of instructions,
but not load instructions. Noticed by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140966
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Craig Topper [Sun, 2 Oct 2011 04:54:26 +0000 (04:54 +0000)]
Fix typo in r140954.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140962
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Ted Kremenek [Sun, 2 Oct 2011 01:47:07 +0000 (01:47 +0000)]
Make canonicalization of ImmutableSetRef::asImmutableSet() semi-explicit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140959
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Craig Topper [Sat, 1 Oct 2011 21:20:14 +0000 (21:20 +0000)]
Fix disassembling of INVEPT and INVVPID to take operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140955
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Craig Topper [Sat, 1 Oct 2011 19:54:56 +0000 (19:54 +0000)]
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954
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Chad Rosier [Sat, 1 Oct 2011 19:30:36 +0000 (19:30 +0000)]
Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."
to appease nightly testers. Not quite there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140953
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Nadav Rotem [Sat, 1 Oct 2011 18:39:28 +0000 (18:39 +0000)]
Moved type construction out of the loop and added an assert on the legality of the type. Formatted lines to the 80 char limit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140952
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Peter Collingbourne [Sat, 1 Oct 2011 16:41:13 +0000 (16:41 +0000)]
Move TableGen's parser and entry point into a library
This is the first step towards splitting LLVM and Clang's tblgen executables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951
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Bill Wendling [Sat, 1 Oct 2011 12:47:34 +0000 (12:47 +0000)]
No one should be using the method directly. Assert if they do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140947
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Bill Wendling [Sat, 1 Oct 2011 12:44:28 +0000 (12:44 +0000)]
Add a convenience method to tell if two things are equal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140946
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Bill Wendling [Sat, 1 Oct 2011 09:30:42 +0000 (09:30 +0000)]
Use the ARMConstantPoolMBB class to handle the MBB values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140943
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Bill Wendling [Sat, 1 Oct 2011 09:19:10 +0000 (09:19 +0000)]
Add ARMConstantPoolMBB to hold an MBB value in the constant pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140942
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Bill Wendling [Sat, 1 Oct 2011 09:05:12 +0000 (09:05 +0000)]
Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140941
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Bill Wendling [Sat, 1 Oct 2011 09:04:18 +0000 (09:04 +0000)]
Remove now dead methods and ivar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140940
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