Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108094 91177308-0d34-0410-b5e6-96231b3b80d8

Convert uses of getPhysicalRegisterRegClass in VirtRegRewriter.cpp.

The first one was used just to call isSafeToMoveRegClassDefs. In
general, using a more specific reg class is better, in practice only
x86 implements that method and the results are always the same.

The second one is in FindFreeRegister and is used to check if a register
is in a register class, a much more direct call to contains is better as
it should cover more cases and is faster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108093 91177308-0d34-0410-b5e6-96231b3b80d8

Replace copyRegToReg with copyPhysReg for SystemZ.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108092 91177308-0d34-0410-b5e6-96231b3b80d8

Avoid SSE instructions in FastIsel when it is not available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108091 91177308-0d34-0410-b5e6-96231b3b80d8

Remove two other uses of ATTRIBUTE_UNUSED for variables only used within
assert()s, switching to void-casts. Removed an unneeded Compiler.h include as
a result. There are two other uses in LLVM, but they're not due to assert()s,
so I've left them alone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108088 91177308-0d34-0410-b5e6-96231b3b80d8

Replace copyRegToReg with copyPhysReg for XCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108087 91177308-0d34-0410-b5e6-96231b3b80d8

Replace copyRegToReg with copyPhysReg for Sparc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108086 91177308-0d34-0410-b5e6-96231b3b80d8

Replace copyRegToReg with copyPhysReg for CellSPU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108084 91177308-0d34-0410-b5e6-96231b3b80d8

Replace copyRegToReg with copyPhysReg for PowerPC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108083 91177308-0d34-0410-b5e6-96231b3b80d8

Fix PIC16 comments referencing copyRegToReg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108082 91177308-0d34-0410-b5e6-96231b3b80d8

Replace copyRegToReg with copyPhysReg for PIC16.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108081 91177308-0d34-0410-b5e6-96231b3b80d8

Replace copyRegToReg with copyPhysReg for MSP430.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108080 91177308-0d34-0410-b5e6-96231b3b80d8

Replace copyRegToReg with copyPhysReg for MBlaze.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108079 91177308-0d34-0410-b5e6-96231b3b80d8

Replace copyRegToReg with copyPhysReg for ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108078 91177308-0d34-0410-b5e6-96231b3b80d8

Replace copyRegToReg with copyPhysReg for Blackfin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108077 91177308-0d34-0410-b5e6-96231b3b80d8

X86InstrInfo::copyRegToReg is dead. Long live copyPhysReg!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108076 91177308-0d34-0410-b5e6-96231b3b80d8

Remove copyRegToReg from TargetInstrInfo so it is not longer accesible.

Use a COPY instruction instead for register copies, or TII::copyPhysReg() after
COPY instructions are lowered.

Targets should implement copyPhysReg instead of copyRegToReg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108075 91177308-0d34-0410-b5e6-96231b3b80d8

Use COPY in X86FastISel::X86SelectRet.

Don't try a cross-class copy. That is very unlikely anywy since return value
registers are usually register class friendly. (%EAX, %XMM0, etc).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108074 91177308-0d34-0410-b5e6-96231b3b80d8

Use COPY for fast-isel bitconvert, but don't create cross-class copies.

This doesn't change the behavior of SelectBitcast for X86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108073 91177308-0d34-0410-b5e6-96231b3b80d8

Fix va_arg for doubles. With this patch VAARG nodes always contain the
correct alignment information, which simplifies ExpandRes_VAARG a bit.

The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:

* The 's' in target data: If this is set to the minimal alignment of any
  argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
  example.
* The getTransientStackAlignment method. It is possible for an architecture to
  have argument less aligned than what we maintain the stack pointer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108072 91177308-0d34-0410-b5e6-96231b3b80d8

Replace copyRegToReg with COPY in FastISelEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108071 91177308-0d34-0410-b5e6-96231b3b80d8

Use COPY for extracting ImplicitDef'ed values from fast-isel instructions.

This assumes that the registers can be copied which is probably a safe
assumption.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108070 91177308-0d34-0410-b5e6-96231b3b80d8

Use COPY in FastISel everywhere it is safe and trivial.

The remaining copyRegToReg calls actually check the return value (shock!), so we
cannot trivially replace them with COPY instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108069 91177308-0d34-0410-b5e6-96231b3b80d8

Replace copyRegToReg with copyPhysReg for Mips.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108066 91177308-0d34-0410-b5e6-96231b3b80d8

Replace copyRegToReg with copyPhysReg for Alpha.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108065 91177308-0d34-0410-b5e6-96231b3b80d8

sdiv overflow is outright undefined behavior, with or without the
'exact' keyword. Thanks to nlewycky for pointing this out!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108064 91177308-0d34-0410-b5e6-96231b3b80d8

Use COPY in targets

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108063 91177308-0d34-0410-b5e6-96231b3b80d8

Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108062 91177308-0d34-0410-b5e6-96231b3b80d8

Only collect subreg extracting copies for later coalescing.
This also avoids fatal copies from physregs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108061 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a bug in the code which re-inserts DBG_VALUE nodes after scheduling;
if a block is split (by a custom inserter), the insert point may be in a
different block than it was originally. This fixes 32-bit llvm-gcc
bootstrap builds, and I haven't been able to reproduce it otherwise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108060 91177308-0d34-0410-b5e6-96231b3b80d8

Fix this test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108059 91177308-0d34-0410-b5e6-96231b3b80d8

The accumulator tail recursion transform claims to work for any associative
operation, but the way it's implemented requires the operation to also be
commutative.  So add a check for commutativity (and tweak the corresponding
comments).  This makes no difference in practice since every associative
LLVM instruction is also commutative!  Here's an example to show the need
for commutativity: the accum_recursion.ll testcase calculates the factorial
function.  Before the transformation the result of a call is
  ((((1*1)*2)*3)...)*x
while afterwards it is
  (((1*x)*(x-1))...*2)*1
which clearly requires both associativity and commutativity of * to be equal
to the original.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108056 91177308-0d34-0410-b5e6-96231b3b80d8

Emit COPY instructions instead of using copyRegToReg in InstrEmitter,
ScheduleDAGEmit, TwoAddressLowering, and PHIElimination.

This switches the bulk of register copies to using COPY, but many less used
copyRegToReg calls remain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108050 91177308-0d34-0410-b5e6-96231b3b80d8

Use non-bool values for .count.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108048 91177308-0d34-0410-b5e6-96231b3b80d8

Don't emit st(0)/st(1) copies as FpMOV instructions. Use FpSET_ST? instead.

Based on a patch by Rafael Espíndola.

Attempt to make the FpSET_ST1 hack more robust, but we are still relying on
FpSET_ST0 preceeding it. This is only for supporting really weird x87 inline
asm.

We support:

  FpSET_ST0
  INLINEASM

  FpSET_ST0
  FpSET_ST1
  INLINEASM

with and without kills on the arguments. We don't support:

  FpSET_ST1
  FpSET_ST0
  INLINEASM

nor

  FpSET_ST1
  INLINEASM

Just Don't Do It!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108047 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheckize inline asm FP stack tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108046 91177308-0d34-0410-b5e6-96231b3b80d8

Insert IMPLICIT_DEF instructions at the current insert position, not
at the end of the block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108045 91177308-0d34-0410-b5e6-96231b3b80d8

Add parentheses yet again to satisfy GCC's warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108043 91177308-0d34-0410-b5e6-96231b3b80d8

Add an explicit triple to make this test behave consistently.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108041 91177308-0d34-0410-b5e6-96231b3b80d8

Fix this XTARGET so that this does doesn't XPASS on non-darwin hosts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108040 91177308-0d34-0410-b5e6-96231b3b80d8

Reapply bottom-up fast-isel, with several fixes for x86-32:
 - Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8

An x86 function returns a floating point value in st(0), and we must make sure
it is popped, even if it is ununsed. A CopyFromReg node is too weak to represent
the required sideeffect, so insert an FpGET_ST0 instruction directly instead.

This will matter when CopyFromReg gets lowered to a generic COPY instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108037 91177308-0d34-0410-b5e6-96231b3b80d8

Update DBG_VALUE to refer appropriate stack slot in case of a spill.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108023 91177308-0d34-0410-b5e6-96231b3b80d8

Declare YMM subregisters in the right way! Thanks Jakob

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108022 91177308-0d34-0410-b5e6-96231b3b80d8

Add AVX 256-bit packed MOVNT variants

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108021 91177308-0d34-0410-b5e6-96231b3b80d8

Remember the *_TC opcodes for load/store

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108020 91177308-0d34-0410-b5e6-96231b3b80d8

Add AVX 256-bit unpack and interleave

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108017 91177308-0d34-0410-b5e6-96231b3b80d8

Fix small bug in isMoveInstr -> COPY translation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108013 91177308-0d34-0410-b5e6-96231b3b80d8

Automatically fold COPY instructions into stack load/store.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108012 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a few tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108011 91177308-0d34-0410-b5e6-96231b3b80d8

Remat uncoalescable COPY instrs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108010 91177308-0d34-0410-b5e6-96231b3b80d8

In the presence of variable sized objects, allocate an emergency spill slot.
rdar://8131327

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108008 91177308-0d34-0410-b5e6-96231b3b80d8

Clarify what mysterious check means.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108005 91177308-0d34-0410-b5e6-96231b3b80d8

Add a target triple.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108003 91177308-0d34-0410-b5e6-96231b3b80d8

Fix MachineLICM to actually visit inner loops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108001 91177308-0d34-0410-b5e6-96231b3b80d8

Start the support for AVX instructions with 256-bit %ymm registers. A couple of
notes:
- The instructions are being added with dummy placeholder patterns using some 256
  specifiers, this is not meant to work now, but since there are some multiclasses
  generic enough to accept them,  when we go for codegen, the stuff will be already
  there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
  file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8

Change TII::foldMemoryOperand API to require the machine instruction to be
inserted in a MBB, and return an already inserted MI.

This target API change is necessary to allow foldMemoryOperand to call
storeToStackSlot and loadFromStackSlot when folding a COPY to a stack slot
reference in a target independent way.

The foldMemoryOperandImpl hook is going to change in the same way, but I'll wait
until COPY folding is actually implemented. Most targets only fold copies and
won't need to specialize this hook at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107991 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107990 91177308-0d34-0410-b5e6-96231b3b80d8

remove useless cast and fix typos in comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107989 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107988 91177308-0d34-0410-b5e6-96231b3b80d8

--- Reverse-merging r107947 into '.':
U    utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U    test/CodeGen/X86/fast-isel.ll
U    test/CodeGen/X86/fast-isel-loads.ll
U    include/llvm/Target/TargetLowering.h
U    include/llvm/Support/PassNameParser.h
U    include/llvm/CodeGen/FunctionLoweringInfo.h
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/CodeGen/FastISel.h
U    include/llvm/CodeGen/SelectionDAGISel.h
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/CallingConvLower.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U    lib/CodeGen/SelectionDAG/FastISel.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.h
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86ISelLowering.h

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107984 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107983 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107982 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107981 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107980 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107979 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107978 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107977 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107976 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107975 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107974 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107972 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator* (found by inspection)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107971 91177308-0d34-0410-b5e6-96231b3b80d8

fix clang selfhost issue (shadowing)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107970 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107969 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107968 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107967 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107966 91177308-0d34-0410-b5e6-96231b3b80d8

cache operator*'s result (in multiple functions)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107965 91177308-0d34-0410-b5e6-96231b3b80d8

refactor type expressions and cache operator*'s result

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107964 91177308-0d34-0410-b5e6-96231b3b80d8

do not repeatedly dereference use_iterator

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107963 91177308-0d34-0410-b5e6-96231b3b80d8

do not repeatedly dereference use_iterator

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107962 91177308-0d34-0410-b5e6-96231b3b80d8

two more cases of reuse result of operator*, found by inspection

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107961 91177308-0d34-0410-b5e6-96231b3b80d8

another case of reuse result of operator*, it is expensive to recompute

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107960 91177308-0d34-0410-b5e6-96231b3b80d8

reuse result of operator*, it is expensive to recompute

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107959 91177308-0d34-0410-b5e6-96231b3b80d8

Added a support for inserting new MBBs into the numbering.

Unlike insertMachineInstrInMaps this does not guarantee live intervals will
remain correct. The caller will need to manually update intervals to account
for the changes made to the CFG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107958 91177308-0d34-0410-b5e6-96231b3b80d8

Avoid creating %physreg:subidx operands in SimpleRegisterCoalescing::RemoveCopyByCommutingDef.

This fixes PR7602.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107957 91177308-0d34-0410-b5e6-96231b3b80d8

Deal with a few remaining spots that assume physical registers have live intervals.

This fixes PR7601.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107955 91177308-0d34-0410-b5e6-96231b3b80d8

Merge VEX enums with other x86 enum forms. Also fix all checks of which VEX
fields to use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107952 91177308-0d34-0410-b5e6-96231b3b80d8

Fix test to be less sensitive of regalloc accidents

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107951 91177308-0d34-0410-b5e6-96231b3b80d8

Fix broken isCopy handling in TrimLiveIntervalToLastUse.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107950 91177308-0d34-0410-b5e6-96231b3b80d8

Handle COPY in VirtRegRewriter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107949 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the memoperand offsets in code generated for va_start.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107948 91177308-0d34-0410-b5e6-96231b3b80d8

These changes should have accompanied r107943.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107947 91177308-0d34-0410-b5e6-96231b3b80d8

have the mc lowering process handle a few tail call forms, lowering them to
jumps where possible and turning the TAILCALL marker in the instruction
asm string into a proper comment.

This eliminates a FIXME and is on the path to finishing:
rdar://7639610 - eliminate encoding and asm info for TAILJMPd TAILJMPr TAILJMPn, etc.

However, I can't eliminate the encodings for these instructions because the JIT
still exists and has its own copy of the encoder, sigh.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107946 91177308-0d34-0410-b5e6-96231b3b80d8

Print "dregpair" NEON operands with a space between them, for readability and
consistency with other instructions that have lists of register operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107944 91177308-0d34-0410-b5e6-96231b3b80d8

Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8

Factor out x86 segment override prefix encoding, and also use it for VEX

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107942 91177308-0d34-0410-b5e6-96231b3b80d8

Reenable DAG combining for vector shuffles.  It looks like it was temporarily
disabled and then never turned back on again.  Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8