Justin Holewinski [Wed, 20 Mar 2013 00:10:32 +0000 (00:10 +0000)]
Propagate DAG node ordering during type legalization and instruction selection
A node's ordering is only propagated during legalization if (a) the new node does
not have an ordering (is not a CSE'd node), or (b) the new node has an ordering
that is higher than the node being legalized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177465
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Chad Rosier [Tue, 19 Mar 2013 23:44:03 +0000 (23:44 +0000)]
Fix pr13145 - Naming a function like a register name confuses the asm parser.
Patch by Stepan Dyatkovskiy <stpworld@narod.ru>
rdar://
13457826
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177463
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David Blaikie [Tue, 19 Mar 2013 23:25:22 +0000 (23:25 +0000)]
Move the DIFile operand to DITypes from the 4th operand to the 2nd.
This is another step along the way to making all DIScopes have a common prefix
which can be added to in a general manner to support using directives
(DW_TAG_imported_module).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177462
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Jakob Stoklund Olesen [Tue, 19 Mar 2013 23:23:31 +0000 (23:23 +0000)]
Annotate various null idioms with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177461
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Jakob Stoklund Olesen [Tue, 19 Mar 2013 23:23:29 +0000 (23:23 +0000)]
Annotate SSE float conversions with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177460
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Jakob Stoklund Olesen [Tue, 19 Mar 2013 23:23:26 +0000 (23:23 +0000)]
Annotate X86InstrCMovSetCC.td with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177459
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Eric Christopher [Tue, 19 Mar 2013 23:10:26 +0000 (23:10 +0000)]
Formatting fixups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177458
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Chad Rosier [Tue, 19 Mar 2013 22:13:05 +0000 (22:13 +0000)]
Dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177451
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Chad Rosier [Tue, 19 Mar 2013 22:12:47 +0000 (22:12 +0000)]
Dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177450
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Chad Rosier [Tue, 19 Mar 2013 21:58:18 +0000 (21:58 +0000)]
[ms-inline asm] Move the immediate asm rewrite into the target specific
logic as a QOI cleanup. No functional change. Tests already in place.
rdar://
13456414
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177446
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Quentin Colombet [Tue, 19 Mar 2013 21:46:49 +0000 (21:46 +0000)]
Update global merge pass according to Duncan's advices:
- Remove useless includes
- Change misleading comments
- Move code into doFinalization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177445
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Jakob Stoklund Olesen [Tue, 19 Mar 2013 21:16:56 +0000 (21:16 +0000)]
Annotate X86InstrCompiler.td with SchedRW lists.
Add a new WriteZero SchedWrite type for the common dependency-breaking
instructions that clear a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177442
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Chad Rosier [Tue, 19 Mar 2013 21:12:14 +0000 (21:12 +0000)]
[ms-inline asm] Remove the brackets from X86Operand in the IR. These will be
added back in by X86AsmPrinter::printIntelMemReference() during codegen.
Previously, this following example
void t() {
int i;
__asm mov eax, [i]
}
would generate the below assembly
mov eax, dword ptr [[eax]]
which resulted in a fatal error when compiling. Test case coming on the
clang side.
rdar://
13444264
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177440
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Chad Rosier [Tue, 19 Mar 2013 21:11:56 +0000 (21:11 +0000)]
[ms-inline asm] Create a helper function, CreateMemForInlineAsm, that creates
an X86Operand, but also performs a Sema lookup and adds the sizing directive
when appropriate. Use this when parsing a bracketed statement. This is
necessary to get the instruction matching correct as well. Test case coming
on clang side.
rdar://
13455408
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177439
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Bill Wendling [Tue, 19 Mar 2013 21:03:22 +0000 (21:03 +0000)]
Register the GCOV writeout functions so that they're emitted serially.
We don't want to write out >1000 files at the same time. That could make things
prohibitively expensive. Instead, register the "writeout" function so that it's
emitted serially.
<rdar://problem/
12439551>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177437
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Hal Finkel [Tue, 19 Mar 2013 20:22:32 +0000 (20:22 +0000)]
Add a comment to the CodeGen/PowerPC/asym-regclass-copy.ll test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177434
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Arnaud A. de Grandmaison [Tue, 19 Mar 2013 20:00:22 +0000 (20:00 +0000)]
IndVarSimplify: do not recompute an IV value outside of the loop if :
- it is trivially known to be used inside the loop in a way that can not be optimized away
- there is no use outside of the loop which can take advantage of the computation hoisting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177432
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Ulrich Weigand [Tue, 19 Mar 2013 19:53:27 +0000 (19:53 +0000)]
Add missing mayLoad flag to LHAUX8 and LWAUX.
All pre-increment load patterns need to set the mayLoad flag (since
they don't provide a DAG pattern).
This was missing for LHAUX8 and LWAUX, which is added by this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177431
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Ulrich Weigand [Tue, 19 Mar 2013 19:52:30 +0000 (19:52 +0000)]
Rewrite LHAU8 pattern to use standard memory operand.
As opposed to to pre-increment store patterns, the pre-increment
load patterns were already using standard memory operands, with
the sole exception of LHAU8.
As there's no real reason why LHAU8 should be different here,
this patch simply rewrites the pattern to also use a memri
operand, just like all the other patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177430
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Ulrich Weigand [Tue, 19 Mar 2013 19:52:04 +0000 (19:52 +0000)]
Rewrite pre-increment store patterns to use standard memory operands.
Currently, pre-increment store patterns are written to use two separate
operands to represent address base and displacement:
stwu $rS, $ptroff($ptrreg)
This causes problems when implementing the assembler parser, so this
commit changes the patterns to use standard (complex) memory operands
like in all other memory access instruction patterns:
stwu $rS, $dst
To still match those instructions against the appropriate pre_store
SelectionDAG nodes, the patch uses the new feature that allows a Pat
to match multiple DAG operands against a single (complex) instruction
operand.
Approved by Hal Finkel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177429
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Ulrich Weigand [Tue, 19 Mar 2013 19:51:09 +0000 (19:51 +0000)]
Extend TableGen instruction selection matcher to improve handling
of complex instruction operands (e.g. address modes).
Currently, if a Pat pattern creates an instruction that has a complex
operand (i.e. one that consists of multiple sub-operands at the MI
level), this operand must match a ComplexPattern DAG pattern with the
correct number of output operands.
This commit extends TableGen to alternatively allow match a complex
operands against multiple separate operands at the DAG level.
This allows using Pat patterns to match pre-increment nodes like
pre_store (which must have separate operands at the DAG level) onto
an instruction pattern that uses a multi-operand memory operand,
like the following example on PowerPC (will be committed as a
follow-on patch):
def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst),
"stwu $rS, $dst", LdStStoreUpd, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff),
(STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>;
Here, the pair of "ptroff" and "ptrreg" operands is matched onto the
complex operand "dst" of class "memri" in the "STWU" instruction.
Approved by Jakob Stoklund Olesen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177428
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Ulrich Weigand [Tue, 19 Mar 2013 19:50:30 +0000 (19:50 +0000)]
Fix sub-operand size mismatch in tocentry operands.
The tocentry operand class refers to 64-bit values (it is only used in 64-bit,
where iPTR is a 64-bit type), but its sole suboperand is designated as 32-bit
type. This causes a mismatch to be detected at compile-time with the TableGen
patch I'll check in shortly.
To fix this, this commit changes the suboperand to a 64-bit type as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177427
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Ulrich Weigand [Tue, 19 Mar 2013 19:49:52 +0000 (19:49 +0000)]
Remove an invalid and unnecessary Pat pattern from the X86 backend:
def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
(MOV64rm tglobaltlsaddr :$dst)>;
This pattern is invalid because the MOV64rm instruction expects a
source operand of type "i64mem", which is a subclass of X86MemOperand
and thus actually consists of five MI operands, but the Pat provides
only a single MI operand ("tglobaltlsaddr" matches an SDnode of
type ISD::TargetGlobalTLSAddress and provides a single output).
Thus, if the pattern were ever matched, subsequent uses of the MOV64rm
instruction pattern would access uninitialized memory. In addition,
with the TableGen patch I'm about to check in, this would actually be
reported as a build-time error.
Fortunately, the pattern does in fact never match, for at least two
independent reasons.
First, the code generator actually never generates a pattern of the
form (load (X86Wrapper (tglobaltlsaddr))). For most combinations of
TLS and code models, (tglobaltlsaddr) represents just an offset that
needs to be added to some base register, so it is never directly
dereferenced. The only exception is the initial-exec model, where
(tglobaltlsaddr) refers to the (pc-relative) address of a GOT slot,
which *is* in fact directly dereferenced: but in that case, the
X86WrapperRIP node is used, not X86Wrapper, so the Pat doesn't match.
Second, even if some patterns along those lines *were* ever generated,
we should not need an extra Pat pattern to match it. Instead, the
original MOV64rm instruction pattern ought to match directly, since
it uses an "addr" operand, which is implemented via the SelectAddr
C++ routine; this routine is supposed to accept the full range of
input DAGs that may be implemented by a single mov instruction,
including those cases involving ISD::TargetGlobalTLSAddress (and
actually does so e.g. in the initial-exec case as above).
To avoid build breaks (due to the above-mentioned error) after the
TableGen patch is checked in, I'm removing this Pat here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177426
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Hal Finkel [Tue, 19 Mar 2013 18:51:05 +0000 (18:51 +0000)]
Prepare to make r0 an allocatable register on PPC
Currently the PPC r0 register is unconditionally reserved. There are two reasons
for this:
1. r0 is treated specially (as the constant 0) by certain instructions, and so
cannot be used with those instructions as a regular register.
2. r0 is used as a temporary register in the CR-register spilling process
(where, under some circumstances, we require two GPRs).
This change addresses the first reason by introducing a restricted register
class (without r0) for use by those instructions that treat r0 specially. These
register classes have a new pseudo-register, ZERO, which represents the r0-as-0
use. This has the side benefit of making the existing target code simpler (and
easier to understand), and will make it clear to the register allocator that
uses of r0 as 0 don't conflict will real uses of the r0 register.
Once the CR spilling code is improved, we'll be able to allocate r0.
Adding these extra register classes, for some reason unclear to me, causes
requests to the target to copy 32-bit registers to 64-bit registers. The
resulting code seems correct (and causes no test-suite failures), and the new
test case covers this new kind of asymmetric copy.
As r0 is still reserved, no functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177423
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Nadav Rotem [Tue, 19 Mar 2013 18:38:27 +0000 (18:38 +0000)]
Optimize sext <4 x i8> and <4 x i16> to <4 x i64>.
Patch by Ahmad, Muhammad T <muhammad.t.ahmad@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177421
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Jakob Stoklund Olesen [Tue, 19 Mar 2013 18:03:58 +0000 (18:03 +0000)]
Annotate X86InstrExtension.td with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177418
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Jakob Stoklund Olesen [Tue, 19 Mar 2013 18:03:55 +0000 (18:03 +0000)]
Annotate a lot of X86InstrInfo.td with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177417
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Chad Rosier [Tue, 19 Mar 2013 17:32:17 +0000 (17:32 +0000)]
[ms-inline asm] Move the size directive asm rewrite into the target specific
logic as a QOI cleanup.
rdar://
13445327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177413
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Eli Bendersky [Tue, 19 Mar 2013 16:04:19 +0000 (16:04 +0000)]
Update documentation of llvm-link to reflect recent cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177411
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Eli Bendersky [Tue, 19 Mar 2013 16:04:02 +0000 (16:04 +0000)]
Remove stale comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177410
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Alexey Samsonov [Tue, 19 Mar 2013 15:33:18 +0000 (15:33 +0000)]
Fix for r177390: map values are pointers, use DeleteContainerSeconds() instead of .clear()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177409
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Eli Bendersky [Tue, 19 Mar 2013 15:26:24 +0000 (15:26 +0000)]
The Linker interface has some dead code after the cleanup in r172749
(and possibly others). The attached patch removes it, and tries to
update comments accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177406
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Hal Finkel [Tue, 19 Mar 2013 15:23:39 +0000 (15:23 +0000)]
Cleanup PPC64 unaligned i64 load/store
Remove an accidentally-added instruction definition and add a comment in the
test case. This is in response to a post-commit review by Bill Schmidt.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177404
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Sean Silva [Tue, 19 Mar 2013 15:22:02 +0000 (15:22 +0000)]
[docs] Remove incorrect information about lit.
Lit does support redirects in the 2>&1 style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177403
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Dmitry Vyukov [Tue, 19 Mar 2013 10:24:42 +0000 (10:24 +0000)]
llvm-symbolizer: flush internal caches functionality
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177390
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David Tweed [Tue, 19 Mar 2013 10:16:40 +0000 (10:16 +0000)]
The testing to ensure a vector of zeros of type floating point isn't misclassified as negative zero can be simplified, as pointed out by Duncan Sands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177386
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Alexey Samsonov [Tue, 19 Mar 2013 10:10:03 +0000 (10:10 +0000)]
Enable -Wnon-virtual-dtor build warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177385
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Renato Golin [Tue, 19 Mar 2013 08:15:38 +0000 (08:15 +0000)]
Improve long vector sext/zext lowering on ARM
The ARM backend currently has poor codegen for long sext/zext
operations, such as v8i8 -> v8i32. This patch addresses this
by performing a custom expansion in ARMISelLowering. It also
adds/changes the cost of such lowering in ARMTTI.
This partially addresses PR14867.
Patch by Pete Couperus
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177380
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Hal Finkel [Tue, 19 Mar 2013 08:09:38 +0000 (08:09 +0000)]
Don't reserve R31 on PPC64 unless the frame pointer is needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177379
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Andrew Trick [Tue, 19 Mar 2013 05:10:27 +0000 (05:10 +0000)]
Revert "Cleanup some SCEV logic a bit."
This reverts commit
82cd8f7382322bee7a71cdc31f7a923c44d37d32.
Just add a comment instead!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177377
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Andrew Trick [Tue, 19 Mar 2013 04:14:59 +0000 (04:14 +0000)]
Cleanup some SCEV logic a bit.
Make the code more obvious to scan-build and humans.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177375
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Andrew Trick [Tue, 19 Mar 2013 04:14:57 +0000 (04:14 +0000)]
Tighten up an internal LSR API that should check for NULL.
No test case, but should fix a scan_build warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177374
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Nick Lewycky [Tue, 19 Mar 2013 01:37:55 +0000 (01:37 +0000)]
Emit the linkage name instead of the function name, when available. This means
that we'll prefer to emit the mangled C++ name (pending a clang change).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177371
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Hal Finkel [Mon, 18 Mar 2013 23:58:28 +0000 (23:58 +0000)]
Fix a sign-extension bug in PPCCTRLoops
Don't sign extend the immediate value from the OR instruction in
an LIS/OR pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177361
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Jakub Staszak [Mon, 18 Mar 2013 23:45:45 +0000 (23:45 +0000)]
Move #include of BitVector from .h to .cpp file.
Also remove unneeded #include and forward declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177357
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Jakub Staszak [Mon, 18 Mar 2013 23:40:46 +0000 (23:40 +0000)]
Add some constantness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177356
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Jakub Staszak [Mon, 18 Mar 2013 23:33:44 +0000 (23:33 +0000)]
Remove unneeded #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177351
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Jakub Staszak [Mon, 18 Mar 2013 23:33:14 +0000 (23:33 +0000)]
Make methods const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177350
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Jakub Staszak [Mon, 18 Mar 2013 23:31:30 +0000 (23:31 +0000)]
Make method private. Keep coding standard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177348
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Chad Rosier [Mon, 18 Mar 2013 23:31:24 +0000 (23:31 +0000)]
[ms-inline asm] Avoid emitting a redundant sizing directive, if we've already
parsed one. Test case coming shortly.
rdar://
13446980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177347
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Jakub Staszak [Mon, 18 Mar 2013 23:08:01 +0000 (23:08 +0000)]
Change NULL to 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177342
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Bill Wendling [Mon, 18 Mar 2013 23:04:39 +0000 (23:04 +0000)]
Register the flush function for each compile unit.
For each compile unit, we want to register a function that will flush that
compile unit. Otherwise, __gcov_flush() would only flush the counters within the
current compile unit, and not any outside of it.
PR15191 & <rdar://problem/
13167507>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177340
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Jakub Staszak [Mon, 18 Mar 2013 23:04:30 +0000 (23:04 +0000)]
Remove trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177339
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Hal Finkel [Mon, 18 Mar 2013 23:00:58 +0000 (23:00 +0000)]
Fix PPC unaligned 64-bit loads and stores
PPC64 supports unaligned loads and stores of 64-bit values, but
in order to use the r+i forms, the offset must be a multiple of 4.
Unfortunately, this cannot always be determined by examining the
immediate itself because it might be available only via a TOC entry.
In order to get around this issue, we additionally predicate the
selection of the r+i form on the alignment of the load or store
(forcing it to be at least 4 in order to select the r+i form).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177338
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Arnold Schwaighofer [Mon, 18 Mar 2013 22:47:09 +0000 (22:47 +0000)]
ARM cost model: Make some vector integer to float casts cheaper
The default logic marks them as too expensive.
For example, before this patch we estimated:
cost of 16 for instruction: %r = uitofp <4 x i16> %v0 to <4 x float>
While this translates to:
vmovl.u16 q8, d16
vcvt.f32.u32 q8, q8
All other costs are left to the values assigned by the fallback logic. Theses
costs are mostly reasonable in the sense that they get progressively more
expensive as the instruction sequences emitted get longer.
radar://
13445992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177334
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Arnold Schwaighofer [Mon, 18 Mar 2013 22:47:06 +0000 (22:47 +0000)]
ARM cost model: Correct cost for some cheap float to integer conversions
Fix cost of some "cheap" cast instructions. Before this patch we used to
estimate for example:
cost of 16 for instruction: %r = fptoui <4 x float> %v0 to <4 x i16>
While we would emit:
vcvt.s32.f32 q8, q8
vmovn.i32 d16, q8
vuzp.8 d16, d17
All other costs are left to the values assigned by the fallback logic. Theses
costs are mostly reasonable in the sense that they get progressively more
expensive as the instruction sequences emitted get longer.
radar://
13434072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177333
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Quentin Colombet [Mon, 18 Mar 2013 22:30:07 +0000 (22:30 +0000)]
Extend global merge pass to optionally consider global constant variables.
Also add some checks to not merge globals used within landing pad instructions or marked as "used".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177331
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Bill Schmidt [Mon, 18 Mar 2013 22:12:04 +0000 (22:12 +0000)]
Change test cases to handle unaligned references.
Hal Finkel recently added code to allow unaligned memory references
for PowerPC. Two tests were temporarily modified with
-disable-ppc-unaligned to keep them from failing. This patch adjusts
the expected code generation for the unaligned references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177328
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David Blaikie [Mon, 18 Mar 2013 22:08:16 +0000 (22:08 +0000)]
Remove unnecessary leading comment characters in lit-only file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177327
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Jakob Stoklund Olesen [Mon, 18 Mar 2013 22:01:35 +0000 (22:01 +0000)]
Add SchedRW annotations to most of X86InstrSSE.td.
We hitch a ride with the existing OpndItins class that was used to add
instruction itinerary classes in the many multiclasses in this file.
Use the link provided by the X86FoldableSchedWrite.Folded to find the
right SchedWrite for folded loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177326
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Jakob Stoklund Olesen [Mon, 18 Mar 2013 21:32:39 +0000 (21:32 +0000)]
Annotate X86 arithmetic instructions with SchedRW lists.
This new-style scheduling information is going to replace the
instruction iteneraries.
This also serves as a test case for Andy's fix in r177317.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177323
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Manman Ren [Mon, 18 Mar 2013 21:23:25 +0000 (21:23 +0000)]
Check whether a pointer is non-null (isKnownNonNull) in isKnownNonZero.
This handles the case where we have an inbounds GEP with alloca as the pointer.
This fixes the regression in PR12750 and rdar://
13286434.
Note that we can also fix this by handling some GEP cases in isKnownNonNull.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177321
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Andrew Trick [Mon, 18 Mar 2013 20:42:25 +0000 (20:42 +0000)]
TableGen fix for the new machine model.
Properly handle cases where a group of instructions have different
SchedRW lists with the same itinerary class.
This was supposed to work, but I left in an early break.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177317
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David Blaikie [Mon, 18 Mar 2013 20:31:44 +0000 (20:31 +0000)]
Include '.test' suffix in target specific lit configs that need it
Apparently my final cleanup to use a relevant suffix for these tests before
committing r176831 caused them to stop running since lit wasn't configured to
run tests with that suffix in those directories (why don't we just have a
global suffix list?). So, add the suffix to the relevant directories & fix the
test that has bitrotted over the last week due to my debug info schema changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177315
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Eric Christopher [Mon, 18 Mar 2013 20:21:47 +0000 (20:21 +0000)]
Make the fields in the diagram match the descriptive text above them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177314
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Bill Wendling [Mon, 18 Mar 2013 17:47:33 +0000 (17:47 +0000)]
Update
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177298
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Hal Finkel [Mon, 18 Mar 2013 17:40:46 +0000 (17:40 +0000)]
Fix 80-col. violations in PPCCTRLoops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177296
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Hal Finkel [Mon, 18 Mar 2013 17:40:44 +0000 (17:40 +0000)]
Fix large count and negative constant count handling in PPCCTRLoops
This commit fixes an assert that would occur on loops with large constant counts
(like looping for ((uint32_t) -1) iterations on PPC64). The existing code did
not handle counts that it computed to be negative (asserting instead), but
these can be created with valid inputs.
This bug was discovered by bugpoint while I was attempting to isolate a
completely different problem.
Also, in writing test cases for the negative-count problem, I discovered that
the ori/lsi handling was broken (there was a typo which caused the logic that
was supposed to detect these pairs and extract the iteration count to always
fail). This has now also been corrected (and is covered by one of the new test
cases).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177295
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Hal Finkel [Mon, 18 Mar 2013 17:40:27 +0000 (17:40 +0000)]
Cleanup initial-value constants in PPCCTRLoops
Because the initial-value constants had not been added to the list
of instructions considered for DCE the resulting code had redundant
constant-materialization instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177294
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Hans Wennborg [Mon, 18 Mar 2013 17:03:05 +0000 (17:03 +0000)]
Fix integer comparison in DIEInteger::BestForm.
The always-true "(int)Int == (signed)Int" comparison was found
while experimenting with a potential new Clang warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177290
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Matthew Curtis [Mon, 18 Mar 2013 13:08:24 +0000 (13:08 +0000)]
ReleaseNotes: Tweak hexagonv2/hexagonv3 removal note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177284
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Benjamin Kramer [Mon, 18 Mar 2013 12:14:30 +0000 (12:14 +0000)]
Remove default copy ctor/assignment, makes AttributeSet trivially copyable.
And enables SmallVector's pod optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177281
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David Tweed [Mon, 18 Mar 2013 12:07:24 +0000 (12:07 +0000)]
Initially forgotten-to-svn-add test case for r177279.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177280
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David Tweed [Mon, 18 Mar 2013 11:54:44 +0000 (11:54 +0000)]
The optimization a + (-0.0f) -> a was being misapplied to a + (+0.0f) in the vector case (because
we weren't differntiating floating-point zeroinitializers from other zero-initializers)
which was causing problems for code relying upon a + (+0.0f) to, eg, flush denormals to
0. Make the scalar and vector cases have the same behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177279
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Christian Konig [Mon, 18 Mar 2013 11:34:16 +0000 (11:34 +0000)]
R600/SI: implement indirect adressing for SI
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177277
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Christian Konig [Mon, 18 Mar 2013 11:34:10 +0000 (11:34 +0000)]
R600/SI: add float vector types
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177276
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Christian Konig [Mon, 18 Mar 2013 11:34:05 +0000 (11:34 +0000)]
R600/SI: add shl pattern
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177275
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Christian Konig [Mon, 18 Mar 2013 11:34:00 +0000 (11:34 +0000)]
R600/SI: add BUFFER_LOAD_DWORD pattern
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177274
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Christian Konig [Mon, 18 Mar 2013 11:33:55 +0000 (11:33 +0000)]
R600/SI: implement SI.load.const intrinsic
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177273
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Christian Konig [Mon, 18 Mar 2013 11:33:50 +0000 (11:33 +0000)]
R600/SI: enable all S_LOAD and S_BUFFER_LOAD opcodes
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177272
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Christian Konig [Mon, 18 Mar 2013 11:33:45 +0000 (11:33 +0000)]
R600/SI: fix inserting waits for all defines
Unfortunately the previous fix for inserting waits for unordered
defines wasn't sufficient, cause it's possible that even ordered
defines are only partially used (or not used at all).
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177271
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Kostya Serebryany [Mon, 18 Mar 2013 09:38:39 +0000 (09:38 +0000)]
[asan] when creating string constants, set unnamed_attr and align 1 so that equal strings are merged by the linker. Observed up to 1% binary size reduction. Thanks to Anton Korobeynikov for the suggestion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177264
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Chandler Carruth [Mon, 18 Mar 2013 08:36:46 +0000 (08:36 +0000)]
Mark internal classes as POD-like to get better behavior out of
SmallVector and DenseMap.
This speeds up SROA by 25% on PR15412.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177259
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Anton Korobeynikov [Mon, 18 Mar 2013 08:12:28 +0000 (08:12 +0000)]
TLS support for MinGW targets.
MinGW is almost completely compatible to MSVC, with the exception of the _tls_array global not being available.
Patch by David Nadlinger!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177257
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Anton Korobeynikov [Mon, 18 Mar 2013 08:10:10 +0000 (08:10 +0000)]
Windows TLS: Section name prefix to ensure correct order
The linker sorts the .tls$<xyz> sections by name, and we need
to make sure any extra sections we produce (e.g. for weak globals)
always end up between .tls$AAA and .tls$ZZZ, even if the name
starts with e.g. an underscore.
Patch by David Nadlinger!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177256
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Kostya Serebryany [Mon, 18 Mar 2013 08:05:29 +0000 (08:05 +0000)]
[asan] while generating the description of a global variable, emit the module name in a separate field, thus not duplicating this information if every description. This decreases the binary size (observed up to 3%). https://code.google.com/p/address-sanitizer/issues/detail?id=168 . This changes the asan API version. llvm-part
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177254
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Kostya Serebryany [Mon, 18 Mar 2013 07:33:49 +0000 (07:33 +0000)]
[asan] don't instrument functions with available_externally linkage. This saves a bit of compile time and reduces the number of redundant global strings generated by asan (https://code.google.com/p/address-sanitizer/issues/detail?id=167)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177250
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Jakob Stoklund Olesen [Mon, 18 Mar 2013 04:08:07 +0000 (04:08 +0000)]
Extract a method.
This computes the type of an instruction operand or result based on the
records in the instruction's ins and outs lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177244
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Craig Topper [Mon, 18 Mar 2013 03:34:55 +0000 (03:34 +0000)]
Post process ADC/SBB and use a shorter encoding if they use a sign extended immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177243
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Craig Topper [Mon, 18 Mar 2013 02:53:34 +0000 (02:53 +0000)]
Refactor some duplicated code into helper functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177242
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David Blaikie [Sun, 17 Mar 2013 21:32:54 +0000 (21:32 +0000)]
Fix the build broken in r177239
Seems some accidental C++11 crept in there. Reported by the C++98 buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177241
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Michael Gottesman [Sun, 17 Mar 2013 21:31:12 +0000 (21:31 +0000)]
Reduced dont-infinite-loop-during-block-escape-analysis.ll with bugpoint and moved it to retain-block-escape-analysis.ll.
*NOTE* I verified that the original bug behind
dont-infinite-loop-during-block-escape-analysis.ll occurs when using opt on
retain-block-escape-analysis.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177240
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David Blaikie [Sun, 17 Mar 2013 21:13:55 +0000 (21:13 +0000)]
Split out filename & directory from DIFile to start generalizing over DIScopes
This is the first step to making all DIScopes have a common metadata prefix (so
that things (using directives, for example) that can appear in any scope can be
added to that common prefix). DIFile is itself a DIScope so the common prefix
of all DIScopes cannot be a DIFile - instead it's the raw filename/directory
name pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177239
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David Blaikie [Sun, 17 Mar 2013 21:08:22 +0000 (21:08 +0000)]
Generalize debug info test to be resilient to changes in metadata node numbering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177238
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David Blaikie [Sun, 17 Mar 2013 20:28:12 +0000 (20:28 +0000)]
Improve DIFile debug info annotation by letting it fallback to DIScope
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177236
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Jakob Stoklund Olesen [Sun, 17 Mar 2013 17:26:09 +0000 (17:26 +0000)]
Use ArrayRef<MVT::SimpleValueType> when possible.
Not passing vector references around makes it possible to use
SmallVector in most places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177235
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Sylvestre Ledru [Sun, 17 Mar 2013 12:40:42 +0000 (12:40 +0000)]
To avoid symbol clash, undefine PPC here. PPC may be predefined on some hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177234
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Rafael Espindola [Sun, 17 Mar 2013 12:01:05 +0000 (12:01 +0000)]
Build LLVMgold.so on FreeBSD using cmake.
Patch by Stephen Checkoway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177233
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Michael Gottesman [Sun, 17 Mar 2013 08:42:58 +0000 (08:42 +0000)]
The promised test case for r175939.
This test makes sure that the ObjCARC escape analysis looks at the uses of
instructions which copy the block pointer value by checking all four cases where
that can occur.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177232
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Hal Finkel [Sun, 17 Mar 2013 04:43:44 +0000 (04:43 +0000)]
Improve PPC VR (Altivec) register spilling
This change cleans up two issues with Altivec register spilling:
1. The spilling code was inefficient (using two instructions, and add and a
load, when just one would do)
2. The code assumed that r0 would always be available (true for now, but this
will change)
The new code handles VR spilling just like GPR spills but forced into r+r mode.
As a result, when any VR spills are present, we must now always allocate the
register-scavenger spill slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177231
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